  GE   8  @0   (              ?                                                      S   edgeble,neural-compute-module-2-io edgeble,neural-compute-module-2 rockchip,rv1126           &            7Edgeble Neu2 IO Board      aliases          =/i2c@ff3f0000            B/mmc@ffc50000            G/serial@ff570000          cpus                                 cpu@f00          Ocpu          arm,cortex-a7            [            _psci             m               t                     cpu@f01          Ocpu          arm,cortex-a7            [           _psci             m                        cpu@f02          Ocpu          arm,cortex-a7            [           _psci             m                        cpu@f03          Ocpu          arm,cortex-a7            [           _psci             m                           arm-pmu          arm,cortex-a7-pmu         0          {          |          }          ~                              psci             arm,psci-1.0             fsmc       timer            arm,armv7-timer       0                                 
           n6       oscillator           fixed-clock          n6          xin24m                                 syscon@fe000000       &   rockchip,rv1126-grf syscon simple-mfd            [                        syscon@fe020000       )   rockchip,rv1126-pmugrf syscon simple-mfd             [                    io-domains        &   rockchip,rv1126-pmu-io-voltage-domain            okay                            	            
                              "           0           >           L            qos@fe860000             rockchip,rv1126-qos syscon           [                        qos@fe860080             rockchip,rv1126-qos syscon           [                       qos@fe860200             rockchip,rv1126-qos syscon           [                       qos@fe86c000             rockchip,rv1126-qos syscon           [                       interrupt-controller@feff0000            arm,gic-400          Z        o                           [          @     `                    	                    power-management@ff3e0000         &   rockchip,rv1126-pmu syscon simple-mfd            [>        power-controller          !   rockchip,rv1126-power-controller                                                     /   power-domain@15          [         8   m            r            u                  v                                   power-domain@16          [            m            o                                   i2c@ff3f0000          (   rockchip,rv1126-i2c rockchip,rk3399-i2c          [?                                            m            !      	  i2c pclk            default                                               okay                 pmic@20          rockchip,rk809           [             &               	                        rk808-clkout1 rk808-clkout2         default                                                                                  +           7           C           O   	        [                   regulators     DCDC_REG1           gvdd_npu_vepu             v                             	         ~          q   regulator-state-mem                   DCDC_REG2           gvdd_arm          v                                      p          q               regulator-state-mem                   DCDC_REG3           gvcc_ddr          v                       regulator-state-mem                   DCDC_REG4           gvcc3v3_sys           v                             2Z         2Z            	   regulator-state-mem                  ) 2Z         DCDC_REG5         
  gvcc_buck5            v                  !         !               regulator-state-mem                  ) !         LDO_REG1            gvcc_0v8          v                  5          5    regulator-state-mem                   LDO_REG2            gvcc1v8_pmu           v                  w@         w@               regulator-state-mem                  ) w@         LDO_REG3            gvcc0v8_pmu           v                  5          5    regulator-state-mem                  ) 5          LDO_REG4            gvcc_1v8          v                  w@         w@               regulator-state-mem                  ) w@         LDO_REG5          
  gvcc_dovdd                     w@         w@               regulator-state-mem                   LDO_REG6          	  gvcc_dvdd             O         O   regulator-state-mem                   LDO_REG7          	  gvcc_avdd             *         *   regulator-state-mem                   LDO_REG8          	  gvccio_sd             v                  w@         2Z               regulator-state-mem                   LDO_REG9          
  gvcc3v3_sd            v                  2Z         2Z   regulator-state-mem                   SWITCH_REG1         gvcc_5v0       SWITCH_REG2         gvcc_3v3          v                     +               serial@ff410000       &   rockchip,rv1126-uart snps,dw-apb-uart            [A                                 n6          m                     baudclk apb_pclk            E                    Jtx rx           default                    T           ^         	   disabled          clock-controller@ff480000            rockchip,rv1126-pmucru           [H                                    k                     clock-controller@ff490000            rockchip,rv1126-cru          [I              m           xin24m                                 k                     dma-controller@ff4e0000          arm,pl330 arm,primecell          [N    @                                      x                     m            	  apb_pclk                      serial@ff560000       &   rockchip,rv1126-uart snps,dw-apb-uart            [V                                 n6          m                    baudclk apb_pclk            E                    Jtx rx           default                          T           ^            okay       bluetooth            qcom,qca9377-bt          m                  !                        default            "           	                    serial@ff570000       &   rockchip,rv1126-uart snps,dw-apb-uart            [W                                 n6          m                    baudclk apb_pclk            E      	              Jtx rx           default            #        T           ^            okay          serial@ff580000       &   rockchip,rv1126-uart snps,dw-apb-uart            [X                                 n6          m                    baudclk apb_pclk            E            
        Jtx rx           default            $        T           ^         	   disabled          serial@ff590000       &   rockchip,rv1126-uart snps,dw-apb-uart            [Y                                 n6          m                    baudclk apb_pclk            E                    Jtx rx           default            %        T           ^         	   disabled          serial@ff5a0000       &   rockchip,rv1126-uart snps,dw-apb-uart            [Z                                 n6          m                     baudclk apb_pclk            E                    Jtx rx           default            &        T           ^         	   disabled          adc@ff5e0000          .   rockchip,rv1126-saradc rockchip,rk3399-saradc            [^                     (                       m      ,     
        saradc apb_pclk               ;        saradc-apb           okay                     timer@ff660000        ,   rockchip,rv1126-timer rockchip,rk3288-timer          [f                                  m           -        pclk timer        ethernet@ffc40000         &   rockchip,rv1126-gmac snps,dwmac-4.20a            [    @                 _          `           macirq eth_wake_irq                  @   m      ~                                               T  stmmaceth mac_clk_rx mac_clk_tx clk_mac_ref aclk_mac pclk_mac clk_mac_speed ptp_ref                     
  stmmaceth                             &   '        6   (        I   )         okay            \      ~                    l      }              sY@    }x@        input              *        rgmii              +        default            ,   -           *              mdio             snps,dwmac-mdio                              ethernet-phy@0        4   ethernet-phy-id001c.c916 ethernet-phy-ieee802.3-c22          [            default            .          N                                       *         stmmac-axi-config                                 $                                     '      rx-queues-config            .               (   queue0           tx-queues-config            D               )   queue0              mmc@ffc50000          0   rockchip,rv1126-dw-mshc rockchip,rk3288-dw-mshc          [    @                 N             m            r      s      t        biu ciu ciu-drive ciu-sample            Z           e         s   /            okay                                default            0   1   2   3           Z           +           
      mmc@ffc60000          0   rockchip,rv1126-dw-mshc rockchip,rk3288-dw-mshc          [    @                 L             m            l      m      n        biu ciu ciu-drive ciu-sample            Z           e          okay                                                    default            4   5   6   7           Z                                            mmc@ffc70000          0   rockchip,rv1126-dw-mshc rockchip,rk3288-dw-mshc          [    @                 M             m            o      p      q        biu ciu ciu-drive ciu-sample            Z           e         s   /            okay                                 -         :        P   8                 default            9   :   ;           Z                    	                                           pinctrl          rockchip,rv1126-pinctrl                    [                                     h   gpio@ff460000            rockchip,gpio-bank           [F                     "            m      &               o                    Z        o                     gpio@ff620000            rockchip,gpio-bank           [b                     #            m           (         o                    Z        o               D      gpio@ff630000            rockchip,gpio-bank           [c                     $            m           )         o                    Z        o         gpio@ff640000            rockchip,gpio-bank           [d                     %            m           *         o                    Z        o               !      gpio@ff650000            rockchip,gpio-bank           [e                     &            m     	      +         o                    Z        o         pcfg-pull-up                         @      pcfg-pull-down                       A      pcfg-pull-none                       <      pcfg-pull-none-drv-level-3                                  ?      pcfg-pull-up-drv-level-2                                    =      pcfg-pull-none-drv-level-0-smt                                            >      clk_out_ethernet       clk-out-ethernetm1-pins                     <            -         emmc       emmc-rstnout                        <            3      emmc-bus8                        =             =             =             =             =             =             =             =            0      emmc-clk                         =            2      emmc-cmd                         =            1         i2c0       i2c0-xfer                         >             >                     rgmii      rgmiim1-pins                        <            <            <            <            <            <            <            <            ?            ?            ?            ?            ?            ?            ,         sdmmc0     sdmmc0-bus4       @              =            =            =            =            6      sdmmc0-clk                      =            4      sdmmc0-cmd                	      =            5      sdmmc0-det                       <            7         sdmmc1     sdmmc1-bus4       @              =            =            =            =            ;      sdmmc1-clk                
      =            9      sdmmc1-cmd                      =            :         uart0      uart0-xfer                       @            @                  uart0-ctsn                      <                  uart0-rtsn                      <                     uart1      uart1m0-xfer                          @             @                     uart2      uart2m1-xfer                         @            @            #         uart3      uart3m0-xfer                         @            @            $         uart4      uart4m0-xfer                         @            @            %         uart5      uart5m0-xfer                         @            @            &         bt     bt-enable                        <            "         flash      flash-vol-sel                         <            B         pmic       pmic-int-l                 	       @                     wifi       wifi-enable-h                        <            C         ethernet       eth-phy-rst                       A            .            vcc5v0-sys-regulator             regulator-fixed         gvcc5v0_sys           v                  LK@         LK@                  vccio-flash-regulator            regulator-fixed                                    default            B        gvccio_flash          v                  w@         w@           +            
      pwrseq-sdio          mmc-pwrseq-simple            m             
  ext_clock           default            C           D                  8      chosen          	serial2:1500000n8            	#address-cells #size-cells compatible interrupt-parent model i2c0 mmc0 serial2 device_type reg enable-method clocks cpu-supply phandle interrupts interrupt-affinity clock-frequency clock-output-names #clock-cells status pmuio0-supply pmuio1-supply vccio1-supply vccio2-supply vccio3-supply vccio4-supply vccio5-supply vccio6-supply vccio7-supply interrupt-controller #interrupt-cells #power-domain-cells pm_qos rockchip,grf clock-names pinctrl-names pinctrl-0 rockchip,system-power-controller wakeup-source vcc1-supply vcc2-supply vcc3-supply vcc4-supply vcc5-supply vcc6-supply vcc7-supply vcc8-supply vcc9-supply regulator-name regulator-always-on regulator-boot-on regulator-initial-mode regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-off-in-suspend regulator-on-in-suspend regulator-suspend-microvolt dmas dma-names reg-shift reg-io-width #reset-cells #dma-cells arm,pl330-periph-burst enable-gpios max-speed vddxo-supply vddio-supply #io-channel-cells resets reset-names vref-supply interrupt-names snps,mixed-burst snps,tso snps,axi-config snps,mtl-rx-config snps,mtl-tx-config assigned-clocks assigned-clock-parents assigned-clock-rates clock_in_out phy-handle phy-mode phy-supply tx_delay rx_delay reset-assert-us reset-deassert-us reset-gpios snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,tx-queues-to-use fifo-depth max-frequency power-domains bus-width non-removable rockchip,default-sample-phase vmmc-supply vqmmc-supply cap-mmc-highspeed cap-sd-highspeed card-detect-delay sd-uhs-sdr12 sd-uhs-sdr25 sd-uhs-sdr104 cap-sdio-irq keep-power-in-suspend mmc-pwrseq rockchip,pmu ranges gpio-controller #gpio-cells bias-pull-up bias-pull-down bias-disable drive-strength input-schmitt-enable rockchip,pins enable-active-high gpio vin-supply stdout-path 