  BN   8  >   (            Z  >                             $    rockchip,rk3128-evb rockchip,rk3128                                  +         !   7Rockchip RK3128 Evaluation board       arm-pmu           arm,cortex-a7-pmu         0   =       L          M          N          O            H                  cpus                         +       cpu@f00          [cpu           arm,cortex-a7            g            k  @         y                s B@                              cpu@f01          [cpu           arm,cortex-a7            g                    cpu@f02          [cpu           arm,cortex-a7            g                    cpu@f03          [cpu           arm,cortex-a7            g                       timer             arm,armv7-timer       0   =                              
                     n6       oscillator            fixed-clock          n6          xin24m                                 syscon@100a0000       &    rockchip,rk3128-pmu syscon simple-mfd            g
           interrupt-controller@10139000             arm,cortex-a7-gic             g                           =      	                                                      usb@10180000          2    rockchip,rk3128-usb rockchip,rk3066-usb snps,dwc2            g              =       
            y             "otg         .otg         6         	  ;usb2-phy            Eokay            L         usb@101c0000              generic-ehci             g              =                  6   	        ;usb         Eokay          usb@101e0000              generic-ohci             g              =                   6   	        ;usb         Eokay          mmc@10214000          0    rockchip,rk3128-dw-mshc rockchip,rk3288-dw-mshc          g!@   @          =                    y           D      r      v        "biu ciu ciu-drive ciu-sample            X   
   
        ]rx-tx           g           rр              Q        reset         	  Edisabled          mmc@10218000          0    rockchip,rk3128-dw-mshc rockchip,rk3288-dw-mshc          g!   @          =                    y           E      s      w        "biu ciu ciu-drive ciu-sample            X   
           ]rx-tx           g           rр              R        reset         	  Edisabled          mmc@1021c000          0    rockchip,rk3128-dw-mshc rockchip,rk3288-dw-mshc          g!   @          =                    y           G      u      y        "biu ciu ciu-drive ciu-sample            X   
           ]rx-tx           g           rр              S        reset           Eokay                       default                        nand-controller@10500000          (    rockchip,rk3128-nfc rockchip,rk2928-nfc          gP    @          =                   y           C        "ahb nfc         default                                        	  Edisabled          clock-controller@20000000             rockchip,rk3128-cru          g                y           "xin24m                                                          #g                  syscon@20008000       &    rockchip,rk3128-grf syscon simple-mfd            g                           +                  usb2phy@17c           rockchip,rk3128-usb2phy          g  |            y              "phyclk           usb480m_phy                      Eokay       host-port            =       5         
  linestate                       Eokay                	      otg-port          $   =       #          3          4           otg-bvalid otg-id linestate                     Eokay                            timer@20044000        ,    rockchip,rk3128-timer rockchip,rk3288-timer          g @              =                   y     a      U        "pclk timer        timer@20044020        ,    rockchip,rk3128-timer rockchip,rk3288-timer          g @              =                   y     a      V        "pclk timer        timer@20044040        ,    rockchip,rk3128-timer rockchip,rk3288-timer          g @@             =       ;            y     a      W        "pclk timer        timer@20044060        ,    rockchip,rk3128-timer rockchip,rk3288-timer          g @`             =       <            y     a      X        "pclk timer        timer@20044080        ,    rockchip,rk3128-timer rockchip,rk3288-timer          g @             =       =            y     a      Y        "pclk timer        timer@200440a0        ,    rockchip,rk3128-timer rockchip,rk3288-timer          g @             =       >            y     a      Z        "pclk timer        watchdog@2004c000              rockchip,rk3128-wdt snps,dw-wdt          g              =       "            y     ?      	  Edisabled          pwm@20050000          (    rockchip,rk3128-pwm rockchip,rk3288-pwm          g               y     ^        default                             	  Edisabled          pwm@20050010          (    rockchip,rk3128-pwm rockchip,rk3288-pwm          g              y     ^        default                             	  Edisabled          pwm@20050020          (    rockchip,rk3128-pwm rockchip,rk3288-pwm          g               y     ^        default                             	  Edisabled          pwm@20050030          (    rockchip,rk3128-pwm rockchip,rk3288-pwm          g  0            y     ^        default                             	  Edisabled          i2c@20056000          (    rockchip,rk3128-i2c rockchip,rk3288-i2c          g `             =                  "i2c          y     M        default                                 +            Eokay       rtc@51            haoyu,hym8563            g   Q                      xin32k           i2c@2005a000          (    rockchip,rk3128-i2c rockchip,rk3288-i2c          g              =                  "i2c          y     N        default                                 +          	  Edisabled          i2c@2005e000          (    rockchip,rk3128-i2c rockchip,rk3288-i2c          g              =                  "i2c          y     O        default                                 +          	  Edisabled          serial@20060000       &    rockchip,rk3128-uart snps,dw-apb-uart            g               =                   n6          y      M     U        "baudclk apb_pclk            X   
      
           ]tx rx           default                   !                   '         	  Edisabled          serial@20064000       &    rockchip,rk3128-uart snps,dw-apb-uart            g @             =                   n6          y      N     V        "baudclk apb_pclk            X   
      
           ]tx rx           default            "                   '         	  Edisabled          serial@20068000       &    rockchip,rk3128-uart snps,dw-apb-uart            g              =                   n6          y      O     W        "baudclk apb_pclk            X   
      
           ]tx rx           default            #                   '         	  Edisabled          saradc@2006c000           rockchip,saradc          g              =                   y      [     >        "saradc apb_pclk               W        saradc-apb          1         	  Edisabled          i2c@20072000          (    rockchip,rk3128-i2c rockchip,rk3288-i2c          g               =                  "i2c          y     L        default            $                     +          	  Edisabled          spi@20074000          (    rockchip,rk3128-spi rockchip,rk3066-spi          g @             =                   y      A     R        "spiclk apb_pclk         X   
      
   	        ]tx rx           default            %   &   '   (   )                     +          	  Edisabled          dma-controller@20078000           arm,pl330 arm,primecell          g    @          =                              C         ^         y            	  "apb_pclk            u               
      pinctrl           rockchip,rk3128-pinctrl                                 +               gpio@2007c000             rockchip,gpio-bank           g              =       $            y     @                                                     ,      gpio@20080000             rockchip,gpio-bank           g               =       %            y     A                                               gpio@20084000             rockchip,gpio-bank           g @             =       &            y     B                                                     .      gpio@20088000             rockchip,gpio-bank           g              =       '            y     C                                               pcfg-pull-default                        +      pcfg-pull-none                       *      emmc       emmc-clk                        *                  emmc-cmd                        +                  emmc-cmd1                       +      emmc-pwr                        +      emmc-bus1                       +      emmc-bus4         @              +            +            +            +      emmc-bus8                       +            +            +            +            +            +            +            +                     gmac       rgmii-pins                      +      	      +            +            +            +            +            +            +            +            +            +            +            +            +            +      rmii-pins                       +            +            +            +            +            +            +            +            +            +         hdmi       hdmii2c-xfer                          *             *      hdmi-hpd                         *      hdmi-cec                         *         i2c0       i2c0-xfer                          *             *            $         i2c1       i2c1-xfer                         *             *                     i2c2       i2c2-xfer                        *            *                     i2c3       i2c3-xfer                         *             *                     i2s    i2s-bus       `               *       	      *             *             *             *             *      i2s1-bus          `               *            *            *            *            *            *         lcdc       lcdc-dclk                       *      lcdc-den                        *      lcdc-hsync                	      *      lcdc-vsync                
      *      lcdc-rgb24                      *            *            *            *            *            *            *            *            *            *            *            *            *            *         nfc    flash-ale                        *                  flash-cle                       *                  flash-wrn                       *                  flash-rdn                       *                  flash-rdy                       *                  flash-cs0                       *                  flash-dqs                       *                  flash-bus8                      *            *            *            *            *            *            *            *                     pwm0       pwm0-pin                         *                     pwm1       pwm1-pin                         *                     pwm2       pwm2-pin                         *                     pwm3       pwm3-pin                        *                     sdio       sdio-clk                         *      sdio-cmd                         +      sdio-pwren                       +      sdio-bus4         @              +            +            +            +         sdmmc      sdmmc-clk                       *      sdmmc-cmd                       +      sdmmc-wp                        +      sdmmc-pwren                     +      sdmmc-bus4        @              +            +            +            +         spdif      spdif-tx                        *         spi0       spi0-clk                        +            '      spi0-cs0                        +            (      spi0-tx               	      +            %      spi0-rx               
      +            &      spi0-cs1                        +            )      spi1-clk                         +      spi1-cs0                        +      spi1-tx                     +      spi1-rx                     +      spi1-cs1                        +      spi2-clk                   	      +      spi2-cs0                         +      spi2-tx                      +      spi2-rx                      +         uart0      uart0-xfer                       +            *                  uart0-cts                       *                   uart0-rts                        *            !         uart1      uart1-xfer                 	      +      
      +            "      uart1-cts                       *      uart1-rts                       *         uart2      uart2-xfer                       +            *            #      uart2-cts                        *      uart2-rts                        *         usb-host       host-vbus-drv                        *            /         usb-otg    otg-vbus-drv                          *            -            aliases         /pinctrl/gpio@2007c000          /pinctrl/gpio@20080000          /pinctrl/gpio@20084000          /pinctrl/gpio@20088000          /i2c@20056000           /mmc@1021c000         chosen          /serial@20068000          memory@60000000          [memory           g`   @         vcc5v0-otg-regulator              regulator-fixed            ,               default            -        vcc5v0_otg           LK@        . LK@                  vcc5v0-host-regulator             regulator-fixed            .               default            /        vcc5v0_host          F         LK@        . LK@         	compatible interrupt-parent #address-cells #size-cells model interrupts interrupt-affinity device_type reg clock-latency clocks operating-points #cooling-cells phandle arm,cpu-registers-not-fw-configured clock-frequency clock-output-names #clock-cells interrupt-controller #interrupt-cells clock-names dr_mode phys phy-names status vbus-supply dmas dma-names fifo-depth max-frequency resets reset-names bus-width pinctrl-names pinctrl-0 rockchip,grf #reset-cells assigned-clocks assigned-clock-rates interrupt-names #phy-cells #pwm-cells reg-io-width reg-shift #io-channel-cells arm,pl330-broken-no-flushp arm,pl330-periph-burst #dma-cells ranges gpio-controller #gpio-cells bias-pull-pin-default bias-disable rockchip,pins gpio0 gpio1 gpio2 gpio3 i2c1 mmc0 stdout-path gpio regulator-name regulator-min-microvolt regulator-max-microvolt regulator-always-on 