  8   8  L   (                                                                                 .   ,Toradex Colibri iMX8QXP on Colibri Iris Board         =   2toradex,colibri-imx8x-iris toradex,colibri-imx8x fsl,imx8qxp       aliases           =/bus@5b000000/ethernet@5b040000           G/bus@5b000000/ethernet@5b050000          Q/bus@5d000000/gpio@5d080000          W/bus@5d000000/gpio@5d090000          ]/bus@5d000000/gpio@5d0a0000          c/bus@5d000000/gpio@5d0b0000          i/bus@5d000000/gpio@5d0c0000          o/bus@5d000000/gpio@5d0d0000          u/bus@5d000000/gpio@5d0e0000          {/bus@5d000000/gpio@5d0f0000          /bus@5a000000/i2c@5a800000           /bus@5a000000/i2c@5a810000           /bus@5a000000/i2c@5a820000           /bus@5a000000/i2c@5a830000           /bus@5b000000/mmc@5b010000           /bus@5b000000/mmc@5b020000           /bus@5b000000/mmc@5b030000           /bus@5d000000/mailbox@5d1b0000           /bus@5d000000/mailbox@5d1c0000           /bus@5d000000/mailbox@5d1d0000           /bus@5d000000/mailbox@5d1e0000           /bus@5d000000/mailbox@5d1f0000           /bus@5a000000/serial@5a060000            /bus@5a000000/serial@5a070000            /bus@5a000000/serial@5a080000            /bus@5a000000/serial@5a090000             /vpu@2c000000/vpu-core@2d080000           /vpu@2c000000/vpu-core@2d090000           /vpu@2c000000/vpu-core@2d0a0000       "   /bus@5a000000/i2c@5a810000/rtc@68            /system-controller/rtc        cpus                                 cpu@0            cpu          2arm,cortex-a35                          psci                       +   @        =           J           W   @        i           v                                                    	      cpu@1            cpu          2arm,cortex-a35                         psci                       +   @        =           J           W   @        i           v                                                    
      cpu@2            cpu          2arm,cortex-a35                         psci                       +   @        =           J           W   @        i           v                                                          cpu@3            cpu          2arm,cortex-a35                         psci                       +   @        =           J           W   @        i           v                                                          l2-cache0            2cache                                           -   @        ?                       opp-table            2operating-points-v2                        opp-900000000               5          B@         I      opp-1200000000              G                   I                  interrupt-controller@51a00000            2arm,gic-v3               Q             Q                             !        6      	                    reserved-memory                                   A   decoder-boot@84000000                                  H      encoder-boot@86000000                                   H      decoder-rpc@92000000                                   H      dsp@92400000                @                  H      encoder-rpc@94400000                @       p           H         pmu          2arm,cortex-a35-pmu          6               psci             2arm,psci-1.0            smc       system-controller            2fsl,imx-scu         Otx0 rx0 gip3          $  Z                                 power-controller             2fsl,imx8qxp-scu-pd fsl,scu-pd           a                    clock-controller             2fsl,imx8qxp-clk fsl,scu-clk         u                    pinctrl          2fsl,imx8qxp-iomuxc          default                       P   ad7879intgrp                     !           '      adc0grp       0     d       `   c       `   h       `   g       `      atmeladaptergrp            N      !   M     !      atmelconnectorgrp                   !         !      canintgrp                    @      csictlgrp                                     csimclkgrp                   A      extio0grp              1     @      fec1grp       x     5          4          &       a   %     a   '       a   (       a   -       a   .       a   /       a   0      a           @      fec1slpgrp        x     5     A   4     A   &      A   %      A   '      A   (      A   -      A   .      A   /      A   0      A           A      flexcan0grp            j       !   i       !      flexcan1grp            l       !   k       !      flexcan2grp            n       !   m       !      gpioblongrp                  `      gpiohpdgrp             z             gpiokeysgrp               p A           R      hog0grp                  a             S                 a   ,                a             T                 a             U                 a   R                 a                                                               X                                 hog1grp                         hog2grp                         hogscfwgrp                          i2c0grp                 !        !           %      i2c0mipilvds0grp               t          u             i2c0mipilvds1grp               x          y             i2c1grp            v     !   w     !           *      lcdifgrp         ,     L      `   H      `   K      `   J      @         @   7      `         `   8      `   9      `   :      `   ;      `   <      `   =      `   >      `   ?      `   @      `   A      `   B      `   C      `   E      `   F      `   G      `   I      `   )      `   P      `      lpspi2grp         0     Y      !   Z      @   [      @   \      @                 lpspi2cs2grp               *      !      lpuart0grp        0     o          p          i         j                       lpuart2grp             r          q                        lpuart3grp             m         n                 !      lpuart3ctrlgrp        H     {          V          W                                                "      pciebgrp          $          a        a          `      pwmagrp                   a   `      `      pwmbgrp            M      `           J      pwmcgrp            N      `           L      pwmdgrp                   a   O      `           N      sai0grp       0     ^     @   a     @   ]     @   _     @      sgtl5000grp                  A      sgtl5000usbclkgrp              e      !           &      usb3503agrp                  a      usbcdetgrp             3     @      usbh1reggrp                 @      usdhc1grp              	      A   
       !          !          !          !          !          !          !          !          !          A          !           3      usdhc1-100mhzgrp               	      A   
       !          !          !          !          !          !          !          !          !          A          !           4      usdhc1-200mhzgrp               	      A   
       !          !          !          !          !          !          !          !          !          A          !           5      usdhc2gpiogrp                   !           9      usdhc2gpioslpgrp                     `           =      usdhc2grp         T           A          !           !   !       !   "       !   #       !          !           8      usdhc2-100mhzgrp          T           A          !           !   !       !   "       !   #       !          !           :      usdhc2-200mhzgrp          T           A          !           !   !       !   "       !   #       !          !           ;      usdhc2slpgrp          T           `         `          `   !      `   "      `   #      `          !           <      wifigrp                         gpioirisgrp       T                         R          U          T          ,         S                        uart1forceoffgrp                            uart23forceoffgrp              {                ocotp            2fsl,imx8qxp-scu-ocotp                                  keys          "   2fsl,imx8qxp-sc-key fsl,imx-sc-key              t      	  disabled          rtc          2fsl,imx8qxp-sc-rtc        watchdog          "   2fsl,imx8qxp-sc-wdt fsl,imx-sc-wdt              <      thermal-sensor        *   2fsl,imx8qxp-sc-thermal fsl,imx-sc-thermal                                  timer            2arm,armv8-timer       0  6                                 
         clock-xtal32k            2fixed-clock         u                       xtal_32KHz        clock-xtal24m            2fixed-clock         u            n6         xtal_24MHz        thermal-zones      cpu0-thermal                                 "     c   trips      trip0           2 _        >          passive                  trip1           2 (        >        	  critical             cooling-maps       map0            I         0  N   	   
                     bus@58000000             2simple-bus                                   AX       X         clock-img-ipg            2fixed-clock         u                     img_ipg_clk                  jpegdec@58400000            X@           0  6      5         6         7         8                                ]per ipg         i                     y        (                                    2nxp,imx8qxp-jpgdec          okay          jpegenc@58450000            XE           0  6      1         2         3         4                                ]per ipg         i                     y        (                                    2nxp,imx8qxp-jpgenc          okay          clock-controller@585d0000            2fsl,imx8qxp-lpcg            X]             u                                      0  img_jpeg_dec_lpcg_clk img_jpeg_dec_lpcg_ipg_clk                               clock-controller@585f0000            2fsl,imx8qxp-lpcg            X_             u                                      0  img_jpeg_enc_lpcg_clk img_jpeg_enc_lpcg_ipg_clk                                  vpu@2c000000                                     A,       ,                  ,                             	  disabled       mailbox@2d000000             2fsl,imx6sx-mu           -              6                                       	  disabled                     mailbox@2d020000             2fsl,imx6sx-mu           -             6                                       	  disabled                     mailbox@2d040000             2fsl,imx6sx-mu           -             6                                       	  disabled                     vpu-core@2d080000           -              2nxp,imx8q-vpu-decoder                        Otx0 tx1 rx        $  Z                                     	  disabled          vpu-core@2d090000           -	              2nxp,imx8q-vpu-encoder                        Otx0 tx1 rx        $  Z                                     	  disabled          vpu-core@2d0a0000           -
              2nxp,imx8q-vpu-encoder                        Otx0 tx1 rx        $  Z                                     	  disabled             bus@59000000             2simple-bus                                   AY       Y         clock-audio-ipg          2fixed-clock         u            '         audio_ipg_clk                    clock-controller@59590000            2fsl,imx8qxp-lpcg            YY             u                                 dsp_ram_lpcg_ipg_clk                          bus@5a000000             2simple-bus                                   AZ       Z         clock-dma-ipg            2fixed-clock         u            '         dma_ipg_clk            #      spi@5a000000             2fsl,imx7ulp-spi         Z                                        6      P                                             ]per ipg         i      5           y               5      	  disabled          spi@5a010000             2fsl,imx7ulp-spi         Z                                       6      Q                                             ]per ipg         i      6           y               6      	  disabled          spi@5a020000             2fsl,imx7ulp-spi         Z                                       6      R                                             ]per ipg         i      7           y               7        okay            default                                    spi@5a030000             2fsl,imx7ulp-spi         Z                                       6      S                                             ]per ipg         i      8           y               8      	  disabled          serial@5a060000         Z             6                                     	  ]ipg baud            i      9           yĴ               9        okay             2fsl,imx8qxp-lpuart          default                  serial@5a070000         Z             6                                     	  ]ipg baud            i      :           yĴ               :      	  disabled             2fsl,imx8qxp-lpuart        serial@5a080000         Z             6                                     	  ]ipg baud            i      ;           yĴ               ;        okay             2fsl,imx8qxp-lpuart          default                  serial@5a090000         Z	             6                                       	  ]ipg baud            i      <           yĴ               <        okay             2fsl,imx8qxp-lpuart          default            !   "      clock-controller@5a400000            2fsl,imx8qxp-lpcg            Z@             u                 5      #                        spi0_lpcg_clk spi0_lpcg_ipg_clk               5                 clock-controller@5a410000            2fsl,imx8qxp-lpcg            ZA             u                 6      #                        spi1_lpcg_clk spi1_lpcg_ipg_clk               6                 clock-controller@5a420000            2fsl,imx8qxp-lpcg            ZB             u                 7      #                        spi2_lpcg_clk spi2_lpcg_ipg_clk               7                 clock-controller@5a430000            2fsl,imx8qxp-lpcg            ZC             u                 8      #                        spi3_lpcg_clk spi3_lpcg_ipg_clk               8                 clock-controller@5a460000            2fsl,imx8qxp-lpcg            ZF             u                 9      #                     '  uart0_lpcg_baud_clk uart0_lpcg_ipg_clk                9                 clock-controller@5a470000            2fsl,imx8qxp-lpcg            ZG             u                 :      #                     '  uart1_lpcg_baud_clk uart1_lpcg_ipg_clk                :                 clock-controller@5a480000            2fsl,imx8qxp-lpcg            ZH             u                 ;      #                     '  uart2_lpcg_baud_clk uart2_lpcg_ipg_clk                ;                 clock-controller@5a490000            2fsl,imx8qxp-lpcg            ZI             u                 <      #                     '  uart3_lpcg_baud_clk uart3_lpcg_ipg_clk                <                  i2c@5a800000            Z    @         6                     $       $           ]per ipg         i      `           yn6               `        okay          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c                                            default            %   &   touchscreen@2c           2adi,ad7879-1            default            '           ,             (        6                            x                   
                      6           D         	  disabled             i2c@5a810000            Z    @         6                     )       )           ]per ipg         i      a           yn6               a        okay          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c                                            default            *   rtc@68        	   2st,m41t0               h         i2c@5a820000            Z    @         6                     +       +           ]per ipg         i      b           yn6               b      	  disabled          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c       i2c@5a830000            Z    @         6                     ,       ,           ]per ipg         i      c           yn6               c      	  disabled          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c       adc@5a880000             2nxp,imx8qxp-adc         \           Z             6                                  -       -           ]per ipg         i      e           yn6               e      	  disabled          can@5a8d0000             2fsl,imx8qm-flexcan          Z             6                                  .      .            ]ipg per         i      i           ybZ               i        n            }          	  disabled          can@5a8e0000             2fsl,imx8qm-flexcan          Z             6                                  .      .            ]ipg per         i      i           ybZ               j        n            }         	  disabled          can@5a8f0000             2fsl,imx8qm-flexcan          Z             6                                  .      .            ]ipg per         i      i           ybZ               k        n            }         	  disabled          clock-controller@5ac00000            2fsl,imx8qxp-lpcg            Z             u                 `      #                        i2c0_lpcg_clk i2c0_lpcg_ipg_clk               `           $      clock-controller@5ac10000            2fsl,imx8qxp-lpcg            Z             u                 a      #                        i2c1_lpcg_clk i2c1_lpcg_ipg_clk               a           )      clock-controller@5ac20000            2fsl,imx8qxp-lpcg            Z             u                 b      #                        i2c2_lpcg_clk i2c2_lpcg_ipg_clk               b           +      clock-controller@5ac30000            2fsl,imx8qxp-lpcg            Z             u                 c      #                        i2c3_lpcg_clk i2c3_lpcg_ipg_clk               c           ,      clock-controller@5ac80000            2fsl,imx8qxp-lpcg            Z             u                 e      #                        adc0_lpcg_clk adc0_lpcg_ipg_clk               e           -      clock-controller@5acd0000            2fsl,imx8qxp-lpcg            Z             u                 i      #   #                        5  can0_lpcg_pe_clk can0_lpcg_ipg_clk can0_lpcg_chi_clk                  i           .         bus@5b000000             2simple-bus                                   A[       [         clock-conn-axi           2fixed-clock         u            CU        conn_axi_clk               G      clock-conn-ahb           2fixed-clock         u            	!        conn_ahb_clk               H      clock-conn-ipg           2fixed-clock         u                    conn_ipg_clk               F      usb@5b0d0000          -   2fsl,imx7ulp-usb fsl,imx6ul-usb fsl,imx27-usb            [                          6                    /           0               1                                                         	  disabled          usbmisc@5b0d0200                     8   2fsl,imx7ulp-usbmisc fsl,imx7d-usbmisc fsl,imx6q-usbmisc         [               0      usbphy@5b100000          2fsl,imx7ulp-usbphy          [                1                      	  disabled               /      mmc@5b010000            6                  [                2      2       2           ]ipg ahb per                       okay          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc                                                "  default state_100mhz state_200mhz              3           4           5      mmc@5b020000            6                  [                6      6       6           ]ipg ahb per                       "           7           okay          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc                      G   (   	           P   7      (  default state_100mhz state_200mhz sleep            8   9           :   9           ;   9        \   <   =         f         q      mmc@5b030000            6                  [                >      >       >           ]ipg ahb per                     	  disabled          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc         ethernet@5b040000           [           0  6                                                 ?      ?      ?      ?            ]ipg ahb enet_clk_ref ptp            i                          y沀sY@        z                                    okay          .   2fsl,imx8qxp-fec fsl,imx8qm-fec fsl,imx6sx-fec           default sleep              @           A        rmii               B            mdio                                 ethernet-phy@2           2ethernet-phy-ieee802.3-c22             d                      B            ethernet@5b050000           [           0  6                                                C      C      C      C            ]ipg ahb enet_clk_ref ptp            i                          y沀sY@        z                                  	  disabled          .   2fsl,imx8qxp-fec fsl,imx8qm-fec fsl,imx6sx-fec         usb@5b110000             2fsl,imx8qm-usb3         [                                       A      (     D      D       D      D      D           ]lpm bus aclk ipg core           i                y沀                   	  disabled       usb@5b120000          
   2cdns,usb3           [     [     [             xhci dev otg                                                0  6                                            host peripheral otg wakeup             E        cdns3,usb3-phy                   	  disabled             usb-phy@5b160000             2nxp,salvo-phy           [                D           ]salvo_phy_clk                                  	  disabled               E      clock-controller@5b200000            2fsl,imx8qxp-lpcg            [              u                       F   G                        9  sdhc0_lpcg_per_clk sdhc0_lpcg_ipg_clk sdhc0_lpcg_ahb_clk                             2      clock-controller@5b210000            2fsl,imx8qxp-lpcg            [!             u                       F   G                        9  sdhc1_lpcg_per_clk sdhc1_lpcg_ipg_clk sdhc1_lpcg_ahb_clk                             6      clock-controller@5b220000            2fsl,imx8qxp-lpcg            ["             u                       F   G                        9  sdhc2_lpcg_per_clk sdhc2_lpcg_ipg_clk sdhc2_lpcg_ahb_clk                             >      clock-controller@5b230000            2fsl,imx8qxp-lpcg            [#             u         0                       G            F   F                                   enet0_lpcg_timer_clk enet0_lpcg_txc_sampling_clk enet0_lpcg_ahb_clk enet0_lpcg_rgmii_txc_clk enet0_lpcg_ipg_clk enet0_lpcg_ipg_s_clk                             ?      clock-controller@5b240000            2fsl,imx8qxp-lpcg            [$             u         0                       G            F   F                                   enet1_lpcg_timer_clk enet1_lpcg_txc_sampling_clk enet1_lpcg_ahb_clk enet1_lpcg_rgmii_txc_clk enet1_lpcg_ipg_clk enet1_lpcg_ipg_s_clk                             C      clock-controller@5b270000            2fsl,imx8qxp-lpcg            ['             u              H   F                    "  usboh3_ahb_clk usboh3_phy_ipg_clk                           1      clock-controller@5b280000            2fsl,imx8qxp-lpcg            [(             u                                    0                     F   F   F              M  usb3_app_clk usb3_lpm_clk usb3_ipg_clk usb3_core_pclk usb3_phy_clk usb3_aclk                            D         bus@5c000000             2simple-bus                                   A\       \         ddr-pmu@5c020000             2fsl,imx8-ddr-pmu            \             6                   bus@5d000000             2simple-bus                                    A]       ]                      clock-lsio-mem           2fixed-clock         u                     lsio_mem_clk          clock-lsio-bus           2fixed-clock         u                     lsio_bus_clk               Q      pwm@5d000000             2fsl,imx27-pwm           ]              ]ipg per            I      I           i                 yn6                    okay               J        default       pwm@5d010000             2fsl,imx27-pwm           ]             ]ipg per            K      K           i                 yn6                    okay               L        default       pwm@5d020000             2fsl,imx27-pwm           ]             ]ipg per            M      M           i                 yn6                    okay               N        default       pwm@5d030000             2fsl,imx27-pwm           ]             ]ipg per            O      O           i                 yn6                  	  disabled          gpio@5d080000           ]             6                   #        3            !                                   2fsl,imx8qxp-gpio fsl,imx35-gpio       P  ?   P      8      P      E      P      K      P      P      P      R          K SODIMM_70 SODIMM_60 SODIMM_58 SODIMM_78 SODIMM_72 SODIMM_80 SODIMM_46 SODIMM_62 SODIMM_48 SODIMM_74 SODIMM_50 SODIMM_52 SODIMM_54 SODIMM_66 SODIMM_64 SODIMM_68   SODIMM_82 SODIMM_56 SODIMM_28 SODIMM_30  SODIMM_61 SODIMM_103    SODIMM_25 SODIMM_27 SODIMM_100        gpio@5d090000           ]	             6                   #        3            !                                   2fsl,imx8qxp-gpio fsl,imx35-gpio       0  ?   P       Y   	   P   	   c      P      t          KSODIMM_86 SODIMM_92 SODIMM_90 SODIMM_88    SODIMM_59  SODIMM_6 SODIMM_8   SODIMM_2 SODIMM_4 SODIMM_34 SODIMM_32 SODIMM_63 SODIMM_55 SODIMM_33 SODIMM_35 SODIMM_36 SODIMM_38 SODIMM_21 SODIMM_19 SODIMM_140 SODIMM_142 SODIMM_196 SODIMM_194 SODIMM_186 SODIMM_188 SODIMM_138                     gpio@5d0a0000           ]
             6                   #        3            !                                   2fsl,imx8qxp-gpio fsl,imx35-gpio       0  ?   P       {      P      ~      P                 KSODIMM_23   SODIMM_144        gpio@5d0b0000           ]             6                   #        3            !                                   2fsl,imx8qxp-gpio fsl,imx35-gpio       0  ?   P             P            P                 KSODIMM_96 SODIMM_75 SODIMM_37 SODIMM_29      SODIMM_43 SODIMM_45 SODIMM_69 SODIMM_71 SODIMM_73 SODIMM_77 SODIMM_89 SODIMM_93 SODIMM_95 SODIMM_99 SODIMM_105 SODIMM_107 SODIMM_98 SODIMM_102 SODIMM_104 SODIMM_106              (   lvds-tx-on-hog           [                        d         gpio@5d0c0000           ]             6                   #        3            !                                   2fsl,imx8qxp-gpio fsl,imx35-gpio         ?   P              P            P      	      P            P            P            P            P      %           K   SODIMM_129 SODIMM_133 SODIMM_127 SODIMM_131             SODIMM_44  SODIMM_76 SODIMM_31 SODIMM_47 SODIMM_190 SODIMM_192 SODIMM_49 SODIMM_51 SODIMM_53       gpio@5d0d0000           ]             6                   #        3            !                                   2fsl,imx8qxp-gpio fsl,imx35-gpio       0  ?   P       (      P      ,      P   	   3         a  K SODIMM_57 SODIMM_65 SODIMM_85     SODIMM_135 SODIMM_137 UNUSABLE_SODIMM_180 UNUSABLE_SODIMM_184          gpio@5d0e0000           ]             6                   #        3            !                                   2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0f0000           ]             6                   #        3            !                                   2fsl,imx8qxp-gpio fsl,imx35-gpio       spi@5d120000                                       2nxp,imx8qxp-fspi            ]                   fspi_base fspi_mmap         6       \                                     ]fspi_en fspi                        	  disabled          mailbox@5d1b0000            ]             6                           	  disabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1c0000            ]             6                           -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu                     mailbox@5d1d0000            ]             6                           	  disabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1e0000            ]             6                           	  disabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1f0000            ]             6                           	  disabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d200000            ]              6                                         	  disabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d210000            ]!             6                                         	  disabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d280000            ](             6                                            2fsl,imx8qxp-mu fsl,imx6sx-mu          clock-controller@5d400000            2fsl,imx8qxp-lpcg            ]@             u         4                                Q                                       h  pwm0_lpcg_ipg_clk pwm0_lpcg_ipg_hf_clk pwm0_lpcg_ipg_s_clk pwm0_lpcg_ipg_slv_clk pwm0_lpcg_ipg_mstr_clk                          I      clock-controller@5d410000            2fsl,imx8qxp-lpcg            ]A             u         4                                Q                                       h  pwm1_lpcg_ipg_clk pwm1_lpcg_ipg_hf_clk pwm1_lpcg_ipg_s_clk pwm1_lpcg_ipg_slv_clk pwm1_lpcg_ipg_mstr_clk                          K      clock-controller@5d420000            2fsl,imx8qxp-lpcg            ]B             u         4                                Q                                       h  pwm2_lpcg_ipg_clk pwm2_lpcg_ipg_hf_clk pwm2_lpcg_ipg_s_clk pwm2_lpcg_ipg_slv_clk pwm2_lpcg_ipg_mstr_clk                          M      clock-controller@5d430000            2fsl,imx8qxp-lpcg            ]C             u         4                                Q                                       h  pwm3_lpcg_ipg_clk pwm3_lpcg_ipg_hf_clk pwm3_lpcg_ipg_s_clk pwm3_lpcg_ipg_slv_clk pwm3_lpcg_ipg_mstr_clk                          O      clock-controller@5d440000            2fsl,imx8qxp-lpcg            ]D             u         4                                Q                                       h  pwm4_lpcg_ipg_clk pwm4_lpcg_ipg_hf_clk pwm4_lpcg_ipg_s_clk pwm4_lpcg_ipg_slv_clk pwm4_lpcg_ipg_mstr_clk                     clock-controller@5d450000            2fsl,imx8qxp-lpcg            ]E             u         4                                Q                                       h  pwm5_lpcg_ipg_clk pwm5_lpcg_ipg_hf_clk pwm5_lpcg_ipg_s_clk pwm5_lpcg_ipg_slv_clk pwm5_lpcg_ipg_mstr_clk                     clock-controller@5d460000            2fsl,imx8qxp-lpcg            ]F             u         4                                Q                                       h  pwm6_lpcg_ipg_clk pwm6_lpcg_ipg_hf_clk pwm6_lpcg_ipg_s_clk pwm6_lpcg_ipg_slv_clk pwm6_lpcg_ipg_mstr_clk                     clock-controller@5d470000            2fsl,imx8qxp-lpcg            ]G             u         4                                Q                                       h  pwm7_lpcg_ipg_clk pwm7_lpcg_ipg_hf_clk pwm7_lpcg_ipg_s_clk pwm7_lpcg_ipg_slv_clk pwm7_lpcg_ipg_mstr_clk                        chosen          p/bus@5a000000/serial@5a090000         gpio-keys         
   2gpio-keys           default            R        okay       key-wakeup          |   
           (   
            Wake-Up                              regulator-module-3v3             2regulator-fixed         +V3.3            2Z         2Z           7      regulator-3v3            2regulator-fixed          2Z         2Z        3.3V             	interrupt-parent #address-cells #size-cells model compatible ethernet0 ethernet1 gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 i2c0 i2c1 i2c2 i2c3 mmc0 mmc1 mmc2 mu0 mu1 mu2 mu3 mu4 serial0 serial1 serial2 serial3 vpu_core0 vpu_core1 vpu_core2 rtc0 rtc1 device_type reg enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache clocks operating-points-v2 #cooling-cells phandle cache-level cache-unified opp-shared opp-hz opp-microvolt clock-latency-ns opp-suspend #interrupt-cells interrupt-controller interrupts ranges no-map mbox-names mboxes #power-domain-cells #clock-cells pinctrl-names pinctrl-0 fsl,pins linux,keycodes status timeout-sec #thermal-sensor-cells clock-frequency clock-output-names polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device clock-names assigned-clocks assigned-clock-rates power-domains clock-indices #mbox-cells cs-gpios touchscreen-max-pressure adi,resistance-plate-x adi,first-conversion-delay adi,acquisition-time adi,median-filter-size adi,averaging adi,conversion-interval #io-channel-cells fsl,clk-source fsl,scu-index fsl,usbphy fsl,usbmisc ahb-burst-config tx-burst-size-dword rx-burst-size-dword #index-cells bus-width non-removable no-sd no-sdio pinctrl-1 pinctrl-2 fsl,tuning-start-tap fsl,tuning-step cd-gpios vmmc-supply pinctrl-3 disable-wp no-1-8-v fsl,num-tx-queues fsl,num-rx-queues phy-mode phy-handle fsl,magic-packet max-speed reg-names interrupt-names phys phy-names cdns,on-chip-buff-size #phy-cells #pwm-cells gpio-controller #gpio-cells gpio-ranges gpio-line-names gpio-hog output-high stdout-path debounce-interval label linux,code wakeup-source regulator-name regulator-min-microvolt regulator-max-microvolt 