  U3   8  M   (              M`                                                      S   edgeble,neural-compute-module-2-io edgeble,neural-compute-module-2 rockchip,rv1126           &            7Edgeble Neu2 IO Board      aliases          =/i2c@ff3f0000            B/i2c@ff400000            G/serial@ff560000             O/serial@ff410000             W/serial@ff570000             _/serial@ff580000             g/serial@ff590000             o/serial@ff5a0000             w/mmc@ffc50000         cpus                                 cpu@f00          |cpu          arm,cortex-a7                        psci                                                 cpu@f01          |cpu          arm,cortex-a7                       psci                                     cpu@f02          |cpu          arm,cortex-a7                       psci                                     cpu@f03          |cpu          arm,cortex-a7                       psci                                        arm-pmu          arm,cortex-a7-pmu         0          {          |          }          ~                              psci             arm,psci-1.0             smc       timer            arm,armv7-timer       0                                 
           n6       display_subsystem            rockchip,display-subsystem                    oscillator           fixed-clock          n6          xin24m                           #      syscon@fe000000       &   rockchip,rv1126-grf syscon simple-mfd                              "      syscon@fe020000       )   rockchip,rv1126-pmugrf syscon simple-mfd                                 io-domains        &   rockchip,rv1126-pmu-io-voltage-domain           okay               	           
        +           9           G           U           c           q                       qos@fe860000             rockchip,rv1126-qos syscon                                   qos@fe860080             rockchip,rv1126-qos syscon                                  qos@fe860200             rockchip,rv1126-qos syscon                                  qos@fe86c000             rockchip,rv1126-qos syscon                                  qos@fe8a0000             rockchip,rv1126-qos syscon                                   qos@fe8a0080             rockchip,rv1126-qos syscon                                  qos@fe8a0100             rockchip,rv1126-qos syscon                                  qos@fe8a0180             rockchip,rv1126-qos syscon                                 interrupt-controller@feff0000            arm,gic-400                                                       @     `                    	                    power-management@ff3e0000         &   rockchip,rv1126-pmu syscon simple-mfd            >        power-controller          !   rockchip,rv1126-power-controller                                                     0   power-domain@15                   8               r            u                  v                                   power-domain@16                                  o                             power-domain@10             
      P                     Z                                         [                                            i2c@ff3f0000          (   rockchip,rv1126-i2c rockchip,rk3399-i2c          ?                                                        !      	  i2c pclk            default                                              okay                 pmic@20          rockchip,rk809                        &               	                        rk808-clkout1 rk808-clkout2         default                                       .           :           F           R           ^           j           v              
                       (   regulators     DCDC_REG1           vdd_npu_vepu                                          	         ~          q   regulator-state-mem          +         DCDC_REG2           vdd_arm                                                p          q               regulator-state-mem          +         DCDC_REG3           vcc_ddr                                 regulator-state-mem          D         DCDC_REG4           vcc3v3_sys                                        2Z         2Z            
   regulator-state-mem          D        \ 2Z         DCDC_REG5         
  vcc_buck5                              !         !               regulator-state-mem          D        \ !         LDO_REG1            vcc_0v8                            5          5    regulator-state-mem          +         LDO_REG2            vcc1v8_pmu                             w@         w@            	   regulator-state-mem          D        \ w@         LDO_REG3            vcc0v8_pmu                             5          5    regulator-state-mem          D        \ 5          LDO_REG4            vcc_1v8                            w@         w@               regulator-state-mem          D        \ w@         LDO_REG5          
  vcc_dovdd                     w@         w@               regulator-state-mem          +         LDO_REG6          	  vcc_dvdd             O         O   regulator-state-mem          +         LDO_REG7          	  vcc_avdd             *         *   regulator-state-mem          +         LDO_REG8          	  vccio_sd                               w@         2Z               regulator-state-mem          +         LDO_REG9          
  vcc3v3_sd                              2Z         2Z   regulator-state-mem          +         SWITCH_REG1         vcc_5v0       SWITCH_REG2         vcc_3v3                               5               i2c@ff400000          (   rockchip,rv1126-i2c rockchip,rk3399-i2c          @                                                        "      	  i2c pclk            default                                            	  disabled          serial@ff410000       &   rockchip,rv1126-uart snps,dw-apb-uart            A                                 n6                               baudclk apb_pclk            x                    }tx rx           default                                         	  disabled          pwm@ff430020          (   rockchip,rv1126-pwm rockchip,rk3328-pwm          C           	  pwm pclk                         #        default            !                 	  disabled          clock-controller@ff480000            rockchip,rv1126-pmucru           H                "                                         clock-controller@ff490000            rockchip,rv1126-cru          I                 #        xin24m             "                                         dma-controller@ff4e0000          arm,pl330 arm,primecell          N    @                                                                       	  apb_pclk                      pwm@ff550030          (   rockchip,rv1126-pwm rockchip,rk3328-pwm          U 0         	  pwm pclk                   '                $        default                    okay          serial@ff560000       &   rockchip,rv1126-uart snps,dw-apb-uart            V                                 n6                              baudclk apb_pclk            x                    }tx rx           default            %   &   '                              okay       bluetooth            qcom,qca9377-bt             (              )                        default            *           
                    serial@ff570000       &   rockchip,rv1126-uart snps,dw-apb-uart            W                                 n6                              baudclk apb_pclk            x      	              }tx rx           default            +                              okay          serial@ff580000       &   rockchip,rv1126-uart snps,dw-apb-uart            X                                 n6                              baudclk apb_pclk            x            
        }tx rx           default            ,                            	  disabled          serial@ff590000       &   rockchip,rv1126-uart snps,dw-apb-uart            Y                                 n6                              baudclk apb_pclk            x                    }tx rx           default            -                            	  disabled          serial@ff5a0000       &   rockchip,rv1126-uart snps,dw-apb-uart            Z                                 n6                               baudclk apb_pclk            x                    }tx rx           default            .                            	  disabled          adc@ff5e0000          .   rockchip,rv1126-saradc rockchip,rk3399-saradc            ^                     (           	                  ,     
        saradc apb_pclk               ;        "saradc-apb          okay            .         timer@ff660000        ,   rockchip,rv1126-timer rockchip,rk3288-timer          f                                             -        pclk timer        vop@ffb00000             rockchip,rv1126-vop               
                    ;           aclk_vop dclk_vop hclk_vop                                     "axi ahb dclk                                      :   /        A   0   
      	  disabled       port                                             endpoint@0                     endpoint@1                          iommu@ffb00f00           rockchip,iommu                               ;           aclk iface                               O            A   0   
      	  disabled                /      ethernet@ffc40000         &   rockchip,rv1126-gmac snps,dwmac-4.20a                @                 _          `           \macirq eth_wake_irq            "      @         ~                                               T  stmmaceth mac_clk_rx mac_clk_tx clk_mac_ref aclk_mac pclk_mac clk_mac_speed ptp_ref                     
  "stmmaceth            l         }           1           2           3        okay                  ~                          }              sY@    }x@        input              4        rgmii              5        default            6   7   8   9        $   *        -      mdio             snps,dwmac-mdio                              ethernet-phy@0        4   ethernet-phy-id001c.c916 ethernet-phy-ieee802.3-c22                      default            :        6  N         F         X                     4         stmmac-axi-config           d           t                                                1      rx-queues-config                           2   queue0           tx-queues-config                           3   queue0              mmc@ffc50000          0   rockchip,rv1126-dw-mshc rockchip,rk3288-dw-mshc              @                 N                         r      s      t        biu ciu ciu-drive ciu-sample                                A   0           okay                                default            ;   <   =           Z        	   5                 mmc@ffc60000          0   rockchip,rv1126-dw-mshc rockchip,rk3288-dw-mshc              @                 L                         l      m      n        biu ciu ciu-drive ciu-sample                                okay                        "         4        E           default            >   ?   @   A           Z         W         d         q                 mmc@ffc70000          0   rockchip,rv1126-dw-mshc rockchip,rk3288-dw-mshc              @                 M                         o      p      q        biu ciu ciu-drive ciu-sample                                A   0           okay                        4                             B                 default            C   D   E           Z         q        	   
                                           spi@ffc90000             rockchip,sfc                 @                 P                 v        Ĵ         clk_sfc hclk_sfc                   v              A   0           okay            default            F                             flash@0          jedec,spi-nor                                                       pinctrl          rockchip,rv1126-pinctrl            "                                                gpio@ff460000            rockchip,gpio-bank           F                     "                  &                                                                gpio@ff620000            rockchip,gpio-bank           b                     #                       (                                                    O      gpio@ff630000            rockchip,gpio-bank           c                     $                       )                                              gpio@ff640000            rockchip,gpio-bank           d                     %                       *                                                    )      gpio@ff650000            rockchip,gpio-bank           e                     &                 	      +                                              pcfg-pull-up                         J      pcfg-pull-down                       I      pcfg-pull-none           -            G      pcfg-pull-none-drv-level-3           -        :               L      pcfg-pull-up-drv-level-2                     :               H      pcfg-pull-none-drv-level-0-smt           -        :             I            K      clk_out_ethernet       clk-out-ethernetm1-pins         ^            G            9         emmc       emmc-bus8           ^             H             H             H             H             H             H             H             H            ;      emmc-clk            ^             H            =      emmc-cmd            ^             H            <         fspi       fspi-pins         `  ^            I             J             J            J             J            J            F         i2c0       i2c0-xfer            ^             K             K                     i2c2       i2c2-xfer            ^             K             K                     pwm2       pwm2m0-pins         ^             G            !         pwm11      pwm11m0-pins            ^            G            $         rgmii      rgmiim1-miim             ^            G            G            6      rgmiim1-bus2          `  ^            G            G            G            L            L            L            7      rgmiim1-bus4          `  ^            G            G            G            L            L            L            8         sdmmc0     sdmmc0-bus4       @  ^            H            H            H            H            @      sdmmc0-clk          ^            H            >      sdmmc0-cmd          ^      	      H            ?      sdmmc0-det          ^             G            A         sdmmc1     sdmmc1-bus4       @  ^            H            H            H            H            E      sdmmc1-clk          ^      
      H            C      sdmmc1-cmd          ^            H            D         uart0      uart0-xfer           ^            J            J            %      uart0-ctsn          ^            G            &      uart0-rtsn          ^            G            '         uart1      uart1m0-xfer             ^             J             J                      uart2      uart2m1-xfer             ^            J            J            +         uart3      uart3m0-xfer             ^            J            J            ,         uart4      uart4m0-xfer             ^            J            J            -         uart5      uart5m0-xfer             ^            J            J            .         bt     bt-enable           ^             G            *         flash      flash-vol-sel           ^              G            M         pmic       pmic-int-l          ^       	       J                     wifi       wifi-enable-h           ^             G            N         ethernet       eth-phy-rst         ^              I            :            vccio-flash-regulator            regulator-fixed          l                          default            M        vccio_flash                            w@         w@           5                  pwrseq-sdio          mmc-pwrseq-simple               (         
  ext_clock           default            N        X   O                  B      chosen          serial2:1500000n8         vcc12v-dcin-regulator            regulator-fixed         vcc12v_dcin                                                   P      vcc5v0-sys-regulator             regulator-fixed         vcc5v0_sys                             LK@         LK@           P                  v3v3-sys-regulator           regulator-fixed       	  v3v3_sys                               2Z         2Z                    	#address-cells #size-cells compatible interrupt-parent model i2c0 i2c2 serial0 serial1 serial2 serial3 serial4 serial5 mmc0 device_type reg enable-method clocks cpu-supply phandle interrupts interrupt-affinity clock-frequency ports clock-output-names #clock-cells status pmuio0-supply pmuio1-supply vccio1-supply vccio2-supply vccio3-supply vccio4-supply vccio5-supply vccio6-supply vccio7-supply interrupt-controller #interrupt-cells #power-domain-cells pm_qos rockchip,grf clock-names pinctrl-names pinctrl-0 rockchip,system-power-controller wakeup-source vcc1-supply vcc2-supply vcc3-supply vcc4-supply vcc5-supply vcc6-supply vcc7-supply vcc8-supply vcc9-supply regulator-name regulator-always-on regulator-boot-on regulator-initial-mode regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-off-in-suspend regulator-on-in-suspend regulator-suspend-microvolt dmas dma-names reg-shift reg-io-width #pwm-cells #reset-cells #dma-cells arm,pl330-periph-burst enable-gpios max-speed vddxo-supply vddio-supply #io-channel-cells resets reset-names vref-supply iommus power-domains #iommu-cells interrupt-names snps,mixed-burst snps,tso snps,axi-config snps,mtl-rx-config snps,mtl-tx-config assigned-clocks assigned-clock-parents assigned-clock-rates clock_in_out phy-handle phy-mode phy-supply tx_delay rx_delay reset-assert-us reset-deassert-us reset-gpios snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,tx-queues-to-use fifo-depth max-frequency bus-width non-removable rockchip,default-sample-phase vmmc-supply vqmmc-supply cap-mmc-highspeed cap-sd-highspeed card-detect-delay sd-uhs-sdr12 sd-uhs-sdr25 sd-uhs-sdr104 cap-sdio-irq keep-power-in-suspend mmc-pwrseq spi-max-frequency spi-rx-bus-width spi-tx-bus-width rockchip,pmu ranges gpio-controller #gpio-cells bias-pull-up bias-pull-down bias-disable drive-strength input-schmitt-enable rockchip,pins enable-active-high gpio vin-supply stdout-path 