 :   8    (            R                              .    radxa,nio-12l mediatek,mt8395 mediatek,mt8195                                    +            7Radxa NIO 12L         	   =embedded       aliases          J/soc/dp-intf@1c015000            S/soc/dp-intf@1c113000            \/soc/dpi@1c112000            a/soc/mailbox@10320000            f/soc/mailbox@10330000            k/soc/hdmi-tx@1c300000            q/soc/hdr-engine@1c114000             x/soc/mutex@1c016000          /soc/mutex@1c101000          /soc/vpp-merge@1c10c000          /soc/vpp-merge@1c10d000          /soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000            /soc/i2c@11e02000           /soc/i2c@11e03000           /soc/i2c@11e04000           /soc/i2c@11e00000           /soc/i2c@11e01000           /soc/ethernet@11021000          $/soc/serial@11001100            ,/soc/serial@11001200            4/soc/spi@11010000           9/soc/spi@11012000         cpus                         +       cpu@0           >cpu           arm,cortex-a55          J            Npsci            \               pec3@          4                                    @                                 @                                                    &         cpu@100         >cpu           arm,cortex-a55          J           Npsci            \               pec3@          4                                    @                                 @                                                    &         cpu@200         >cpu           arm,cortex-a55          J           Npsci            \               pec3@          4                                    @                                 @                                                    &         cpu@300         >cpu           arm,cortex-a55          J           Npsci            \               pec3@          4                                    @                                 @                                                    &         cpu@400         >cpu           arm,cortex-a78          J           Npsci            \              pf                                               @                                 @                      	                      
        &         cpu@500         >cpu           arm,cortex-a78          J           Npsci            \              pf                                               @                                 @                      	                      
        &         cpu@600         >cpu           arm,cortex-a78          J           Npsci            \              pf                                               @                                 @                      	                      
        &         cpu@700         >cpu           arm,cortex-a78          J           Npsci            \              pf                                               @                                 @                      	                      
        &         cpu-map    cluster0       core0           .         core1           .         core2           .         core3           .         core4           .         core5           .         core6           .         core7           .               idle-states         2psci       cpu-retention-l           arm,idle-state          ?           V        g   2        x   _          D        &         cpu-retention-b           arm,idle-state          ?           V        g   -        x                     &         cpu-off-l             arm,idle-state          ?          V        g   7        x             H        &         cpu-off-b             arm,idle-state          ?          V        g   2        x                     &            l2-cache0             cache                                    @                                       &         l2-cache1             cache                                    @                                       &   	      l3-cache              cache                                     @                            &            dsu-pmu           arm,dsu-pmu                                                                fail          dmic-codec            dmic-codec                        2        &         mt8195-sound                       okay              mediatek,mt8195_mt6359           7mt8395-evk          default                  ,  Headphone Headphone L Headphone Headphone R                    &      headphone-dai-link        
  -DL_SRC_BE      codec           7                hdmi-dai-link           -ETDM3_OUT_BE       codec           7                   fixed-factor-clock-13m            fixed-factor-clock          A            N           U           _           jclk13m          &   0      oscillator-26m            fixed-clock         A            p        jclk26m          &         oscillator-32k            fixed-clock         A            p           jclk32k          &         performance-controller@11bc10             mediatek,cpufreq-hw          J                 0               }           &         opp-table-gpu             operating-points-v2                  &   ~   opp-390000000               >         	h      opp-410000000               p         	      opp-431000000                        	      opp-473000000               1h@         	<      opp-515000000               F         	<      opp-556000000               !#          	Ҧ      opp-598000000               #         	      opp-640000000               &%          	      opp-670000000               'c         
      opp-700000000               )'          
L      opp-730000000               +         
}      opp-760000000               -L          
`      opp-790000000               /q         
4      opp-820000000               05                opp-850000000               2         @      opp-880000000               4s          q         pmu-a55           arm,cortex-a55-pmu                                        pmu-a78           arm,cortex-a78-pmu                                        psci              arm,psci-1.0            Usmc       timer             arm,armv8-timer                   @                                               
               &         soc                      +             simple-bus                                             interrupt-controller@c000000              arm,gic-v3                                                      J                                          	               &      ppi-partitions     interrupt-partition-0                               &         interrupt-partition-1                               &               syscon@10000000            mediatek,mt8195-topckgen syscon         J                      A           &         syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          J                     A                      &          syscon@10003000           mediatek,mt8195-pericfg syscon          J     0                A           &   I      pinctrl@10005000              mediatek,mt8195-pinctrl         J     P                                                                                                         B  iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            &        6           B                                                                 N        &      audio-default-pins          &      pins-cmd-dat            r  F  E  G  H  I  J  K         dsi0-backlight-pins         &      pins-backlight-en           r  k          y         eth-default-pins            &   E   pins-cc         r  U  V  W  X                 pins-mdio           r  Y  Z               pins-power          r  [   \          y      pins-rst            r  ]       pins-rxd            r  Q  R  S  T      pins-txd            r  M  N  O  P                    eth-sleep-pins          &   F   pins-cc         r  U   V   W   X       pins-mdio           r  Y   Z                         pins-rxd            r  Q   R   S   T       pins-txd            r  M   N   O   P          gpio-keys-pins          &      pins            r  j                            hdmi-vreg-pins          &   j   pins-pwr            r                    hdmi-pins           &      pins-hotplug            r                  pins-ddc            r  "  #           
      pins-cec            r  !                  i2c2-pins           &   l   pins-bus            r                                            i2c4-pins           &   o   pins-bus            r                                 i2c6-pins           &   d   pins            r                      mmc0-default-pins           &   N   pins-clk            r  z           f                 pins-cmd-dat          $  r  ~  }  |  {  w  v  u  t  y           e                          pins-rst            r  x           e                    mmc0-uhs-pins           &   O   pins-clk            r  z           f                 pins-cmd-dat          $  r  ~  }  |  {  w  v  u  t  y           e                          pins-ds         r             f                 pins-rst            r  x           e                    mmc1-default-pins           &   R   pins-clk            r  o           f                 pins-cmd-dat            r  n  p  q  r  s           e                             mmc1-detect-pins            &   S   pins-insert         r                     mt6360-pins         &   e   pins-irq            r  d   e                            panel-pins          &      pins-rst            r  l                   pcie0-default-pins          &   _   pins-bus            r                        pcie1-default-pins          &   b   pins-bus            r                         pwm0-pins           &      pins-disp-pwm           r  a         spi1-default-pins           &   ?   pins-bus            r                          spi2-default-pins           &   @   pins-bus            r                          touch-pins          &      pins-touch-int          r                           pins-touch-rst          r            y         uart0-pins          &   :   pins-bus            r  b  c         uart1-pins          &   ;   pins-bus            r  f  g         usb3p0-default-pins         &   J   pins-vbus           r  ?                  usb2p0-default-pins         &   Z   pins-iddig          r                          pins-vbus           r                    wifi-vreg-pins          &      pins-wifi-pmu-en            r  A          y      pins-wifi-vreg-en           r  C             syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            J     `                &      power-controller          !    mediatek,mt8195-power-controller                         +                       &   3   power-domain@8          J                        +                                  &      power-domain@9          J   	        N                    mfg alt         )                         +                          !        &      power-domain@10         J   
                  power-domain@11         J                     power-domain@12         J                     power-domain@13         J                     power-domain@14         J                           power-domain@15         J           N                        	      @      A      K         "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "           vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           )                         +                  power-domain@16         J         8  N         #   $   #   %   #   &   #   '   #   (   #   )      D  vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         )                         +                  power-domain@17         J           N         $      $           vppsys1 vppsys1-0 vppsys1-1         )                      power-domain@22         J            N   %      %      %      %         $  wepsys-0 wepsys-1 wepsys-2 wepsys-3         )                      power-domain@23         J           N   &            vdec0-0         )                         +                   power-domain@24         J           N   '            vdec1-0         )                      power-domain@25         J           N   (            vdec2-0         )                         power-domain@26         J           N   )            venc0-larb          )                         +                   power-domain@27         J           N   *            venc1-larb          )                         power-domain@18         J            N         +       +      +         &  vdosys1 vdosys1-0 vdosys1-1 vdosys1-2           )                         +                  power-domain@19         J           )                      power-domain@20         J           )                      power-domain@21         J           N      Q        hdmi_tx                      power-domain@28         J           N   ,       ,   
        img-0 img-1         )                         +                  power-domain@29         J                     power-domain@30         J           N         ,      -           ipe ipe-0 ipe-1         )                         power-domain@31         J         (  N   .       .      .      .      .           cam-0 cam-1 cam-2 cam-3 cam-4           )                         +                  power-domain@32         J                      power-domain@33         J   !                  power-domain@34         J   "                           power-domain@0          J            )                      power-domain@1          J           )                      power-domain@2          J                     power-domain@3          J                     power-domain@4          J           N      5      7        csi_rx_top csi_rx_top1                    power-domain@5          J           N   /           ether                     power-domain@6          J           N      X      n        adsp adsp1                       +            )                  power-domain@7          J            N      g      "      n       2        audio audio1 audio2 audio3          )                               watchdog@10007000             mediatek,mt8195-wdt          ;        J     p                           &   8      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           J                     A           &         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         J    p                      	               N   0        &         pwrap@10024000            mediatek,mt8195-pwrap syscon            J    @                pwrap                                 N                     	  spi wrap            S      $        c              &      pmic              mediatek,mt6359                             z                            &      adc           mediatek,mt6359-auxadc                     &         audio-codec           mediatek,mt6359-codec           &         regulators            mediatek,mt6359-regulator      buck_vs1            vs1          5          !                             &         buck_vgpu11         vgpu11                    7                              5                           &         buck_vmodem         vmodem                               *                   &         buck_vpu            vpu                   7                              5                           &         buck_vcore          vcore                                                    5                           &         buck_vs2            vs2          5          j                              &         buck_vpa            vpa                    7          ,        &         buck_vproc2         vproc2                    7           L                   5                           &         buck_vproc1         vproc1                    7           L                   5                           &         buck_vcore_sshub            vcore_sshub                   7        &         buck_vgpu11_sshub           vgpu11_sshub                      7        &         ldo_vaud18          vaud18           w@         w@                            &         ldo_vsim1           vsim1                     /M`        &         ldo_vibr            vibr             O         2Z        &   m      ldo_vrf12           vrf12                                       &         ldo_vusb            vusb             -         -                           &   K      ldo_vsram_proc2         vsram_proc2                               L                            &         ldo_vio18           vio18                                                &         ldo_vcamio          vcamio                                     &         ldo_vcn18           vcn18            w@         w@                   &         ldo_vfe28           vfe28            *         *           x        &         ldo_vcn13           vcn13                              &         ldo_vcn33_1_bt          vcn33_1_bt           *         5g        &         ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g        &         ldo_vaux18          vaux18           w@         w@                            &         ldo_vsram_others            vsram_others             q         q                              &   !      ldo_vefuse          vefuse                            &        ldo_vxo22           vxo22            w@         !                 &        ldo_vrfck           vrfck            `                 &        ldo_vrfck_1         vrfck                     j         &        ldo_vbif28          vbif28           *         *                   &        ldo_vio28           vio28            *         2Z                 &        ldo_vemc            vemc             ,@          2Z        &        ldo_vemc_1          vemc             &%         2Z        &   P      ldo_vcn33_2_bt          vcn33_2_bt           2Z         2Z        &        ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g        &  	      ldo_va12            va12             O                           &  
      ldo_va09            va09             5          O        &        ldo_vrf18           vrf18                     P        &        ldo_vsram_md          	  vsram_md                                  *                            &        ldo_vufs            vufs                              &   Q      ldo_vm18            vm18                                       &        ldo_vbbck           vbbck                     O                 &        ldo_vsram_proc1         vsram_proc1                               L                            &        ldo_vsim2           vsim2                     /M`        &        ldo_vsram_others_sshub          vsram_others_sshub                             &           rtc           mediatek,mt6358-rtc         &        keys              mediatek,mt6359-keys            M           f            &     power-key           y   t               home            y   f               spmi@10027000             mediatek,mt8195-spmi             J    p                            pmif spmimst            N                     E      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         S      $        c                           +            &     pmic@6            mediatek,mt6315-regulator           J               &     regulators     vbuck1          Vbcpu                     7                   5                           &   
            pmic@7            mediatek,mt6315-regulator           J               &     regulators     vbuck1          Vgpu                      7                   5                  &                  infra-iommu@10315000              mediatek,mt8195-iommu-infra         J    1P       P       P                                                                                      &   \      mailbox@10320000              mediatek,mt8195-gce         J    2        @                                          N               &         mailbox@10330000              mediatek,mt8195-gce         J    3        @                                          N               &         scp@10500000              mediatek,mt8195-scp       0  J    P             r             p                 sram cfg l1tcm                               okay               1        mediatek/mt8195/scp.img         &         clock-controller@10720000             mediatek,mt8195-scp_adsp            J    r                 A           &   2      dsp@10803000              mediatek,mt8195-dsp          J    0                           	  cfg sram          ,  N      X         n         2          #      K  adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             3           rx tx              4   5        okay               6   7        &         mailbox@10816000              mediatek,mt8195-adsp-mbox                       J    `                                     &   4      mailbox@10817000              mediatek,mt8195-adsp-mbox                       J    p                                     &   5      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           J                                   3                 6                  8         	  audiosys            N                                                   g      "      #      n      e      a      b      c      d       2   2            clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp          okay               9        &         serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           J                                           N                	  baud bus            okay               :        default         &        serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           J                                           N                	  baud bus            okay               ;        default         &        serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           J                                           N                	  baud bus          	  disabled            &        serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           J                                          N                	  baud bus          	  disabled            &        serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           J                                          N                	  baud bus          	  disabled            &        serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           J                                          N                	  baud bus          	  disabled            &        auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           J                      N               main                     	  disabled            &        syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           J     0                A           &   /      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            J                                           N                           parent-clk sel-clk spi-clk        	  disabled            &        thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         J                                           N                                  <   =      $  lvts-calib-data-1 lvts-calib-data-2         -           &         svs@1100bc00              mediatek,mt8195-svs         J                                           N               main               >   <      (  svs-calibration-data t-calibration-data                        svs_rst         &         pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           J                                              3           C           N      *       0        main mm       	  disabled            &         pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           J                                          C           N      +       N        main mm       	  disabled            &  !      spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            J                                           N                   3        parent-clk sel-clk spi-clk          okay               ?        default         N            &  "      spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            J                                           N                   4        parent-clk sel-clk spi-clk          okay               @        default         N            &  #      spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            J    0                                      N                   5        parent-clk sel-clk spi-clk        	  disabled            &  $      spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            J                                          N                   <        parent-clk sel-clk spi-clk        	  disabled            &  %      spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            J                                          N                   =        parent-clk sel-clk spi-clk        	  disabled            &  &      spi@1101d000              mediatek,mt8195-spi-slave           J                                          N       R        spi         S              c            	  disabled            &  '      spi@1101e000              mediatek,mt8195-spi-slave           J                                          N       S        spi         S              c            	  disabled            &  (      ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           J           @                              bmacirq        .  axi apb mac_main ptp_ref rmii_internal mac_cg         0  N   /       /         R      S      T   /           S      R      S      T        c                             3           r               A           B           C                                          okay            rgmii-rxid             D        default sleep              E           F                                  ]            0      N          &  )   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916            J           &   D         stmmac-axi-config           E           U           e                                 &   A      rx-queues-config            o                    &   B   queue0                             queue1                             queue2                             queue3                                tx-queues-config                                &   C   queue0                                        queue1                                       queue2                                       queue3                                             usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           J            -     >              	  mac ippc                                 ?                      +                                 N       /             B        sys_ck ref_ck mcu_ck            	   G      H                    	   I      g        okay            default            J        	host             	8        	H   K        &  *   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          J                       mac                               S      ,      -        c                  $  N       /                      B      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         okay            	V   L        &  +      port       endpoint            	b   M        &   h            mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          J    #                                                    N                            source hclk source_cg           okay            default state_uhs              N           O        	r           	|         	 L         	         	         	         	         	         	         	        	   P        
   Q        &  ,      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          J    $                                                    N                    $        source hclk source_cg           S              c              okay            default state_uhs              R   S           R        	r           	|          
        
                   
)         	         
0         
=        	   T        
   U        &  -      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          J    %                                                    N                     I        source hclk source_cg           S               c            	  disabled            &  .      ufshci@11270000           mediatek,mt8195-ufshci          J    '        #                               	   V      @  N       ?       @       A       6       7       8       Z       ]      X  ufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @  
K                                                                         
Y        okay            
r   P        
}   Q        &  /      thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            J    '                                      N                                 <   =      $  lvts-calib-data-1 lvts-calib-data-2         -           &         usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           J    )             )>              	  mac ippc                                 	   W           S      .      /        c                  $  N   /                     /         $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         	   I      h                 okay             
        	H   K        	V   X        
           &  0      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           J    *       -    *>              	  mac ippc                        *        ?                      +                                S      0        c              N   /            /           sys_ck ref_ck mcu_ck            	   Y                    	   I      i        okay            default            Z        	H   K        &  1   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          J                       mac                              S      1        c              N   /           sys_ck          okay            	V   X        &  2         usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           J    +       -    +>              	  mac ippc                        +        ?                      +                                S      2        c              N   /            /   	        sys_ck ref_ck mcu_ck            	   [                    	   I      j      	  disabled            &  3   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          J                       mac                              S      3        c              N   /   	        sys_ck        	  disabled            &  4         pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           >pci                      +           J    /        @       	  pcie-mac                                 
             8                                                              
       \              
          0  N       V       #       &       +       K   /         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          S      G        c              	   ]      	  
pcie-phy               3                       
                     `  
                  ^                      ^                     ^                     ^           okay            default            _        &  5   interrupt-controller                                             &   ^         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           >pci                      +           J    /       @       	  pcie-mac                                 
             8         $       $                  $       $                 
       \              
          (  N       W          X          Q   /         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          S      H        c              	   `         	  
pcie-phy               3                      
                     `  
                  a                      a                     a                     a           okay            default            b        &  6   interrupt-controller                                             &   a         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         J    2                      9               N      o   /      /           spi sf axi                       +          	  disabled            &  7      efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            J                                  +           &  8   usb3-tx-imp@184,1           J             
               &   u      usb3-rx-imp@184,2           J             
              &   t      usb3-intr@185           J             
              &   s      usb3-tx-imp@186,1           J             
               &   r      usb3-rx-imp@186,2           J             
              &   q      usb3-intr@187           J             
              &   p      usb2-intr-p0@188,1          J             
               &  9      usb2-intr-p1@188,2          J             
              &  :      usb2-intr-p2@189,1          J             
              &  ;      usb2-intr-p3@189,2          J             
              &  <      pciephy-rx-ln1@190,1            J             
               &   |      pciephy-tx-ln1-nmos@190,2           J             
              &   {      pciephy-tx-ln1-pmos@191,1           J             
               &   z      pciephy-rx-ln0@191,2            J             
              &   y      pciephy-tx-ln0-nmos@192,1           J             
               &   x      pciephy-tx-ln0-pmos@192,2           J             
              &   w      pciephy-glb-intr@193            J             
               &   v      dp-data@1ac         J             &         lvts1-calib@1bc         J             &   <      lvts2-calib@1d0         J     8        &   =      svs-calib@580           J     d        &   >      socinfo-data1@7a0           J              t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay            &  =   usb-phy@0           J               N              ref                    &   Y         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                              	  disabled            &  >   usb-phy@0           J               N              ref                    &   [         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         J                     N           jmipi_tx0_pll            A                      	  disabled            &         dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         J                     N           jmipi_tx1_pll            A                      	  disabled            &         i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          J                 "                                     U           N   c           ;      	  main dma                         +          	  disabled            &  ?      i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          J                "                                      U           N   c          ;      	  main dma                         +            okay            p            d        default         &  @   pmic@34           mediatek,mt6360         J   4              e           bIRQB                                   e        &  A   charger           mediatek,mt6360-chg          @   usb-otg-vbus-regulator          usb-otg-vbus             C(         X        &   L         regulator             mediatek,mt6360-regulator           '   f        7   g   buck1         	  emi_vdd2                               5                           &  B      buck2         	  emi_vddq                               5                           &   g      ldo1            ext_lcd_3v3          2Z         2Z        5                        &  C      ldo2            panel1_p1v8          w@         w@        5               &  D      ldo3            vmc_pmu          O         6        5               &   U      ldo5          	  vmch_pmu             2Z         2Z        5                        &   T      ldo6            mt6360_ldo6                              5               &  E      ldo7            emi_vmddr_en                                 5                        &  F         typec             mediatek,mt6360-tcpc                  d           bPD_IRQB    connector             usb-c-connector         GUSB-C           Mdual            W         idual            tsink            "d        ",   ports                        +       port@0          J       endpoint            	b   h        &   M         port@2          J      endpoint            	b   i        &   n                        i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          J                 "                                     U           N   c          ;      	  main dma                         +          	  disabled            &  G      clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          J    0                A           &   c      hdmi-phy@11d5f000             mediatek,mt8195-hdmi-phy            J                     N      P                           pll_ref 26m pll1 pll2           jhdmi_txpll          A                           
                   okay            default            j        &         i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          J                 "                                      U           N   k           ;      	  main dma                         +          	  disabled            &  H      i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          J                "                                      U           N   k          ;      	  main dma                         +          	  disabled            &  I      i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          J                 "                                     U           N   k          ;      	  main dma                         +            okay            p            l        default         &  J   typec-mux@48              ite,it5205          J   H                          
r   m   port       endpoint            	b   n        &   i               i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          J    0            "                                     U           N   k          ;      	  main dma                         +          	  disabled            &  K      i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          J    @            "                                      U           N   k          ;      	  main dma                         +            okay            p            o        default         &  L      clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          J    P                A           &   k      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                   3           okay            &  M   usb-phy@0           J               N                 ref da_ref                     &   W      usb-phy@700         J              N                    ref da_ref             p   q   r        intr rx_imp tx_imp                     &   `         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay            &  N   usb-phy@0           J               N                 ref da_ref                     &   G      usb-phy@700         J              N                    ref da_ref             s   t   u        intr rx_imp tx_imp                     &   H         phy@11e80000              mediatek,mt8195-pcie-phy            J                     sif            v   w   x   y   z   {   |      G  glb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1             3                       okay            &   ]      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           J                     N            
  unipro mp                       okay            &   V      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           J             @         N   }          0                                                 bjob mmu gpu            ~      (     3   
   3      3      3      3           core0 core1 core2 core3 core4           okay                        &  O      clock-controller@13fbf000             mediatek,mt8195-mfgcfg          J                    A           &   }      syscon@14000000           mediatek,mt8195-vppsys0 syscon          J                      A                                 &   "      dma-controller@14001000           mediatek,mt8195-mdp3-rdma           J                                          $              8              3           E              N   "         <                                                       L         display@14002000              mediatek,mt8195-mdp3-fg         J                                            N   "          display@14003000              mediatek,mt8195-mdp3-stitch         J     0                         0            N   "         display@14004000              mediatek,mt8195-mdp3-hdr            J     @                         @            N   "   "      display@14005000              mediatek,mt8195-mdp3-aal            J     P                      F                        P            N   "   
           3         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           J     `                         `            $    %        N   "         display@14007000              mediatek,mt8195-mdp3-tdshp          J     p                         p            N   "   #      display@14008000              mediatek,mt8195-mdp3-color          J                           I                                    N   "   $           3         display@14009000              mediatek,mt8195-mdp3-ovl            J                           J                                    N   "   %           3           E            display@1400a000              mediatek,mt8195-mdp3-padding            J                                          N   "              3         display@1400b000              mediatek,mt8195-mdp3-tcc            J                                          N   "         dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         J                                          $    +        N   "           E                 3           L         mutex@1400f000            mediatek,mt8195-vpp-mutex           J                           P                                    N   "              3         smi@14010000              mediatek,mt8195-smi-sub-common          J                     N   "      "      "           apb smi gals0           W              3           &         smi@14011000              mediatek,mt8195-smi-sub-common          J                    N   "      "      "           apb smi gals0           W              3           &         smi@14012000              mediatek,mt8195-smi-common-vpp          J                      N   "      "      "      "           apb smi gals0 gals1            3           &         larb@14013000             mediatek,mt8195-smi-larb            J    0                d           W           N   "      "           apb smi            3           &         iommu@14018000            mediatek,mt8195-iommu-vpp           J                  8  u                                                        R               N   "           bclk                          3           &         clock-controller@14e00000             mediatek,mt8195-wpesys          J                     A           &   %      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         J                     A           &  P      clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         J    0                A           &  Q      larb@14e04000             mediatek,mt8195-smi-larb            J    @                d           W           N   %      %           apb smi            3           &         larb@14e05000             mediatek,mt8195-smi-larb            J    P                d           W           N   %      %      "           apb smi gals               3           &         syscon@14f00000           mediatek,mt8195-vppsys1 syscon          J                     A                 	               &   $      mutex@14f01000            mediatek,mt8195-vpp-mutex           J                          {                     	              N   $   '           3         larb@14f02000             mediatek,mt8195-smi-larb            J                     d           W           N   $      $      "           apb smi gals               3           &         larb@14f03000             mediatek,mt8195-smi-larb            J    0                d           W           N   $      $      "           apb smi gals               3           &         display@14f06000              mediatek,mt8195-mdp3-split          J    `                      	  `            N   $      $   +   $   ,           3         display@14f07000              mediatek,mt8195-mdp3-tcc            J    p                      	  p            N   $         dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           J                          	              $            N   $           E                 3           L         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           J                          	              $            N   $   
        E                 3           L         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           J                          	              $            N   $           E                 3           L         display@14f0b000              mediatek,mt8195-mdp3-fg         J                          	              N   $   	      display@14f0c000              mediatek,mt8195-mdp3-fg         J                          	              N   $         display@14f0d000              mediatek,mt8195-mdp3-fg         J                          	              N   $         display@14f0e000              mediatek,mt8195-mdp3-hdr            J                          	              N   $         display@14f0f000              mediatek,mt8195-mdp3-hdr            J                          	              N   $         display@14f10000              mediatek,mt8195-mdp3-hdr            J                           
               N   $          display@14f11000              mediatek,mt8195-mdp3-aal            J                          i                     
              N   $              3         display@14f12000              mediatek,mt8195-mdp3-aal            J                           j                     
               N   $              3         display@14f13000              mediatek,mt8195-mdp3-aal            J    0                      k                     
  0            N   $   !           3         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           J    @                      
  @            $            N   $         display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           J    P                      
  P            $            N   $   $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           J    `                      
  `            $            N   $   %      display@14f17000              mediatek,mt8195-mdp3-tdshp          J    p                      
  p            N   $         display@14f18000              mediatek,mt8195-mdp3-tdshp          J                          
              N   $   (      display@14f19000              mediatek,mt8195-mdp3-tdshp          J                          
              N   $   )      display@14f1a000              mediatek,mt8195-mdp3-merge          J                          
              N   $              3         display@14f1b000              mediatek,mt8195-mdp3-merge          J                          
              N   $              3         display@14f1c000              mediatek,mt8195-mdp3-color          J                          t                     
              N   $              3         display@14f1d000              mediatek,mt8195-mdp3-color          J                          
                    u               N   $              3         display@14f1e000              mediatek,mt8195-mdp3-color          J                          v                     
              N   $              3         display@14f1f000              mediatek,mt8195-mdp3-ovl            J                          w                     
              N   $               3           E            display@14f20000              mediatek,mt8195-mdp3-padding            J                                          N   $              3         display@14f21000              mediatek,mt8195-mdp3-padding            J                                        N   $              3         display@14f22000              mediatek,mt8195-mdp3-padding            J                                          N   $              3         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         J    0                        0            $            N   $           E                 3           L         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         J    @                        @            $            N   $           E                 3           L         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         J    P                        P            $            N   $           E                 3           L         clock-controller@15000000             mediatek,mt8195-imgsys          J                      A           &   ,      larb@15001000             mediatek,mt8195-smi-larb            J                     d   	        W           N   ,       ,       ,   
        apb smi gals               3           &         smi@15002000              mediatek,mt8195-smi-sub-common          J                      N   ,      ,      "           apb smi gals0           W              3           &         smi@15003000              mediatek,mt8195-smi-sub-common          J     0                N   ,       ,       ,   
        apb smi gals0           W              3           &         clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         J                     A           &         larb@15120000             mediatek,mt8195-smi-larb            J                     d   
        W           N   ,                  apb smi            3           &         clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          J                     A           &  R      clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         J    "                 A           &         larb@15230000             mediatek,mt8195-smi-larb            J    #                 d           W           N   ,                  apb smi            3           &         clock-controller@15330000             mediatek,mt8195-ipesys          J    3                 A           &   -      larb@15340000             mediatek,mt8195-smi-larb            J    4                 d           W           N   -      -           apb smi            3           &         clock-controller@16000000             mediatek,mt8195-camsys          J                      A           &   .      larb@16001000             mediatek,mt8195-smi-larb            J                     d           W           N   .       .       .           apb smi gals               3           &         larb@16002000             mediatek,mt8195-smi-larb            J                      d           W           N   .      .           apb smi            3           &         smi@16004000              mediatek,mt8195-smi-sub-common          J     @                N   .       .       .           apb smi gals0           W              3           &         smi@16005000              mediatek,mt8195-smi-sub-common          J     P                N   .      .      "           apb smi gals0           W              3           &         larb@16012000             mediatek,mt8195-smi-larb            J                     d           W           N                      apb smi            3            &         larb@16013000             mediatek,mt8195-smi-larb            J    0                d           W           N                      apb smi            3            &         larb@16014000             mediatek,mt8195-smi-larb            J    @                d           W           N                      apb smi            3   !        &         larb@16015000             mediatek,mt8195-smi-larb            J    P                d           W           N                      apb smi            3   !        &         clock-controller@1604f000             mediatek,mt8195-camsys_rawa         J                    A           &         clock-controller@1606f000             mediatek,mt8195-camsys_yuva         J                    A           &         clock-controller@1608f000             mediatek,mt8195-camsys_rawb         J                    A           &         clock-controller@160af000             mediatek,mt8195-camsys_yuvb         J    
                A           &         clock-controller@16140000             mediatek,mt8195-camsys_mraw         J                     A           &         larb@16141000             mediatek,mt8195-smi-larb            J                    d           W           N   .              .           apb smi gals               3   "        &         larb@16142000             mediatek,mt8195-smi-larb            J                     d           W           N                      apb smi            3   "        &         clock-controller@17200000             mediatek,mt8195-ccusys          J                      A           &         larb@17201000             mediatek,mt8195-smi-larb            J                     d           W           N                      apb smi            3           &         video-codec@18000000              mediatek,mt8195-vcodec-dec          8           E                          +            J                   @                                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         J                       E                   N      A   &      &                 sel vdec lat top            S      A        c                 3         video-codec@10000             mediatek,mtk-vcodec-lat         J                                         0  E                                        N      A   &      &                 sel vdec lat top            S      A        c                 3         video-codec@25000             mediatek,mtk-vcodec-core            J     P                                   P  E                                                           N      A   '      '                 sel vdec lat top            S      A        c                 3            larb@1800d000             mediatek,mt8195-smi-larb            J                     d           W           N   &       &            apb smi            3           &         larb@1800e000             mediatek,mt8195-smi-larb            J                     d           W           N   "      &            apb smi            3           &         clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         J                     A           &   &      larb@1802e000             mediatek,mt8195-smi-larb            J                    d           W           N   '       '            apb smi            3           &         clock-controller@1802f000             mediatek,mt8195-vdecsys         J                    A           &   '      larb@1803e000             mediatek,mt8195-smi-larb            J                    d           W           N   "      (            apb smi            3           &         clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           J                    A           &   (      clock-controller@190f3000             mediatek,mt8195-apusys_pll          J    0                A           &  S      clock-controller@1a000000             mediatek,mt8195-vencsys         J                      A           &   )      larb@1a010000             mediatek,mt8195-smi-larb            J                     d           W           N   )      )           apb smi            3           &         video-codec@1a020000              mediatek,mt8195-vcodec-enc          J                   H  E     `     a     b     c     d     v     w     x     y              U               8           N   )         	  venc_sel            S      @        c                 3                        +           &  T      jpeg-decoder@1a040000             mediatek,mt8195-jpgdec             3         0  E     m     n     r     s     t     u                     +         0                                              jpgdec@0,0            mediatek,mt8195-jpgdec-hw           J                     0  E     m     n     r     s     t     u              W               N   )           jpgdec             3         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw           J                    0  E     m     n     r     s     t     u              X               N   )           jpgdec             3         jpgdec@1,0            mediatek,mt8195-jpgdec-hw           J                    0  E                                            \               N   *           jpgdec             3            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           J                      A           &   *      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            J                                      A                               &   #      jpeg-encoder@1a030000             mediatek,mt8195-jpgenc             3            E                                         +         0                                              jpgenc@0,0            mediatek,mt8195-jpgenc-hw           J                        E     g     h     i     l              V               N   )           jpgenc             3         jpgenc@1,0            mediatek,mt8195-jpgenc-hw           J                       E                                  [               N   *           jpgenc             3            larb@1b010000             mediatek,mt8195-smi-larb            J                     d           W           N   *      *      "            apb smi gals               3           &         ovl@1c000000              mediatek,mt8195-disp-ovl            J                            |                  3           N   #            E                                   &  U   ports                        +       port@0          J       endpoint            &  V         port@1          J      endpoint            	b           &                  rdma@1c002000             mediatek,mt8195-disp-rdma           J                            ~                  3           N   #           E                                    &  W   ports                        +       port@0          J       endpoint            	b           &            port@1          J      endpoint            	b           &                  color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           J     0                                        3           N   #                   0            &  X   ports                        +       port@0          J       endpoint            	b           &            port@1          J      endpoint            	b           &                  ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           J     @                                        3           N   #                   @            &  Y   ports                        +       port@0          J       endpoint            	b           &            port@1          J      endpoint            	b           &                  aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           J     P                                        3           N   #                   P            &  Z   ports                        +       port@0          J       endpoint            	b           &            port@1          J      endpoint            	b           &                  gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           J     `                                        3           N   #                   `            &  [   ports                        +       port@0          J       endpoint            	b           &            port@1          J      endpoint            	b           &                  dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         J     p                                        3           N   #   	                p            &  \   ports                        +       port@0          J       endpoint            	b           &            port@1          J      endpoint            	b           &                  dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         J                                             3           N   #      #   *           engine digital hs           	           
dphy          	  disabled                         +            &  ]   ports                        +       port@0          J       endpoint            	b           &            port@1          J      endpoint            &  ^               dsc@1c009000              mediatek,mt8195-disp-dsc            J                                             3           N   #                               &  _      dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         J                                             3           N   #      #   +           engine digital hs           	           
dphy          	  disabled            &  `      merge@1c014000            mediatek,mt8195-disp-merge          J    @                                        3           N   #                   @            &  a      dp-intf@1c015000              mediatek,mt8195-dp-intf         J    P                                        3           N   #   ,   #                 pixel engine pll          	  disabled            &  b      mutex@1c016000            mediatek,mt8195-disp-mutex          J    `                                        3           N   #                   `            $  U        &  c      larb@1c018000             mediatek,mt8195-smi-larb            J                    d            W           N   #   (   #   (   "           apb smi gals               3           &         larb@1c019000             mediatek,mt8195-smi-larb            J                    d           W           N   #   (   "       "           apb smi gals               3           &         syscon@1c100000           mediatek,mt8195-vdosys1 syscon          J                                                           A                      &   +   port                         +       endpoint@1          J           	b           &               smi@1c01b000              mediatek,mt8195-smi-common-vdo          J                     N   #   %   #   &   #   )   #   $        apb smi gals0 gals1            3           &         iommu@1c01f000            mediatek,mt8195-iommu-vdo           J                  8  u                                                                                  N   #   '        bclk               3           &         mutex@1c101000            mediatek,mt8195-disp-mutex          J                                            3           N   +                               $          &  d      larb@1c102000             mediatek,mt8195-smi-larb            J                     d           W           N   +       +       +           apb smi gals               3           &         larb@1c103000             mediatek,mt8195-smi-larb            J    0                d           W           N   +      +      "            apb smi gals               3           &         dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           J    @                                     N   +              3           E      @                @            L           &  e      dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           J    P                                     N   +              3           E      `                P            L           &  f      dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           J    `                                     N   +              3           E      A                `            L           &  g      dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           J    p                                     N   +              3           E      a                p            L           &  h      dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           J                                         N   +              3           E      B                            L           &  i      dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           J                                         N   +              3           E      b                            L           &  j      dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           J                                         N   +              3           E      C                            L           &  k      dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           J                                         N   +              3           E      c                            L           &  l      vpp-merge@1c10c000            mediatek,mt8195-disp-merge          J                                         N   +   	   +           merge merge_async              3                                           +           &  m      vpp-merge@1c10d000            mediatek,mt8195-disp-merge          J                                         N   +   
   +           merge merge_async              3                                           +           &  n      vpp-merge@1c10e000            mediatek,mt8195-disp-merge          J                                         N   +      +           merge merge_async              3                                           +           &  o      vpp-merge@1c10f000            mediatek,mt8195-disp-merge          J                                         N   +      +           merge merge_async              3                                           +           &  p      vpp-merge@1c110000            mediatek,mt8195-disp-merge          J                                          N   +      +           merge merge_async              3                                            +           &  q   ports                        +       port@0                       +            J       endpoint@1          J           	b           &            port@1                       +            J      endpoint@1          J           	b           &                  dpi@1c112000              mediatek,mt8195-dpi         J                     N   +   -   +      +   2        pixel engine pll                                     3              +           okay            &  r   ports                        +       port@0          J       endpoint            	b           &            port@1          J      endpoint            	b           &                  dp-intf@1c113000              mediatek,mt8195-dp-intf         J    0                                        3           N   +   /   +                 pixel engine pll          	  disabled            &  s      hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  J    @            P            p                                                              4  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p          @            P            p                                                          h  N   +   %   +       +   #   +   !   +   $   +   "   +   1   +   &   +   '   +   (   +   )   +   *              mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top             3           E      d      e                           (     +   3   +   4   +   5   +   6   +   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async            &  t   ports                        +       port@0                       +            J       endpoint@1          J           	b           &            port@1                       +            J      endpoint@1          J           	b           &                  hdmi-tx@1c300000              mediatek,mt8195-hdmi-tx         z           J    0                  N      Q      L      M   $   ,        bus hdcp hdcp24m hdmi-split         S      L        c                                      3           	           
hdmi            okay            default                    &      i2c           mediatek,mt8195-hdmi-ddc            N           &         ports                        +       port@0          J       endpoint            	b           &            port@1          J      endpoint            	b           &                  edp-tx@1c500000           mediatek,mt8195-edp-tx          J    P                            dp_calibration_data            3                                        	  disabled            &  u      dp-tx@1c600000            mediatek,mt8195-dp-tx           J    `                            dp_calibration_data            3                                        	  disabled            &  v         thermal-zones           &  w   cpu0-thermal                                          trips      trip-alert           L                    Epassive         &         trip-crit                             	   Ecritical            &  x         cooling-maps       map0                     0                          cpu1-thermal                                          trips      trip-alert           L                    Epassive         &         trip-crit                             	   Ecritical            &  y         cooling-maps       map0                     0                          cpu2-thermal                                          trips      trip-alert           L                    Epassive         &         trip-crit                             	   Ecritical            &  z         cooling-maps       map0                     0                          cpu3-thermal                                          trips      trip-alert           L                    Epassive         &         trip-crit                             	   Ecritical            &  {         cooling-maps       map0                     0                          cpu4-thermal                                           trips      trip-alert           L                    Epassive         &         trip-crit                             	   Ecritical            &  |         cooling-maps       map0                     0                          cpu5-thermal                                          trips      trip-alert           L                    Epassive         &         trip-crit                             	   Ecritical            &  }         cooling-maps       map0                     0                          cpu6-thermal                                          trips      trip-alert           L                    Epassive         &         trip-crit                             	   Ecritical            &  ~         cooling-maps       map0                     0                          cpu7-thermal                                          trips      trip-alert           L                    Epassive         &         trip-crit                             	   Ecritical            &           cooling-maps       map0                     0                          vpu0-thermal                                          trips      trip-alert           L                    Epassive         &        trip-crit                             	   Ecritical            &              vpu1-thermal                                       	   trips      trip-alert           L                    Epassive         &        trip-crit                             	   Ecritical            &              gpu-thermal                                    
   trips      trip-alert           L                    Epassive         &        trip-crit                             	   Ecritical            &              gpu1-thermal                                          trips      trip-alert           L                    Epassive         &        trip-crit                             	   Ecritical            &              vdec-thermal                                          trips      trip-alert           L                    Epassive         &        trip-crit                             	   Ecritical            &              img-thermal                                       trips      trip-alert           L                    Epassive         &        trip-crit                             	   Ecritical            &              infra-thermal                                         trips      trip-alert           L                    Epassive         &        trip-crit                             	   Ecritical            &              cam0-thermal                                          trips      trip-alert           L                    Epassive         &        trip-crit                             	   Ecritical            &              cam1-thermal                                          trips      trip-alert           L                    Epassive         &        trip-crit                             	   Ecritical            &                 chosen          serial0:921600n8          connector             hdmi-connector          Ghdmi             Ea           +           7      port       endpoint            	b           &               firmware       optee             linaro,optee-tz         Usmc          memory@40000000         >memory          J    @                backlight             pwm-backlight           G              Y  @        r      k                      default                                   	  disabled            &        gpio-keys         
    gpio-keys           &     button-volume-up                        d        
#      j         
  Gvolume_up              s         regulator-wifi-3v3-en             regulator-fixed         wifi_3v3_en                   2Z         2Z                 +      C            default                       X        &        regulator-vsys            regulator-fixed         vsys                               LK@         LK@                   &   X      regulator-vsys-buck           regulator-fixed       
  vsys_buck                              LK@         LK@                   &   f      regulator-vcc5v0-sys              regulator-fixed         vcc5v0_sys                            &         reserved-memory                      +               optee@43200000          J    C                           &        memory@50000000           shared-dma-pool         J    P                          &   1      memory@53000000           shared-dma-pool         J    S       @          &        memory@54600000         J    T`                           &        memory@60000000           shared-dma-pool         J    `                           &   7      memory@60f00000           shared-dma-pool         J    `                          &   9      memory@61000000           shared-dma-pool         J    a                           &   6      memory@62000000           shared-dma-pool         J    b       @          &           __symbols__         /cpus/cpu@0         /cpus/cpu@100           /cpus/cpu@200           /cpus/cpu@300           /cpus/cpu@400           /cpus/cpu@500           /cpus/cpu@600           /cpus/cpu@700         "  /cpus/idle-states/cpu-retention-l         "  !/cpus/idle-states/cpu-retention-b           +/cpus/idle-states/cpu-off-l         5/cpus/idle-states/cpu-off-b         ?/cpus/l2-cache0         D/cpus/l2-cache1         I/cpus/l3-cache          N/dmic-codec         Y/mt8195-sound           _/fixed-factor-clock-13m         f/oscillator-26m         m/oscillator-32k         t/performance-controller@11bc10          /opp-table-gpu          /timer        "  /soc/interrupt-controller@c000000         G  /soc/interrupt-controller@c000000/ppi-partitions/interrupt-partition-0        G  /soc/interrupt-controller@c000000/ppi-partitions/interrupt-partition-1          /soc/syscon@10000000            /soc/syscon@10001000            {/soc/syscon@10003000            ,/soc/pinctrl@10005000         )  /soc/pinctrl@10005000/audio-default-pins          *  /soc/pinctrl@10005000/dsi0-backlight-pins         '  /soc/pinctrl@10005000/eth-default-pins        %  /soc/pinctrl@10005000/eth-sleep-pins          %  /soc/pinctrl@10005000/gpio-keys-pins          %  /soc/pinctrl@10005000/hdmi-vreg-pins             "/soc/pinctrl@10005000/hdmi-pins          ,/soc/pinctrl@10005000/i2c2-pins          6/soc/pinctrl@10005000/i2c4-pins          @/soc/pinctrl@10005000/i2c6-pins       (  J/soc/pinctrl@10005000/mmc0-default-pins       $  \/soc/pinctrl@10005000/mmc0-uhs-pins       (  j/soc/pinctrl@10005000/mmc1-default-pins       '  |/soc/pinctrl@10005000/mmc1-detect-pins        "  /soc/pinctrl@10005000/mt6360-pins         !  /soc/pinctrl@10005000/panel-pins          )  /soc/pinctrl@10005000/pcie0-default-pins          )  /soc/pinctrl@10005000/pcie1-default-pins             /soc/pinctrl@10005000/pwm0-pins       (  /soc/pinctrl@10005000/spi1-default-pins       (  /soc/pinctrl@10005000/spi2-default-pins       !  /soc/pinctrl@10005000/touch-pins          !  /soc/pinctrl@10005000/uart0-pins          !  /soc/pinctrl@10005000/uart1-pins          *  /soc/pinctrl@10005000/usb3p0-default-pins         *  )/soc/pinctrl@10005000/usb2p0-default-pins         %  9/soc/pinctrl@10005000/wifi-vreg-pins            H/soc/syscon@10006000          &  O/soc/syscon@10006000/power-controller         5  S/soc/syscon@10006000/power-controller/power-domain@8          D  X/soc/syscon@10006000/power-controller/power-domain@8/power-domain@9         ]/soc/watchdog@10007000          f/soc/syscon@1000c000            q/soc/timer@10017000         z/soc/pwrap@10024000         /soc/pwrap@10024000/pmic            /soc/pwrap@10024000/pmic/adc          %  /soc/pwrap@10024000/pmic/audio-codec          -  /soc/pwrap@10024000/pmic/regulators/buck_vs1          0  /soc/pwrap@10024000/pmic/regulators/buck_vgpu11       0  /soc/pwrap@10024000/pmic/regulators/buck_vmodem       -  /soc/pwrap@10024000/pmic/regulators/buck_vpu          /  /soc/pwrap@10024000/pmic/regulators/buck_vcore        -  /soc/pwrap@10024000/pmic/regulators/buck_vs2          -  /soc/pwrap@10024000/pmic/regulators/buck_vpa          0  ./soc/pwrap@10024000/pmic/regulators/buck_vproc2       0  E/soc/pwrap@10024000/pmic/regulators/buck_vproc1       5  \/soc/pwrap@10024000/pmic/regulators/buck_vcore_sshub          6  x/soc/pwrap@10024000/pmic/regulators/buck_vgpu11_sshub         /  /soc/pwrap@10024000/pmic/regulators/ldo_vaud18        .  /soc/pwrap@10024000/pmic/regulators/ldo_vsim1         -  /soc/pwrap@10024000/pmic/regulators/ldo_vibr          .  /soc/pwrap@10024000/pmic/regulators/ldo_vrf12         -  /soc/pwrap@10024000/pmic/regulators/ldo_vusb          4  /soc/pwrap@10024000/pmic/regulators/ldo_vsram_proc2       .  /soc/pwrap@10024000/pmic/regulators/ldo_vio18         /  -/soc/pwrap@10024000/pmic/regulators/ldo_vcamio        .  C/soc/pwrap@10024000/pmic/regulators/ldo_vcn18         .  X/soc/pwrap@10024000/pmic/regulators/ldo_vfe28         .  m/soc/pwrap@10024000/pmic/regulators/ldo_vcn13         3  /soc/pwrap@10024000/pmic/regulators/ldo_vcn33_1_bt        5  /soc/pwrap@10024000/pmic/regulators/ldo_vcn33_1_wifi          /  /soc/pwrap@10024000/pmic/regulators/ldo_vaux18        5  /soc/pwrap@10024000/pmic/regulators/ldo_vsram_others          /  /soc/pwrap@10024000/pmic/regulators/ldo_vefuse        .   /soc/pwrap@10024000/pmic/regulators/ldo_vxo22         .  /soc/pwrap@10024000/pmic/regulators/ldo_vrfck         0  */soc/pwrap@10024000/pmic/regulators/ldo_vrfck_1       /  A/soc/pwrap@10024000/pmic/regulators/ldo_vbif28        .  W/soc/pwrap@10024000/pmic/regulators/ldo_vio28         -  l/soc/pwrap@10024000/pmic/regulators/ldo_vemc          /  /soc/pwrap@10024000/pmic/regulators/ldo_vemc_1        3  /soc/pwrap@10024000/pmic/regulators/ldo_vcn33_2_bt        5  /soc/pwrap@10024000/pmic/regulators/ldo_vcn33_2_wifi          -  /soc/pwrap@10024000/pmic/regulators/ldo_va12          -  /soc/pwrap@10024000/pmic/regulators/ldo_va09          .  /soc/pwrap@10024000/pmic/regulators/ldo_vrf18         1  	/soc/pwrap@10024000/pmic/regulators/ldo_vsram_md          -  !/soc/pwrap@10024000/pmic/regulators/ldo_vufs          -  5/soc/pwrap@10024000/pmic/regulators/ldo_vm18          .  I/soc/pwrap@10024000/pmic/regulators/ldo_vbbck         4  ^/soc/pwrap@10024000/pmic/regulators/ldo_vsram_proc1       .  y/soc/pwrap@10024000/pmic/regulators/ldo_vsim2         ;  /soc/pwrap@10024000/pmic/regulators/ldo_vsram_others_sshub          /soc/pwrap@10024000/pmic/rtc            /soc/pwrap@10024000/pmic/keys           /soc/spmi@10027000          /soc/spmi@10027000/pmic@6         ,  /soc/spmi@10027000/pmic@6/regulators/vbuck1         /soc/spmi@10027000/pmic@7         ,  /soc/spmi@10027000/pmic@7/regulators/vbuck1         /soc/infra-iommu@10315000            a/soc/mailbox@10320000            f/soc/mailbox@10330000           A/soc/scp@10500000           /soc/clock-controller@10720000          (/soc/dsp@10803000           /soc/mailbox@10816000           /soc/mailbox@10817000           )/soc/mt8195-afe-pcm@10890000            -/soc/serial@11001100            3/soc/serial@11001200            9/soc/serial@11001300            ?/soc/serial@11001400            E/soc/serial@11001500            K/soc/serial@11001600            Q/soc/auxadc@11002000            X/soc/syscon@11003000            4/soc/spi@1100a000           c/soc/thermal-sensor@1100b000            k/soc/svs@1100bc00           o/soc/pwm@1100e000           y/soc/pwm@1100f000           9/soc/spi@11010000           /soc/spi@11012000           /soc/spi@11013000           /soc/spi@11018000           /soc/spi@11019000           /soc/spi@1101d000           /soc/spi@1101e000           /soc/ethernet@11021000        +  /soc/ethernet@11021000/mdio/ethernet-phy@1        )  /soc/ethernet@11021000/stmmac-axi-config          (  /soc/ethernet@11021000/rx-queues-config       (  /soc/ethernet@11021000/tx-queues-config         /soc/usb@11201000           /soc/usb@11201000/usb@0          /soc/usb@11201000/port/endpoint         /soc/mmc@11230000           /soc/mmc@11240000           /soc/mmc@11250000           	/soc/ufshci@11270000            /soc/thermal-sensor@11278000            /soc/usb@11290000           /soc/usb@112a1000           &/soc/usb@112a1000/usb@0         ,/soc/usb@112b1000           3/soc/usb@112b1000/usb@0         9/soc/pcie@112f0000        (  ?/soc/pcie@112f0000/interrupt-controller         J/soc/pcie@112f8000        (  P/soc/pcie@112f8000/interrupt-controller         [/soc/spi@1132c000           e/soc/efuse@11c10000       &  k/soc/efuse@11c10000/usb3-tx-imp@184,1         &  x/soc/efuse@11c10000/usb3-rx-imp@184,2         "  /soc/efuse@11c10000/usb3-intr@185         &  /soc/efuse@11c10000/usb3-tx-imp@186,1         &  /soc/efuse@11c10000/usb3-rx-imp@186,2         "  /soc/efuse@11c10000/usb3-intr@187         '  /soc/efuse@11c10000/usb2-intr-p0@188,1        '  /soc/efuse@11c10000/usb2-intr-p1@188,2        '  /soc/efuse@11c10000/usb2-intr-p2@189,1        '  /soc/efuse@11c10000/usb2-intr-p3@189,2        )  /soc/efuse@11c10000/pciephy-rx-ln1@190,1          .  /soc/efuse@11c10000/pciephy-tx-ln1-nmos@190,2         .  
/soc/efuse@11c10000/pciephy-tx-ln1-pmos@191,1         )  /soc/efuse@11c10000/pciephy-rx-ln0@191,2          .  -/soc/efuse@11c10000/pciephy-tx-ln0-nmos@192,1         .  A/soc/efuse@11c10000/pciephy-tx-ln0-pmos@192,2         )  U/soc/efuse@11c10000/pciephy-glb-intr@193             f/soc/efuse@11c10000/dp-data@1ac       $  u/soc/efuse@11c10000/lvts1-calib@1bc       $  /soc/efuse@11c10000/lvts2-calib@1d0       "  /soc/efuse@11c10000/svs-calib@580           /soc/t-phy@11c40000         /soc/t-phy@11c40000/usb-phy@0           /soc/t-phy@11c50000         /soc/t-phy@11c50000/usb-phy@0           /soc/dsi-phy@11c80000           /soc/dsi-phy@11c90000           /soc/i2c@11d00000           /soc/i2c@11d01000           /soc/i2c@11d01000/pmic@34         9  /soc/i2c@11d01000/pmic@34/charger/usb-otg-vbus-regulator          *  /soc/i2c@11d01000/pmic@34/regulator/buck1         *  /soc/i2c@11d01000/pmic@34/regulator/buck2         )  /soc/i2c@11d01000/pmic@34/regulator/ldo1          )   /soc/i2c@11d01000/pmic@34/regulator/ldo2          )  ,/soc/i2c@11d01000/pmic@34/regulator/ldo3          )  8/soc/i2c@11d01000/pmic@34/regulator/ldo5          )  D/soc/i2c@11d01000/pmic@34/regulator/ldo6          )  P/soc/i2c@11d01000/pmic@34/regulator/ldo7          @  \/soc/i2c@11d01000/pmic@34/typec/connector/ports/port@0/endpoint       @  i/soc/i2c@11d01000/pmic@34/typec/connector/ports/port@2/endpoint         w/soc/i2c@11d02000           |/soc/clock-controller@11d03000          /soc/hdmi-phy@11d5f000          /soc/i2c@11e00000           /soc/i2c@11e01000           /soc/i2c@11e02000         -  /soc/i2c@11e02000/typec-mux@48/port/endpoint            /soc/i2c@11e03000           /soc/i2c@11e04000           /soc/clock-controller@11e05000          /soc/t-phy@11e30000         /soc/t-phy@11e30000/usb-phy@0            /soc/t-phy@11e30000/usb-phy@700         /soc/t-phy@11e40000         /soc/t-phy@11e40000/usb-phy@0            /soc/t-phy@11e40000/usb-phy@700         /soc/phy@11e80000           /soc/ufs-phy@11fa0000           /soc/gpu@13000000           /soc/clock-controller@13fbf000          /soc/syscon@14000000            /soc/smi@14010000           /soc/smi@14011000           </soc/smi@14012000           K/soc/larb@14013000          Q/soc/iommu@14018000         [/soc/clock-controller@14e00000          b/soc/clock-controller@14e02000          n/soc/clock-controller@14e03000          z/soc/larb@14e04000          /soc/larb@14e05000          /soc/syscon@14f00000            /soc/larb@14f02000          /soc/larb@14f03000          /soc/clock-controller@15000000          /soc/larb@15001000          /soc/smi@15002000           /soc/smi@15003000           /soc/clock-controller@15110000          /soc/larb@15120000          /soc/clock-controller@15130000          /soc/clock-controller@15220000          	/soc/larb@15230000          /soc/clock-controller@15330000          /soc/larb@15340000          /soc/clock-controller@16000000          %/soc/larb@16001000          ,/soc/larb@16002000          3/soc/smi@16004000           J/soc/smi@16005000           a/soc/larb@16012000          h/soc/larb@16013000          o/soc/larb@16014000          v/soc/larb@16015000          }/soc/clock-controller@1604f000          /soc/clock-controller@1606f000          /soc/clock-controller@1608f000          /soc/clock-controller@160af000          /soc/clock-controller@16140000          /soc/larb@16141000          /soc/larb@16142000          /soc/clock-controller@17200000          /soc/larb@17201000          /soc/larb@1800d000          /soc/larb@1800e000          /soc/clock-controller@1800f000          /soc/larb@1802e000          /soc/clock-controller@1802f000          /soc/larb@1803e000          /soc/clock-controller@1803f000          /soc/clock-controller@190f3000          /soc/clock-controller@1a000000          &/soc/larb@1a010000          -/soc/video-codec@1a020000           2/soc/clock-controller@1b000000          @/soc/syscon@1c01a000            H/soc/larb@1b010000          O/soc/ovl@1c000000         (  T/soc/ovl@1c000000/ports/port@0/endpoint       (  \/soc/ovl@1c000000/ports/port@1/endpoint          /soc/rdma@1c002000        )  e/soc/rdma@1c002000/ports/port@0/endpoint          )  n/soc/rdma@1c002000/ports/port@1/endpoint            x/soc/color@1c003000       *  /soc/color@1c003000/ports/port@0/endpoint         *  /soc/color@1c003000/ports/port@1/endpoint           /soc/ccorr@1c004000       *  /soc/ccorr@1c004000/ports/port@0/endpoint         *  /soc/ccorr@1c004000/ports/port@1/endpoint           /soc/aal@1c005000         (  /soc/aal@1c005000/ports/port@0/endpoint       (  /soc/aal@1c005000/ports/port@1/endpoint         /soc/gamma@1c006000       *  /soc/gamma@1c006000/ports/port@0/endpoint         *  /soc/gamma@1c006000/ports/port@1/endpoint           /soc/dither@1c007000          +  /soc/dither@1c007000/ports/port@0/endpoint        +  /soc/dither@1c007000/ports/port@1/endpoint          /soc/dsi@1c008000         (  /soc/dsi@1c008000/ports/port@0/endpoint       (  /soc/dsi@1c008000/ports/port@1/endpoint         /soc/dsc@1c009000           /soc/dsi@1c012000           !/soc/merge@1c014000         (/soc/dp-intf@1c015000           1/soc/mutex@1c016000         7/soc/larb@1c018000          =/soc/larb@1c019000          C/soc/syscon@1c100000          %  K/soc/syscon@1c100000/port/endpoint@1            Z/soc/smi@1c01b000           i/soc/iommu@1c01f000          /soc/mutex@1c101000         s/soc/larb@1c102000          y/soc/larb@1c103000          /soc/dma-controller@1c104000            /soc/dma-controller@1c105000            /soc/dma-controller@1c106000            /soc/dma-controller@1c107000            /soc/dma-controller@1c108000            /soc/dma-controller@1c109000            /soc/dma-controller@1c10a000            /soc/dma-controller@1c10b000             /soc/vpp-merge@1c10c000          /soc/vpp-merge@1c10d000          /soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000       0  /soc/vpp-merge@1c110000/ports/port@0/endpoint@1       0  /soc/vpp-merge@1c110000/ports/port@1/endpoint@1          \/soc/dpi@1c112000         (  /soc/dpi@1c112000/ports/port@0/endpoint       (  /soc/dpi@1c112000/ports/port@1/endpoint         /soc/dp-intf@1c113000            q/soc/hdr-engine@1c114000          1  /soc/hdr-engine@1c114000/ports/port@0/endpoint@1          1  /soc/hdr-engine@1c114000/ports/port@1/endpoint@1            /soc/hdmi-tx@1c300000            /soc/hdmi-tx@1c300000/i2c         ,  +/soc/hdmi-tx@1c300000/ports/port@0/endpoint       ,  4/soc/hdmi-tx@1c300000/ports/port@1/endpoint         >/soc/edp-tx@1c500000            ?/soc/dp-tx@1c600000         E/thermal-zones        -  S/thermal-zones/cpu0-thermal/trips/trip-alert          ,  ^/thermal-zones/cpu0-thermal/trips/trip-crit       -  h/thermal-zones/cpu1-thermal/trips/trip-alert          ,  s/thermal-zones/cpu1-thermal/trips/trip-crit       -  }/thermal-zones/cpu2-thermal/trips/trip-alert          ,  /thermal-zones/cpu2-thermal/trips/trip-crit       -  /thermal-zones/cpu3-thermal/trips/trip-alert          ,  /thermal-zones/cpu3-thermal/trips/trip-crit       -  /thermal-zones/cpu4-thermal/trips/trip-alert          ,  /thermal-zones/cpu4-thermal/trips/trip-crit       -  /thermal-zones/cpu5-thermal/trips/trip-alert          ,  /thermal-zones/cpu5-thermal/trips/trip-crit       -  /thermal-zones/cpu6-thermal/trips/trip-alert          ,  /thermal-zones/cpu6-thermal/trips/trip-crit       -  /thermal-zones/cpu7-thermal/trips/trip-alert          ,  /thermal-zones/cpu7-thermal/trips/trip-crit       -  /thermal-zones/vpu0-thermal/trips/trip-alert          ,  /thermal-zones/vpu0-thermal/trips/trip-crit       -  /thermal-zones/vpu1-thermal/trips/trip-alert          ,  /thermal-zones/vpu1-thermal/trips/trip-crit       ,  %/thermal-zones/gpu-thermal/trips/trip-alert       +  0/thermal-zones/gpu-thermal/trips/trip-crit        -  :/thermal-zones/gpu1-thermal/trips/trip-alert          ,  E/thermal-zones/gpu1-thermal/trips/trip-crit       -  O/thermal-zones/vdec-thermal/trips/trip-alert          ,  Z/thermal-zones/vdec-thermal/trips/trip-crit       ,  d/thermal-zones/img-thermal/trips/trip-alert       +  n/thermal-zones/img-thermal/trips/trip-crit        .  w/thermal-zones/infra-thermal/trips/trip-alert         -  /thermal-zones/infra-thermal/trips/trip-crit          -  /thermal-zones/cam0-thermal/trips/trip-alert          ,  /thermal-zones/cam0-thermal/trips/trip-crit       -  /thermal-zones/cam1-thermal/trips/trip-alert          ,  /thermal-zones/cam1-thermal/trips/trip-crit         /connector/port/endpoint            /backlight          /gpio-keys          /regulator-wifi-3v3-en          /regulator-vsys         /regulator-vsys-buck            /regulator-vcc5v0-sys            /reserved-memory/optee@43200000       !  /reserved-memory/memory@50000000          !  /reserved-memory/memory@53000000          !  /reserved-memory/memory@54600000          !  (/reserved-memory/memory@60000000          !  1/reserved-memory/memory@60f00000          !  =/reserved-memory/memory@61000000          !  J/reserved-memory/memory@62000000             	compatible interrupt-parent #address-cells #size-cells model chassis-type dp-intf0 dp-intf1 dpi1 gce0 gce1 hdmi0 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 i2c0 i2c1 i2c2 i2c3 i2c4 ethernet0 serial0 serial1 spi0 spi1 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform pinctrl-names pinctrl-0 audio-routing mediatek,adsp link-name sound-dai #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges mediatek,rsel-resistance-in-si-unit pinmux output-high drive-strength input-enable bias-disable input-disable bias-pull-up bias-pull-down drive-strength-microamp output-low #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes mediatek,long-press-mode power-off-time-sec linux,keycodes wakeup-source #iommu-cells #mbox-cells memory-region firmware-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,tx-delay-ps mediatek,mac-wol snps,reset-gpio snps,reset-delays-us snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys mediatek,syscon-wakeup role-switch-default-mode usb-role-switch vusb33-supply vbus-supply remote-endpoint bus-width max-frequency hs400-ds-delay cap-mmc-highspeed cap-mmc-hw-reset mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable vmmc-supply vqmmc-supply cap-sd-highspeed cd-gpios no-mmc sd-uhs-sdr50 sd-uhs-sdr104 freq-table-hz mediatek,ufs-disable-mcq vcc-supply vccq2-supply usb2-lpm-disable mediatek,u3p-dis-msk bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN1-supply LDO_VIN3-supply label data-role op-sink-microwatt power-role try-power-role source-pdos sink-pdos mediatek,ibias mediatek,ibias_up mode-switch orientation-switch operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path ddc-i2c-bus hdmi-pwr-supply brightness-levels default-brightness-level enable-gpios num-interpolated-steps pwms debounce-interval linux,code enable-active-high vin-supply regulator-boot-on no-map cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_ret_l cpu_ret_b cpu_off_l cpu_off_b l2_0 l2_1 l3_0 dmic_codec sound clk13m clk26m clk32k performance gpu_opp_table timer gic ppi_cluster0 ppi_cluster1 infracfg_ao audio_default_pins dsi0_backlight_pins eth_default_pins eth_sleep_pins gpio_key_pins hdmi_vreg_pins hdmi_pins i2c2_pins i2c4_pins i2c6_pins mmc0_default_pins mmc0_uhs_pins mmc1_default_pins mmc1_pins_detect mt6360_pins panel_default_pins pcie0_default_pins pcie1_default_pins pwm0_default_pins spi1_pins spi2_pins touch_pins uart0_pins uart1_pins usb3_port0_pins usb2_port0_pins wifi_vreg_pins scpsys spm mfg0 mfg1 watchdog apmixedsys systimer pwrap pmic pmic_adc mt6359codec mt6359_vs1_buck_reg mt6359_vgpu11_buck_reg mt6359_vmodem_buck_reg mt6359_vpu_buck_reg mt6359_vcore_buck_reg mt6359_vs2_buck_reg mt6359_vpa_buck_reg mt6359_vproc2_buck_reg mt6359_vproc1_buck_reg mt6359_vcore_sshub_buck_reg mt6359_vgpu11_sshub_buck_reg mt6359_vaud18_ldo_reg mt6359_vsim1_ldo_reg mt6359_vibr_ldo_reg mt6359_vrf12_ldo_reg mt6359_vusb_ldo_reg mt6359_vsram_proc2_ldo_reg mt6359_vio18_ldo_reg mt6359_vcamio_ldo_reg mt6359_vcn18_ldo_reg mt6359_vfe28_ldo_reg mt6359_vcn13_ldo_reg mt6359_vcn33_1_bt_ldo_reg mt6359_vcn33_1_wifi_ldo_reg mt6359_vaux18_ldo_reg mt6359_vsram_others_ldo_reg mt6359_vefuse_ldo_reg mt6359_vxo22_ldo_reg mt6359_vrfck_ldo_reg mt6359_vrfck_1_ldo_reg mt6359_vbif28_ldo_reg mt6359_vio28_ldo_reg mt6359_vemc_ldo_reg mt6359_vemc_1_ldo_reg mt6359_vcn33_2_bt_ldo_reg mt6359_vcn33_2_wifi_ldo_reg mt6359_va12_ldo_reg mt6359_va09_ldo_reg mt6359_vrf18_ldo_reg mt6359_vsram_md_ldo_reg mt6359_vufs_ldo_reg mt6359_vm18_ldo_reg mt6359_vbbck_ldo_reg mt6359_vsram_proc1_ldo_reg mt6359_vsim2_ldo_reg mt6359_vsram_others_sshub_ldo mt6359rtc mt6359keys spmi mt6315_6 mt6315_6_vbuck1 mt6315_7 mt6315_7_vbuck1 iommu_infra scp_adsp adsp_mailbox0 adsp_mailbox1 afe uart0 uart1 uart2 uart3 uart4 uart5 auxadc pericfg_ao lvts_ap svs disp_pwm0 disp_pwm1 spi2 spi3 spi4 spi5 spis0 spis1 eth rgmii_phy stmmac_axi_setup mtl_rx_setup mtl_tx_setup ssusb0 xhci0 mtu3_hs0_role_sw mmc0 mmc1 mmc2 ufshci lvts_mcu xhci1 ssusb2 xhci2 ssusb3 xhci3 pcie0 pcie_intc0 pcie1 pcie_intc1 nor_flash efuse u3_tx_imp_p0 u3_rx_imp_p0 u3_intr_p0 comb_tx_imp_p1 comb_rx_imp_p1 comb_intr_p1 u2_intr_p0 u2_intr_p1 u2_intr_p2 u2_intr_p3 pciephy_rx_ln1 pciephy_tx_ln1_nmos pciephy_tx_ln1_pmos pciephy_rx_ln0 pciephy_tx_ln0_nmos pciephy_tx_ln0_pmos pciephy_glb_intr dp_calibration lvts_efuse_data1 lvts_efuse_data2 svs_calib_data u3phy2 u2port2 u3phy3 u2port3 mipi_tx0 mipi_tx1 i2c5 i2c6 mt6360 otg_vbus_regulator mt6360_buck1 mt6360_buck2 mt6360_ldo1 mt6360_ldo2 mt6360_ldo3 mt6360_ldo5 mt6360_ldo6 mt6360_ldo7 typec_con_hs typec_con_mux i2c7 imp_iic_wrap_s hdmi_phy it5205_sbu_mux imp_iic_wrap_w u3phy1 u2port1 u3port1 u3phy0 u2port0 u3port0 pciephy ufsphy gpu mfgcfg vppsys0 smi_sub_common_vpp0_vpp1_2x1 smi_sub_common_vdec_vpp0_2x1 smi_common_vpp larb4 iommu_vpp wpesys wpesys_vpp0 wpesys_vpp1 larb7 larb8 vppsys1 larb5 larb6 imgsys larb9 smi_sub_common_img0_3x1 smi_sub_common_img1_3x1 imgsys1_dip_top larb10 imgsys1_dip_nr imgsys1_wpe larb11 ipesys larb12 camsys larb13 larb14 smi_sub_common_cam_4x1 smi_sub_common_cam_7x1 larb16 larb17 larb27 larb28 camsys_rawa camsys_yuva camsys_rawb camsys_yuvb camsys_mraw larb25 larb26 ccusys larb18 larb24 larb23 vdecsys_soc larb21 vdecsys larb22 vdecsys_core1 apusys_pll vencsys larb19 venc vencsys_core1 vdosys0 larb20 ovl0 ovl0_in ovl0_out rdma0_in rdma0_out color0 color0_in color0_out ccorr0 ccorr0_in ccorr0_out aal0 aal0_in aal0_out gamma0 gamma0_in gamma0_out dither0 dither0_in dither0_out dsi0 dsi0_in dsi0_out dsc0 dsi1 merge0 dp_intf0 mutex larb0 larb1 vdosys1 vdosys1_ep_ext smi_common_vdo iommu_vdo larb2 larb3 vdo1_rdma0 vdo1_rdma1 vdo1_rdma2 vdo1_rdma3 vdo1_rdma4 vdo1_rdma5 vdo1_rdma6 vdo1_rdma7 merge5_in merge5_out dpi1_in dpi1_out dp_intf1 ethdr0_in ethdr0_out hdmi hdmitx_ddc hdmi0_in hdmi0_out edp_tx thermal_zones cpu0_alert cpu0_crit cpu1_alert cpu1_crit cpu2_alert cpu2_crit cpu3_alert cpu3_crit cpu4_alert cpu4_crit cpu5_alert cpu5_crit cpu6_alert cpu6_crit cpu7_alert cpu7_crit vpu0_alert vpu0_crit vpu1_alert vpu1_crit gpu0_alert gpu0_crit gpu1_alert gpu1_crit vdec_alert vdec_crit img_alert img_crit infra_alert infra_crit cam0_alert cam0_crit cam1_alert cam1_crit hdmi_connector_in backlight wifi_vreg vsys vsys_buck vcc5v0_vsys optee_reserved scp_mem vpu_mem bl31_secmon_mem adsp_mem afe_dma_mem adsp_dma_mem apu_mem 