 i   8 ]D   (            I ]                             6    kontron,3-5-sbc-i1200 mediatek,mt8395 mediatek,mt8195                                    +            7Kontron 3.5"-SBC-i1200     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dpi@1c112000            T/soc/mailbox@10320000            Y/soc/mailbox@10330000            ^/soc/hdmi-tx@1c300000            d/soc/hdr-engine@1c114000             k/soc/mutex@1c016000          r/soc/mutex@1c101000          y/soc/vpp-merge@1c10c000          /soc/vpp-merge@1c10d000          /soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000             /soc/mmc@11230000            /soc/mmc@11240000            /soc/serial@11001200            /soc/serial@11001300            /soc/serial@11001400            /soc/serial@11001500            /soc/serial@11001100          cpus                         +       cpu@0           &cpu           arm,cortex-a55          2            6psci            D               Xec3@        h  4        {                            @                                 @                                            	      cpu@100         &cpu           arm,cortex-a55          2           6psci            D               Xec3@        h  4        {                            @                                 @                                            
      cpu@200         &cpu           arm,cortex-a55          2           6psci            D               Xec3@        h  4        {                            @                                 @                                                  cpu@300         &cpu           arm,cortex-a55          2           6psci            D               Xec3@        h  4        {                            @                                 @                                                  cpu@400         &cpu           arm,cortex-a78          2           6psci            D              Xf        h           {                            @                                 @                                                  cpu@500         &cpu           arm,cortex-a78          2           6psci            D              Xf        h           {                            @                                 @                                                  cpu@600         &cpu           arm,cortex-a78          2           6psci            D              Xf        h           {                            @                                 @                                                  cpu@700         &cpu           arm,cortex-a78          2           6psci            D              Xf        h           {                            @                                 @                                                  cpu-map    cluster0       core0              	      core1              
      core2                    core3                    core4                    core5                    core6                    core7                          idle-states         psci       cpu-retention-l           arm,idle-state                     3        D   2        U   _        e  D                 cpu-retention-b           arm,idle-state                     3        D   -        U           e                   cpu-off-l             arm,idle-state                    3        D   7        U           e  H                 cpu-off-b             arm,idle-state                    3        D   2        U           e                      l2-cache0             cache           v                         @                                                l2-cache1             cache           v                         @                                                l3-cache              cache           v                          @                                        dsu-pmu           arm,dsu-pmu                                   	   
                          fail          dmic-codec            dmic-codec                        2      mt8195-sound                     	  disabled          fixed-factor-clock-13m            fixed-factor-clock                                                       clk13m             (      oscillator-26m            fixed-clock                     X        clk26m                   oscillator-32k            fixed-clock                     X           clk32k        performance-controller@11bc10             mediatek,cpufreq-hw          2                 0                                   opp-table-gpu             operating-points-v2          ,           n   opp-390000000           7    >        > 	h      opp-410000000           7    p        > 	      opp-431000000           7            > 	      opp-473000000           7    1h@        > 	<      opp-515000000           7    F        > 	<      opp-556000000           7    !#         > 	Ҧ      opp-598000000           7    #        > 	      opp-640000000           7    &%         > 	      opp-670000000           7    'c        > 
      opp-700000000           7    )'         > 
L      opp-730000000           7    +        > 
}      opp-760000000           7    -L         > 
`      opp-790000000           7    /q        > 
4      opp-820000000           7    05         >       opp-850000000           7    2        > @      opp-880000000           7    4s         > q         pmu-a55           arm,cortex-a55-pmu                                        pmu-a78           arm,cortex-a78-pmu                                        psci              arm,psci-1.0            =smc       timer             arm,armv8-timer                   @                                               
             soc                      +             simple-bus           L        S                          interrupt-controller@c000000              arm,gic-v3          ^           o                                 2                                          	                     ppi-partitions     interrupt-partition-0              	   
                       interrupt-partition-1                                              syscon@10000000            mediatek,mt8195-topckgen syscon         2                                          syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          2                                                    syscon@10003000           mediatek,mt8195-pericfg syscon          2     0                              A      pinctrl@10005000              mediatek,mt8195-pinctrl         2     P                                                                                                         B  iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint                                                                                    ^                 eth-default-pins               =   pins-txd              M  N  O  P                 pins-rxd              Q  R  S  T      pins-cc           U  V  W  X                 pins-mdio             Y  Z               pins-power            [   \                pins-reset            ]                pins-interrupt            ^                   eth-sleep-pins             >   pins-txd              M   N   O   P       pins-cc           U   X   W   V       pins-rxd              Q   R   S   T       pins-mdio             Y   Z                             gpio-keys-pins                pins              j                   i2c0-pins              [   pins                	        -           :           i2c1-pins              \   pins              
          -           :           i2c2-default-pins              ]   pins-bus                        -           :           i2c3-pins              ^   pins                        -           :           i2c4-pins              _   pins                        -           :           i2c6-pins              X   pins                         -        :           mmc0-default-pins              C   pins-clk              z                   R   f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                            -   e      pins-rst              x                   -   e         mmc0-uhs-pins              D   pins-clk              z                   R   f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                            -   e      pins-ds                              R   f      pins-rst              x                   -   e         mmc1-default-pins              G   pins-clk              o                   R   f      pins-cmd-dat              n  p  q  r  s                            -   e         mmc1-detect-pins               H   pins-insert                     -         nor-default-pins               V   pins-ck-io                                    R      pins-cs                               -         pcie0-default-pins             R   pins-bus                           -         pcie1-default-pins             U   pins-bus                           -   e         led-pins                  pins-power-en             k                   spi0-default-pins              4   pins-cs-mosi-clk                                  pins-miso                      R         spi1-default-pins              8   pins-cs-mosi-clk                                  pins-miso                      R         uart0-pins             /   pins-rx           c                  -      pins-tx           b         uart1-pins             0   pins-rx           g                  -      pins-tx           f      pins-rts              d      pins-cts              e                  uart2-pins             1   pins-rx           D                  -      pins-tx           C      pins-rts              B      pins-cts              A                  uart3-pins             2   pins-rx                            -   e      pins-tx                    uart4-pins             3   pins-rx                             -      pins-tx                       syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            2     `           power-controller          !    mediatek,mt8195-power-controller                         +            a              +   power-domain@8          2                        +            a      power-domain@9          2   	                            umfg alt                                 +            a      power-domain@10         2   
        a          power-domain@11         2           a          power-domain@12         2           a          power-domain@13         2           a          power-domain@14         2           a                power-domain@15         2                                   	      @      A      K                                                                                                                                uvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18                                   +            a      power-domain@16         2         8              $      %      &      '      (      )      D  uvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5                                 +            a      power-domain@17         2                                     uvppsys1 vppsys1-0 vppsys1-1                    a          power-domain@22         2                                          $  uwepsys-0 wepsys-1 wepsys-2 wepsys-3                    a          power-domain@23         2                          uvdec0-0                                 +            a       power-domain@24         2                          uvdec1-0                    a          power-domain@25         2                           uvdec2-0                    a             power-domain@26         2              !            uvenc0-larb                                  +            a       power-domain@27         2              "            uvenc1-larb                     a             power-domain@18         2                     #       #      #         &  uvdosys1 vdosys1-0 vdosys1-1 vdosys1-2                                   +            a      power-domain@19         2                      a          power-domain@20         2                      a          power-domain@21         2                 Q        uhdmi_tx         a             power-domain@28         2              $       $   
        uimg-0 img-1                                 +            a      power-domain@29         2           a          power-domain@30         2                    $      %           uipe ipe-0 ipe-1                    a             power-domain@31         2         (     &       &      &      &      &           ucam-0 cam-1 cam-2 cam-3 cam-4                                   +            a      power-domain@32         2            a          power-domain@33         2   !        a          power-domain@34         2   "        a                   power-domain@0          2                       a          power-domain@1          2                      a          power-domain@2          2           a          power-domain@3          2           a          power-domain@4          2                 5      7        ucsi_rx_top csi_rx_top1          a          power-domain@5          2              '           uether           a          power-domain@6          2                 X      n        uadsp adsp1                       +                       a      power-domain@7          2                  g      "      n      2        uaudio audio1 audio2 audio3                     a                   watchdog@10007000             mediatek,mt8195-wdt                  2     p                              .      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           2                                         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         2    p                      	                  (      pwrap@10024000            mediatek,mt8195-pwrap syscon            2    @                pwrap                                                    	  uspi wrap                  $                 pmic              mediatek,mt6359                  ^                                  adc           mediatek,mt6359-auxadc                   audio-codec           mediatek,mt6359-codec         regulators            mediatek,mt6359-regulator      buck_vs1            	vs1          5         0 !        H             d      buck_vgpu11         	vgpu11                   0 7        x          H                              d      buck_vmodem         	vmodem                   0         x  *        H         buck_vpu            	vpu                  0 7        x          H                              d      buck_vcore          	vcore                    0          x          H                              d      buck_vs2            	vs2          5         0 j         H             d      buck_vpa            	vpa                   0 7        H  ,      buck_vproc2         	vproc2                   0 7        x  L        H                              d      buck_vproc1         	vproc1                   0 7        x  L        H                              d      buck_vcore_sshub            	vcore_sshub                  0 7      buck_vgpu11_sshub           	vgpu11_sshub                     0 7      ldo_vaud18          	vaud18           w@        0 w@        H         ldo_vsim1           	vsim1                    0 /M`      ldo_vibr            	vibr             O        0 2Z      ldo_vrf12           	vrf12                    0           d      ldo_vusb            	vusb             -        0 -        H           d           B      ldo_vsram_proc2         	vsram_proc2                   0         x  L        H            d      ldo_vio18           	vio18                    0         H           d      ldo_vcamio          	vcamio                   0       ldo_vcn18           	vcn18            w@        0 w@        H         ldo_vfe28           	vfe28            *        0 *        H   x      ldo_vcn13           	vcn13                    0        ldo_vcn33_1_bt          	vcn33_1_bt           *        0 5g      ldo_vcn33_1_wifi            	vcn33_1_wifi             *        0 5g      ldo_vaux18          	vaux18           w@        0 w@        H            d      ldo_vsram_others            	vsram_others                      0         x          H            d      ldo_vefuse          	vefuse                   0       ldo_vxo22           	vxo22            w@        0 !         d      ldo_vrfck           	vrfck            `        0       ldo_vrfck_1         	vrfck                    0 j       ldo_vbif28          	vbif28           *        0 *        H         ldo_vio28           	vio28            *        0 2Z         d      ldo_vemc            	vemc             ,@         0 2Z      ldo_vemc_1          	vemc             &%        0 2Z           E      ldo_vcn33_2_bt          	vcn33_2_bt           *        0 5g      ldo_vcn33_2_wifi            	vcn33_2_wifi             *        0 5g      ldo_va12            	va12             O        0           d      ldo_va09            	va09             5         0 O      ldo_vrf18           	vrf18                    0 P      ldo_vsram_md          	  	vsram_md                      0         x  *        H            d      ldo_vufs            	vufs                     0            F      ldo_vm18            	vm18                     0          d      ldo_vbbck           	vbbck                    0 O         d      ldo_vsram_proc1         	vsram_proc1                   0         x  L        H            d      ldo_vsim2           	vsim2                    0 /M`      ldo_vsram_others_sshub          	vsram_others_sshub                    0          rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi             2    p                            pmif spmimst                               E      (  upmif_sys_ck pmif_tmr_ck spmimst_clk_mux               $                                   +       mt6315@6              mediatek,mt6315-regulator           2          regulators     vbuck1          	Vbcpu                    0 7        H           x  j                           d            mt6315@7              mediatek,mt6315-regulator           2          regulators     vbuck1          	Vgpu             	h        0 7        H           x  j                           d           o               infra-iommu@10315000              mediatek,mt8195-iommu-infra         2    1P       P       P                                                                                         O      mailbox@10320000              mediatek,mt8195-gce         2    2        @                                                                 mailbox@10330000              mediatek,mt8195-gce         2    3        @                                                           p      scp@10500000              mediatek,mt8195-scp       0  2    P             r             p                 sram cfg l1tcm                               okay               )        mediatek/mt8195/scp.img            q      clock-controller@10720000             mediatek,mt8195-scp_adsp            2    r                               *      dsp@10803000              mediatek,mt8195-dsp          2    0                           	  cfg sram          ,        X         n         *          #      K  uadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             +           rx tx              ,   -      	  disabled          mailbox@10816000              mediatek,mt8195-adsp-mbox                       2    `                                        ,      mailbox@10817000              mediatek,mt8195-adsp-mbox                       2    p                                        -      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           2                                   +                 6                  .         	  audiosys                                                               g      "      #      n      e      a      b      c      d      2   *            uclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  disabled                     serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           2                                                          	  ubaud bus            okay            default         -   /      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           2                                                          	  ubaud bus            okay            default         -   0         7      serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           2                                                          	  ubaud bus            okay            default         -   1         7      serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           2                                                         	  ubaud bus            okay            default         -   2      serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           2                                                         	  ubaud bus            okay            default         -   3      serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           2                                                         	  ubaud bus          	  disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           2                                    umain                       okay                     syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           2     0                              '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            2                                                                     uparent-clk sel-clk spi-clk          okay            default         -   4        G       tpm@0         !    infineon,slb9670 tcg,tpm_tis-spi            2            [I         thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         2                                                                        m   5   6      $  ylvts-calib-data-1 lvts-calib-data-2                             svs@1100bc00              mediatek,mt8195-svs         2                                                         umain            m   7   5      (  ysvs-calibration-data t-calibration-data                       svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           2                                              +                            *      0        umain mm       	  disabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           2                                                           +      N        umain mm       	  disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            2                                                             3        uparent-clk sel-clk spi-clk          okay            default         -   8        G          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            2                                                             4        uparent-clk sel-clk spi-clk        	  disabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            2    0                                                        5        uparent-clk sel-clk spi-clk        	  disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            2                                                            <        uparent-clk sel-clk spi-clk        	  disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            2                                                            =        uparent-clk sel-clk spi-clk        	  disabled          spi@1101d000              mediatek,mt8195-spi-slave           2                                                R        uspi                                   	  disabled          spi@1101e000              mediatek,mt8195-spi-slave           2                                                S        uspi                                   	  disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           2           @                              macirq        .  uaxi apb mac_main ptp_ref rmii_internal mac_cg         0     '       '         R      S      T   '                 R      S      T                                     +                         9           :           ;                                          okay          	  %rgmii-id            .   <        default sleep           -   =        9   >         C   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916            2                 ^           T  '        d 8        v      ]               <         stmmac-axi-config                                                                     9      rx-queues-config                                   :   queue0                             queue1                             queue2                             queue3                                tx-queues-config                                   ;   queue0          &                    2          queue1          &                    2         queue2          &                    2         queue3          &                    2               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           2            -     >              	  mac ippc            L                     ?                      +                                       /            B        usys_ck ref_ck mcu_ck            @   ?      @            E        S   A      g        okay            jhost            r   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          2                       mac                                     ,      -                          $        /                     B      $  usys_ck ref_ck mcu_ck dma_ck xhci_ck         okay             mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          2    #                                                                              usource hclk source_cg           okay            default state_uhs           -   C        9   D                   _          L                                                                          E        	   F      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          2    $                                                                      $        usource hclk source_cg                                       okay            default state_uhs           -   G   H        9   G        	                            _          	         	)         	6         	D           I        	   J      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          2    %                                                                       I        usource hclk source_cg                                      	  disabled          ufshci@11270000           mediatek,mt8195-ufshci          2    '        #                               @   K      @        ?      @      A      6      7      8      Z      ]      X  uufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @  	K                                                                         	Y      	  disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            2    '                                                                  m   5   6      $  ylvts-calib-data-1 lvts-calib-data-2                             usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           2    )             )>              	  mac ippc                                 @   L                 .      /                          $     '                     '         $  usys_ck ref_ck mcu_ck dma_ck xhci_ck         S   A      h         E        okay            r   B        	r         usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           2    *       -    *>              	  mac ippc            L            *        ?                      +                                      0                         '            '           usys_ck ref_ck mcu_ck            @   M            E        S   A      i        okay            r   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          2                       mac                                    1                         '           usys_ck          okay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           2    +       -    +>              	  mac ippc            L            +        ?                      +                                      2                         '            '   	        usys_ck ref_ck mcu_ck            @   N            E        S   A      j        okay            r   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          2                       mac                                    3                         '   	        usys_ck          okay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           &pci                      +           2    /        @       	  pcie-mac                                 	             8  L                                                            	       O              	          0        V      #      &      +      K   '         /  upl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                G                      @   P      	  	pcie-phy               +            ^           	                     `  	                  Q                      Q                     Q                     Q           okay            default         -   R   interrupt-controller                                  ^              Q         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           &pci                      +           2    /       @       	  pcie-mac                                 	             8  L       $       $                  $       $                 	       O              	          (        W         X         Q   '         /  upl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                H                      @   S         	  	pcie-phy               +           ^           	                     `  	                  T                      T                     T                     T           okay            default         -   U   interrupt-controller                                  ^              T         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         2    2                      9                     o   '      '           uspi sf axi                       +            okay            default         -   V   flash@0           jedec,spi-nor           2            [u         	           	            efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            2                                  +      usb3-tx-imp@184,1           2             	                  e      usb3-rx-imp@184,2           2             	                 d      usb3-intr@185           2             	                 c      usb3-tx-imp@186,1           2             	                  b      usb3-rx-imp@186,2           2             	                 a      usb3-intr@187           2             	                 `      usb2-intr-p0@188,1          2             	             usb2-intr-p1@188,2          2             	            usb2-intr-p2@189,1          2             	            usb2-intr-p3@189,2          2             	            pciephy-rx-ln1@190,1            2             	                  l      pciephy-tx-ln1-nmos@190,2           2             	                 k      pciephy-tx-ln1-pmos@191,1           2             	                  j      pciephy-rx-ln0@191,2            2             	                 i      pciephy-tx-ln0-nmos@192,1           2             	                  h      pciephy-tx-ln0-pmos@192,2           2             	                 g      pciephy-glb-intr@193            2             	                  f      dp-data@1ac         2                      lvts1-calib@1bc         2                5      lvts2-calib@1d0         2     8           6      svs-calib@580           2     d           7      socinfo-data1@7a0           2              t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           L                     okay       usb-phy@0           2                             uref         	              M         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           L                     okay       usb-phy@0           2                             uref         	              N         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         2                                mipi_tx0_pll                        	          	  disabled                     dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         2                                mipi_tx1_pll                        	          	  disabled                     i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2                 "                                                   W          ;      	  umain dma                         +          	  disabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2                "                                                    W         ;      	  umain dma                         +            okay            X         -   X        default    pmic@34           mediatek,mt6360         2   4                       e           IRQB            ^      regulator             mediatek,mt6360-regulator           
   Y        
   Y        
'   Y   buck1         	  	emi_vdd2             	'        0 w@                           d      buck2         	  	emi_vddq                     0                             d      ldo1            	mt6360_ldo1          O        0 6                     ldo2            	panel1_p1v8          w@        0 w@                     ldo3            	vmc_pmu          w@        0 2Z                          J      ldo5          	  	vmch_pmu             2Z        0 2Z                          I      ldo6            	mt6360_ldo6                   0                        ldo7            	emi_vmddr_en             w@        0 w@                        d               i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2                 "                                                   W         ;      	  umain dma                         +          	  disabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          2    0                              W      hdmi-phy@11d5f000             mediatek,mt8195-hdmi-phy            2                           P                          upll_ref 26m pll1 pll2           hdmi_txpll                      	            
7   
        
F         	  disabled                     i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2                 "                                                    Z          ;      	  umain dma                         +            okay            default         -   [        X       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2                "                                                    Z         ;      	  umain dma                         +            okay            default         -   \        X       i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2                 "                                                   Z         ;      	  umain dma                         +            okay            default         -   ]        X       i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2    0            "                                                   Z         ;      	  umain dma                         +            okay            default         -   ^        X       i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2    @            "                                                    Z         ;      	  umain dma                         +            okay            X         -   _        default       clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          2    P                              Z      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           L                        +           okay       usb-phy@0           2                                uref da_ref          	              L      usb-phy@700         2                                  uref da_ref          m   `   a   b        yintr rx_imp tx_imp          	              S         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           L                     okay       usb-phy@0           2                                uref da_ref          	              ?      usb-phy@700         2                                  uref da_ref          m   c   d   e        yintr rx_imp tx_imp          	              @         phy@11e80000              mediatek,mt8195-pcie-phy            2                     sif         m   f   g   h   i   j   k   l      G  yglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1             +           	            okay               P      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           2                                 
  uunipro mp           	          	  disabled               K      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           2             @            m          0                                                 job mmu gpu         
X   n      (     +   
   +      +      +      +           
lcore0 core1 core2 core3 core4           okay            
   o      clock-controller@13fbf000             mediatek,mt8195-mfgcfg          2                                  m      syscon@14000000           mediatek,mt8195-vppsys0 syscon          2                                 
   p                            dma-controller@14001000           mediatek,mt8195-mdp3-rdma           2                     
   p                  
              
   q           +           
   r                       <     p         p         p         p         p              
         display@14002000              mediatek,mt8195-mdp3-fg         2                      
   p                                display@14003000              mediatek,mt8195-mdp3-stitch         2     0                
   p      0                        display@14004000              mediatek,mt8195-mdp3-hdr            2     @                
   p      @                  "      display@14005000              mediatek,mt8195-mdp3-aal            2     P                      F               
   p      P                  
           +         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           2     `                
   p      `            
    %                    display@14007000              mediatek,mt8195-mdp3-tdshp          2     p                
   p      p                  #      display@14008000              mediatek,mt8195-mdp3-color          2                           I               
   p                        $           +         display@14009000              mediatek,mt8195-mdp3-ovl            2                           J               
   p                        %           +           
   r         display@1400a000              mediatek,mt8195-mdp3-padding            2                     
   p                                   +         display@1400b000              mediatek,mt8195-mdp3-tcc            2                     
   p                              dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         2                     
   p                  
    +                      
   r              +           
         mutex@1400f000            mediatek,mt8195-vpp-mutex           2                           P               
   p                                   +         smi@14010000              mediatek,mt8195-smi-sub-common          2                                               uapb smi gals0           
   s           +              t      smi@14011000              mediatek,mt8195-smi-sub-common          2                                              uapb smi gals0           
   s           +                    smi@14012000              mediatek,mt8195-smi-common-vpp          2                                                      uapb smi gals0 gals1            +              s      larb@14013000             mediatek,mt8195-smi-larb            2    0                
           
   t                            uapb smi            +              w      iommu@14018000            mediatek,mt8195-iommu-vpp           2                  8  
   u   v   w   x   y   z   {   |   }   ~                          R                             ubclk                          +              r      clock-controller@14e00000             mediatek,mt8195-wpesys          2                                         clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         2                              clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         2    0                         larb@14e04000             mediatek,mt8195-smi-larb            2    @                
           
                               uapb smi            +                    larb@14e05000             mediatek,mt8195-smi-larb            2    P                
           
   s                                  uapb smi gals               +              y      syscon@14f00000           mediatek,mt8195-vppsys1 syscon          2                                
   p   	                        mutex@14f01000            mediatek,mt8195-vpp-mutex           2                          {               
   p   	                    '           +         larb@14f02000             mediatek,mt8195-smi-larb            2                     
           
                                     uapb smi gals               +                    larb@14f03000             mediatek,mt8195-smi-larb            2    0                
           
   t                                  uapb smi gals               +              x      display@14f06000              mediatek,mt8195-mdp3-split          2    `                
   p   	  `                        +      ,           +         display@14f07000              mediatek,mt8195-mdp3-tcc            2    p                
   p   	  p                        dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           2                    
   p   	              
                          
                 +           
         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           2                    
   p   	              
                  
        
                 +           
         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           2                    
   p   	              
                          
   r              +           
         display@14f0b000              mediatek,mt8195-mdp3-fg         2                    
   p   	                    	      display@14f0c000              mediatek,mt8195-mdp3-fg         2                    
   p   	                          display@14f0d000              mediatek,mt8195-mdp3-fg         2                    
   p   	                          display@14f0e000              mediatek,mt8195-mdp3-hdr            2                    
   p   	                          display@14f0f000              mediatek,mt8195-mdp3-hdr            2                    
   p   	                          display@14f10000              mediatek,mt8195-mdp3-hdr            2                     
   p   
                            display@14f11000              mediatek,mt8195-mdp3-aal            2                          i               
   p   
                               +         display@14f12000              mediatek,mt8195-mdp3-aal            2                           j               
   p   
                                +         display@14f13000              mediatek,mt8195-mdp3-aal            2    0                      k               
   p   
  0                  !           +         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           2    @                
   p   
  @            
                        display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           2    P                
   p   
  P            
                  $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           2    `                
   p   
  `            
                  %      display@14f17000              mediatek,mt8195-mdp3-tdshp          2    p                
   p   
  p                        display@14f18000              mediatek,mt8195-mdp3-tdshp          2                    
   p   
                    (      display@14f19000              mediatek,mt8195-mdp3-tdshp          2                    
   p   
                    )      display@14f1a000              mediatek,mt8195-mdp3-merge          2                    
   p   
                               +         display@14f1b000              mediatek,mt8195-mdp3-merge          2                    
   p   
                               +         display@14f1c000              mediatek,mt8195-mdp3-color          2                          t               
   p   
                               +         display@14f1d000              mediatek,mt8195-mdp3-color          2                    
   p   
                    u                                +         display@14f1e000              mediatek,mt8195-mdp3-color          2                          v               
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                               +         display@14f1f000              mediatek,mt8195-mdp3-ovl            2                          w               
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            display@14f20000              mediatek,mt8195-mdp3-padding            2                     
   p                                   +         display@14f21000              mediatek,mt8195-mdp3-padding            2                    
   p                                  +         display@14f22000              mediatek,mt8195-mdp3-padding            2                     
   p                                   +         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         2    0                
   p     0            
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         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         2    @                
   p     @            
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         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         2    P                
   p     P            
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         clock-controller@15000000             mediatek,mt8195-imgsys          2                                    $      larb@15001000             mediatek,mt8195-smi-larb            2                     
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        uapb smi gals               +                    smi@15002000              mediatek,mt8195-smi-sub-common          2                         $      $                 uapb smi gals0           
   s           +                    smi@15003000              mediatek,mt8195-smi-sub-common          2     0                   $       $       $   
        uapb smi gals0           
              +                    clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         2                                         larb@15120000             mediatek,mt8195-smi-larb            2                     
   
        
              $                  uapb smi            +                    clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          2                              clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         2    "                                     larb@15230000             mediatek,mt8195-smi-larb            2    #                 
           
              $                  uapb smi            +                    clock-controller@15330000             mediatek,mt8195-ipesys          2    3                               %      larb@15340000             mediatek,mt8195-smi-larb            2    4                 
           
              %      %           uapb smi            +              z      clock-controller@16000000             mediatek,mt8195-camsys          2                                    &      larb@16001000             mediatek,mt8195-smi-larb            2                     
           
              &       &       &           uapb smi gals               +                    larb@16002000             mediatek,mt8195-smi-larb            2                      
           
              &      &           uapb smi            +              {      smi@16004000              mediatek,mt8195-smi-sub-common          2     @                   &       &       &           uapb smi gals0           
              +                    smi@16005000              mediatek,mt8195-smi-sub-common          2     P                   &      &                 uapb smi gals0           
   s           +                    larb@16012000             mediatek,mt8195-smi-larb            2                     
           
                                 uapb smi            +               |      larb@16013000             mediatek,mt8195-smi-larb            2    0                
           
                                 uapb smi            +                     larb@16014000             mediatek,mt8195-smi-larb            2    @                
           
                                 uapb smi            +   !                 larb@16015000             mediatek,mt8195-smi-larb            2    P                
           
                                 uapb smi            +   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa         2                                        clock-controller@1606f000             mediatek,mt8195-camsys_yuva         2                                        clock-controller@1608f000             mediatek,mt8195-camsys_rawb         2                                        clock-controller@160af000             mediatek,mt8195-camsys_yuvb         2    
                                    clock-controller@16140000             mediatek,mt8195-camsys_mraw         2                                         larb@16141000             mediatek,mt8195-smi-larb            2                    
           
              &              &           uapb smi gals               +   "                 larb@16142000             mediatek,mt8195-smi-larb            2                     
           
                                 uapb smi            +   "                 clock-controller@17200000             mediatek,mt8195-ccusys          2                                          larb@17201000             mediatek,mt8195-smi-larb            2                     
           
                                 uapb smi            +              }      video-codec@18000000              mediatek,mt8195-vcodec-dec          
   q        
                          +            2                   @                L                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         2                       
   r     r                 A                          usel vdec lat top                  A                         +         video-codec@10000             mediatek,mtk-vcodec-lat         2                                         0  
                                              A                          usel vdec lat top                  A                         +         video-codec@25000             mediatek,mtk-vcodec-core            2     P                                   P  
                                                                 A                          usel vdec lat top                  A                         +            larb@1800d000             mediatek,mt8195-smi-larb            2                     
           
                                 uapb smi            +                    larb@1800e000             mediatek,mt8195-smi-larb            2                     
           
                                uapb smi            +                    clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         2                                         larb@1802e000             mediatek,mt8195-smi-larb            2                    
           
                                 uapb smi            +                    clock-controller@1802f000             mediatek,mt8195-vdecsys         2                                        larb@1803e000             mediatek,mt8195-smi-larb            2                    
           
                                 uapb smi            +                    clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           2                                         clock-controller@190f3000             mediatek,mt8195-apusys_pll          2    0                         clock-controller@1a000000             mediatek,mt8195-vencsys         2                                    !      larb@1a010000             mediatek,mt8195-smi-larb            2                     
           
              !      !           uapb smi            +                    video-codec@1a020000              mediatek,mt8195-vcodec-enc          2                   H  
     `     a     b     c     d     v     w     x     y              U               
   q           !         	  uvenc_sel                  @                         +                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec             +         0  
     m     n     r     s     t     u                     +         0  L                                            jpgdec@0,0            mediatek,mt8195-jpgdec-hw           2                     0  
     m     n     r     s     t     u              W                  !           ujpgdec             +         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw           2                    0  
     m     n     r     s     t     u              X                  !           ujpgdec             +         jpgdec@1,0            mediatek,mt8195-jpgdec-hw           2                    0  
   r     r     r     r     r     r                \                  "           ujpgdec             +            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           2                                    "      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            2                                                 
                             jpeg-encoder@1a030000             mediatek,mt8195-jpgenc             +            
   r     r     r     r                       +         0  L                                            jpgenc@0,0            mediatek,mt8195-jpgenc-hw           2                        
     g     h     i     l              V                  !           ujpgenc             +         jpgenc@1,0            mediatek,mt8195-jpgenc-hw           2                       
   r     r     r     r                [                  "           ujpgenc             +            larb@1b010000             mediatek,mt8195-smi-larb            2                     
           
   s           "      "                  uapb smi gals               +              ~      ovl@1c000000              mediatek,mt8195-disp-ovl            2                            |                  +                          
              
                ports                        +       port@0          2       endpoint             port@1          2      endpoint                                         rdma@1c002000             mediatek,mt8195-disp-rdma           2                            ~                  +                         
               
                ports                        +       port@0          2       endpoint                                   port@1          2      endpoint                                         color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           2     0                                        +                         
        0       ports                        +       port@0          2       endpoint                                   port@1          2      endpoint                                         ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           2     @                                        +                         
        @       ports                        +       port@0          2       endpoint                                   port@1          2      endpoint                                         aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           2     P                                        +                         
        P       ports                        +       port@0          2       endpoint                                   port@1          2      endpoint                                         gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           2     `                                        +                         
        `       ports                        +       port@0          2       endpoint                                   port@1          2      endpoint                                         dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         2     p                                        +                 	        
        p       ports                        +       port@0          2       endpoint                                   port@1          2      endpoint                   dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         2                                             +                       *           uengine digital hs           @           	dphy          	  disabled          dsc@1c009000              mediatek,mt8195-disp-dsc            2                                             +                         
                  dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         2                                             +                       +           uengine digital hs           @           	dphy          	  disabled          merge@1c014000            mediatek,mt8195-disp-merge          2    @                                        +                         
        @          dp-intf@1c015000              mediatek,mt8195-dp-intf         2    P                                        +                 ,                    upixel engine pll          	  disabled          mutex@1c016000            mediatek,mt8195-disp-mutex          2    `                                        +                         
        `            
  U      larb@1c018000             mediatek,mt8195-smi-larb            2                    
            
                 (      (              uapb smi gals               +                    larb@1c019000             mediatek,mt8195-smi-larb            2                    
           
   s              (                     uapb smi gals               +              u      syscon@1c100000           mediatek,mt8195-vdosys1 syscon          2                                      
                                              #      smi@1c01b000              mediatek,mt8195-smi-common-vdo          2                           %      &      )      $        uapb smi gals0 gals1            +                    iommu@1c01f000            mediatek,mt8195-iommu-vdo           2                  8  
                                                                                        '        ubclk               +                    mutex@1c101000            mediatek,mt8195-disp-mutex          2                                            +              #           
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   #           umerge merge_async              +           
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                                #         vpp-merge@1c110000            mediatek,mt8195-disp-merge          2                                             #      #           umerge merge_async              +           
                      '           #         dpi@1c112000              mediatek,mt8195-dpi         2                        #   -   #      #   2        upixel engine pll                                     +              #         	  disabled       ports                        +       port@0          2       endpoint             port@1          2      endpoint                   dp-intf@1c113000              mediatek,mt8195-dp-intf         2    0                                        +              #   /   #                 upixel engine pll          	  disabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  2    @            P            p                                                              4  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  
        @            P            p                                                          h     #   %   #       #   #   #   !   #   $   #   "   #   1   #   &   #   '   #   (   #   )   #   *              umixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top             +           
   r   d   r   e                           (     #   3   #   4   #   5   #   6   #   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          hdmi-tx@1c300000              mediatek,mt8195-hdmi-tx                    2    0                        Q      L      M      ,        ubus hdcp hdcp24m hdmi-split               L                                              +           @           	hdmi          	  disabled       i2c           mediatek,mt8195-hdmi-ddc                     ports                        +       port@0          2       endpoint             port@1          2      endpoint                   edp-tx@1c500000           mediatek,mt8195-edp-tx          2    P                 m           ydp_calibration_data            +                                >        	  disabled          dp-tx@1c600000            mediatek,mt8195-dp-tx           2    `                 m           ydp_calibration_data            +                                >        	  disabled             thermal-zones      cpu0-thermal            O          ]           s         trips      trip-alert           L                  -passive                  trip-crit                            	  -critical             cooling-maps       map0                     0     	   
                  cpu1-thermal            O          ]           s         trips      trip-alert           L                  -passive                  trip-crit                            	  -critical             cooling-maps       map0                     0     	   
                  cpu2-thermal            O          ]           s         trips      trip-alert           L                  -passive                  trip-crit                            	  -critical             cooling-maps       map0                     0     	   
                  cpu3-thermal            O          ]           s         trips      trip-alert           L                  -passive                  trip-crit                            	  -critical             cooling-maps       map0                     0     	   
                  cpu4-thermal            O          ]           s          trips      trip-alert           L                  -passive                  trip-crit                            	  -critical             cooling-maps       map0                     0                          cpu5-thermal            O          ]           s         trips      trip-alert           L                  -passive                  trip-crit                            	  -critical             cooling-maps       map0                     0                          cpu6-thermal            O          ]           s         trips      trip-alert           L                  -passive                  trip-crit                            	  -critical             cooling-maps       map0                     0                          cpu7-thermal            O          ]           s         trips      trip-alert           L                  -passive                  trip-crit                            	  -critical             cooling-maps       map0                     0                          vpu0-thermal            O          ]           s         trips      trip-alert           L                  -passive       trip-crit                            	  -critical                vpu1-thermal            O          ]           s      	   trips      trip-alert           L                  -passive       trip-crit                            	  -critical                gpu-thermal         O          ]           s      
   trips      trip-alert           L                  -passive       trip-crit                            	  -critical                gpu1-thermal            O          ]           s         trips      trip-alert           L                  -passive       trip-crit                            	  -critical                vdec-thermal            O          ]           s         trips      trip-alert           L                  -passive       trip-crit                            	  -critical                img-thermal         O          ]           s         trips      trip-alert           L                  -passive       trip-crit                            	  -critical                infra-thermal           O          ]           s         trips      trip-alert           L                  -passive       trip-crit                            	  -critical                cam0-thermal            O          ]           s         trips      trip-alert           L                  -passive       trip-crit                            	  -critical                cam1-thermal            O          ]           s         trips      trip-alert           L                  -passive       trip-crit                            	  -critical                cpu-thermal         O          ]            s      trips      trip-alert           L                  -passive       trip-crit            s                	  -critical                pcb-top-thermal         O          ]            s      trips      trip-alert           $                  -passive       trip-crit            L                	  -critical                pcb-bottom-thermal          O          ]            s      trips      trip-alert           $                  -passive       trip-crit            L                	  -critical                   chosen          serial0:115200n8          firmware       optee             linaro,optee-tz         =smc          gpio-keys         
    gpio-keys           default         -      key-0           |      j         
  volume_up              s         E                    leds          
    gpio-leds           default         -      led-0           |      k            keep            power                       memory@40000000         &memory          2    @                regulator-vsys            regulator-fixed         	vsys             d                  LK@        0 LK@           Y      reserved-memory                      +            L   optee@43200000                   2    C                memory@50000000           shared-dma-pool         2    P                             )      memory@53000000           shared-dma-pool         2    S       @        memory@54600000                  2    T`                memory@60000000           shared-dma-pool         2    `                        memory@62000000           shared-dma-pool         2    b       @           thermal-sensor-0              generic-adc-thermal                                    sensor-channel          0X    ^h    nx        j      '  {  :    N     a  o  u0  /       @          P        u  `   a     Q p   D $   9 8   0 L   ) _   # s        (        8        H       
 X   	 "    6h    I                    thermal-sensor-1              generic-adc-thermal                                   sensor-channel          0X    ^h    nx        j      '  {  :    N     a  o  u0  /       @          P        u  `   a     Q p   D $   9 8   0 L   ) _   # s        (        8        H       
 X   	 "    6h    I                    thermal-sensor-2              generic-adc-thermal                                   sensor-channel          0X    ^h    nx        j      '  {  :    N     a  o  u0  /       @          P        u  `   a     Q p   D $   9 8   0 L   ) _   # s        (        8        H       
 X   	 "    6h    I                       	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dpi1 gce0 gce1 hdmi0 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 mmc0 mmc1 serial0 serial1 serial2 serial3 serial4 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux drive-strength input-enable output-high input-disable bias-disable bias-pull-up drive-strength-microamp bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells memory-region firmware-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 uart-has-rtscts mediatek,pad-select spi-max-frequency nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,mac-wol reset-assert-us reset-deassert-us reset-gpios snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup dr_mode vusb33-supply bus-width hs400-ds-delay cap-mmc-highspeed cap-mmc-hw-reset mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable vmmc-supply vqmmc-supply cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc freq-table-hz mediatek,ufs-disable-mcq mediatek,u3p-dis-msk bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map spi-rx-bus-width spi-tx-bus-width bits #phy-cells LDO_VIN1-supply LDO_VIN2-supply LDO_VIN3-supply mediatek,ibias mediatek,ibias_up operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path label linux,code debounce-interval default-state function color regulator-boot-on no-map io-channels io-channel-names temperature-lookup-table 