 w   8 i   (             h                             4    mediatek,mt8395-evk mediatek,mt8395 mediatek,mt8195                                  +         "   7MediaTek Genio 1200 EVK-P1V2-EMMC      aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dpi@1c112000            T/soc/mailbox@10320000            Y/soc/mailbox@10330000            ^/soc/hdmi-tx@1c300000            d/soc/hdr-engine@1c114000             k/soc/mutex@1c016000          r/soc/mutex@1c101000          y/soc/vpp-merge@1c10c000          /soc/vpp-merge@1c10d000          /soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000             /soc/serial@11001100             /soc/ethernet@11021000        cpus                         +       cpu@0           cpu           arm,cortex-a55                      psci            $               8ec3@        H  4        [              k           x   @                                 @                                                             cpu@100         cpu           arm,cortex-a55                     psci            $               8ec3@        H  4        [              k           x   @                                 @                                                             cpu@200         cpu           arm,cortex-a55                     psci            $               8ec3@        H  4        [              k           x   @                                 @                                                             cpu@300         cpu           arm,cortex-a55                     psci            $               8ec3@        H  4        [              k           x   @                                 @                                                             cpu@400         cpu           arm,cortex-a78                     psci            $              8f        H           [              k           x   @                                 @                      	                      
                 cpu@500         cpu           arm,cortex-a78                     psci            $              8f        H           [              k           x   @                                 @                      	                      
                 cpu@600         cpu           arm,cortex-a78                     psci            $              8f        H           [              k           x   @                                 @                      	                      
                 cpu@700         cpu           arm,cortex-a78                     psci            $              8f        H           [              k           x   @                                 @                      	                      
                 cpu-map    cluster0       core0                    core1                    core2                    core3                    core4                    core5                    core6                    core7                          idle-states         psci       cpu-retention-l           arm,idle-state                             /   2        @   _        P  D                 cpu-retention-b           arm,idle-state                             /   -        @           P                   cpu-off-l             arm,idle-state                            /   7        @           P  H                 cpu-off-b             arm,idle-state                            /   2        @           P                      l2-cache0             cache           a           m           z   @                               m                 l2-cache1             cache           a           m           z   @                               m           	      l3-cache              cache           a           m            z   @                    m                    dsu-pmu           arm,dsu-pmu         {                                                       fail          dmic-codec            dmic-codec                              mt8195-sound                       okay              mediatek,mt8195_mt6359           7mt8395-evk          default                  ,  Headphone Headphone L Headphone Headphone R               headphone-dai-link        
  DL_SRC_BE      codec                           hdmi-dai-link           ETDM3_OUT_BE       codec                              fixed-factor-clock-13m            fixed-factor-clock          	                                  '           2clk13m             0      oscillator-26m            fixed-clock         	            8        2clk26m                   oscillator-32k            fixed-clock         	            8           2clk32k        performance-controller@11bc10             mediatek,cpufreq-hw                           0               E                    opp-table-gpu             operating-points-v2          _              opp-390000000           j    >        q 	h      opp-410000000           j    p        q 	      opp-431000000           j            q 	      opp-473000000           j    1h@        q 	<      opp-515000000           j    F        q 	<      opp-556000000           j    !#         q 	Ҧ      opp-598000000           j    #        q 	      opp-640000000           j    &%         q 	      opp-670000000           j    'c        q 
      opp-700000000           j    )'         q 
L      opp-730000000           j    +        q 
}      opp-760000000           j    -L         q 
`      opp-790000000           j    /q        q 
4      opp-820000000           j    05         q       opp-850000000           j    2        q @      opp-880000000           j    4s         q q         pmu-a55           arm,cortex-a55-pmu                      {                  pmu-a78           arm,cortex-a78-pmu                      {                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  {                                             
             soc                      +             simple-bus                                             interrupt-controller@c000000              arm,gic-v3                                                                                          {      	                     ppi-partitions     interrupt-partition-0                                        interrupt-partition-1                                              syscon@10000000            mediatek,mt8195-topckgen syscon                               	                    syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon                               	                                syscon@10003000           mediatek,mt8195-pericfg syscon               0                	              L      pinctrl@10005000              mediatek,mt8195-pinctrl              P                                                                                                         B  iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint                               
                               {                                       audio-default-pins                pins-cmd-dat          4    =  >  A  B  C  D  E  F  G  H  I  J  K         disp-pwm1-default-pins     pins1             h         edp-panel-12v-en-pins                 pins1             `                   edp-panel-3v3-en-pins                 pins1                                eth-default-pins               H   pins-cc           U  V  W  X        )         pins-mdio             Y  Z         8      pins-power            [   \                pins-rxd              Q  R  S  T      pins-txd              M  N  O  P        )            eth-sleep-pins             I   pins-cc           U   V   W   X       pins-mdio             Y   Z          E         S      pins-rxd              Q   R   S   T       pins-txd              M   N   O   P          gpio-keys-pins     pins              j          `         8         hdmi-vreg-pins             l   pins-pwr                       S         hdmi-pins                 pins-hotplug                        m      pins-ddc              "  #        )   
      pins-cec              !         S         i2c0-pins              n   pins                	        `           |           i2c1-pins              o   pins              
          `           |           i2c2-pins              r   pins                        `           )            i2c6-pins              f   pins                         `         mmc0-default-pins              Q   pins-clk              z        )           m   f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y         8        )           `   e      pins-rst              x        )           `   e         mmc0-uhs-pins              R   pins-clk              z        )           m   f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y         8        )           `   e      pins-ds                   )           m   f      pins-rst              x        )           `   e         mmc1-default-pins              U   pins-clk              o        )           m   f      pins-cmd-dat              n  p  q  r  s         8        )           `   e         mmc1-uhs-pins              V   pins-clk              o        )           m   f      pins-cmd-dat              n  p  q  r  s         8        )           `   e         mt6360-pins            g   pins                           8         `         dsi0-vreg-en-pins                 pins-pwr-en           /                   panel-default-pins                pins-rst              l                pins-en           0                   pcie0-default-pins             a   pins                           `         pcie0-idle-pins            b   pins                        S                  pcie1-default-pins             d   pins                           `         disp-pwm0-pins             ?   pins-disp-pwm             a         spi1-pins              @   pins                             S         spi-pins               C   pins                             S         touch-pins             q   pins-irq                        8         S      pins-reset                               u3-p0-vbus-default-pins            M   pins-vbus             ?         8         uart0-pins             :   pins              b  c         uart1-pins             ;   pins              d  e  f  g            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8195-power-controller                         +                          3   power-domain@8                                  +                             power-domain@9             	                            mfg alt                                  +                          !   power-domain@10            
                  power-domain@11                              power-domain@12                              power-domain@13                              power-domain@14                                    power-domain@15                                            	      @      A      K         "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "           vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18                                    +                  power-domain@16                  8           #   $   #   %   #   &   #   '   #   (   #   )      D  vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5                                  +                  power-domain@17                             $      $           vppsys1 vppsys1-0 vppsys1-1                               power-domain@22                        %      %      %      %         $  wepsys-0 wepsys-1 wepsys-2 wepsys-3                               power-domain@23                       &            vdec0-0                                  +                   power-domain@24                       '            vdec1-0                               power-domain@25                       (            vdec2-0                                  power-domain@26                       )            venc0-larb                                   +                   power-domain@27                       *            venc1-larb                                   power-domain@18                              +       +      +         &  vdosys1 vdosys1-0 vdosys1-1 vdosys1-2                                    +                  power-domain@19                                          power-domain@20                                          power-domain@21                          Q        hdmi_tx                      power-domain@28                       ,       ,   
        img-0 img-1                                  +                  power-domain@29                              power-domain@30                             ,      -           ipe ipe-0 ipe-1                                  power-domain@31                  (     .       .      .      .      .           cam-0 cam-1 cam-2 cam-3 cam-4                                    +                  power-domain@32                               power-domain@33            !                  power-domain@34            "                           power-domain@0                                            power-domain@1                                           power-domain@2                               power-domain@3                               power-domain@4                           5      7        csi_rx_top csi_rx_top1                    power-domain@5                        /           ether                     power-domain@6                           X      n        adsp adsp1                       +                              power-domain@7                            g      "      n       2        audio audio1 audio2 audio3                                         watchdog@10007000             mediatek,mt8195-wdt                       p                              8      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon                                	                    timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer             p                {      	                  0      pwrap@10024000            mediatek,mt8195-pwrap syscon                @                pwrap           {                                           	  spi wrap                  $                 pmic              mediatek,mt6359                                        /                       adc           mediatek,mt6359-auxadc          C         audio-codec           mediatek,mt6359-codec           U           i           }         regulators            mediatek,mt6359-regulator      buck_vs1            vs1          5          !                           buck_vgpu11         vgpu11                    7                                                       buck_vmodem         vmodem                               *                 buck_vpu            vpu                   7                                                       buck_vcore          vcore                                                                                        buck_vs2            vs2          5          j                            buck_vpa            vpa                    7          ,      buck_vproc2         vproc2                    7           L                                   buck_vproc1         vproc1                    7           L                                   buck_vcore_sshub            vcore_sshub                   7      buck_vgpu11_sshub           vgpu11_sshub                      7      ldo_vaud18          vaud18           w@         w@                          ldo_vsim1           vsim1                     /M`      ldo_vibr            vibr             O         2Z           s      ldo_vrf12           vrf12                                     ldo_vusb            vusb             -         -                              N      ldo_vsram_proc2         vsram_proc2                               L                          ldo_vio18           vio18                                              ldo_vcamio          vcamio                                   ldo_vcn18           vcn18            w@         w@                 ldo_vfe28           vfe28            *         *           x      ldo_vcn13           vcn13                            ldo_vcn33_1_bt          vcn33_1_bt           *         5g      ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g      ldo_vaux18          vaux18           w@         w@                          ldo_vsram_others            vsram_others             q         q                                 !      ldo_vefuse          vefuse                          ldo_vxo22           vxo22            w@         !               ldo_vrfck           vrfck            `               ldo_vrfck_1         vrfck                     j       ldo_vbif28          vbif28           *         *                 ldo_vio28           vio28            *         2Z               ldo_vemc            vemc             ,@          2Z      ldo_vemc_1          vemc             &%         2Z           S      ldo_vcn33_2_bt          vcn33_2_bt           2Z         2Z           B      ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g      ldo_va12            va12             O                         ldo_va09            va09             5          O      ldo_vrf18           vrf18                     P      ldo_vsram_md          	  vsram_md                                  *                 ldo_vufs            vufs                                 T      ldo_vm18            vm18                                     ldo_vbbck           vbbck                     O               ldo_vsram_proc1         vsram_proc1                               L                          ldo_vsim2           vsim2                     /M`      ldo_vsram_others_sshub          vsram_others_sshub                              rtc           mediatek,mt6358-rtc       keys              mediatek,mt6359-keys            -           F       power-key           Y   t         h      home            Y   f               spmi@10027000             mediatek,mt8195-spmi                 p                            pmif spmimst                                 E      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux               $                                   +       pmic@6            mediatek,mt6315-regulator                     regulators     vbuck1          Vbcpu                     7                                                 
            pmic@7            mediatek,mt6315-regulator                     regulators     vbuck1          Vgpu             T         8                                                       infra-iommu@10315000              mediatek,mt8195-iommu-infra             1P       P       P  {                                                                         v              ^      mailbox@10320000              mediatek,mt8195-gce             2        @         {                                                         mailbox@10330000              mediatek,mt8195-gce             3        @         {                                                         scp@10500000              mediatek,mt8195-scp       0      P             r             p                 sram cfg l1tcm          {                     okay               1        mediatek/mt8195/scp.img                  clock-controller@10720000             mediatek,mt8195-scp_adsp                r                 	              2      dsp@10803000              mediatek,mt8195-dsp              0                           	  cfg sram          ,        X         n         2          #      K  adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             3           rx tx              4   5        okay               6   7                 mailbox@10816000              mediatek,mt8195-adsp-mbox                           `                {                        4      mailbox@10817000              mediatek,mt8195-adsp-mbox                           p                {                        5      mt8195-afe-pcm@10890000           mediatek,mt8195-audio                                              3           {      6                  8         	  audiosys                                                               g      "      #      n      e      a      b      c      d       2   2            clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp          okay               9                 serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart                                {                                      	  baud bus            okay               :        default       serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart                                {                                      	  baud bus            okay               ;        default       serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart                                {                                      	  baud bus          	  disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart                                {                                     	  baud bus          	  disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart                                {                                     	  baud bus          	  disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart                                {                                     	  baud bus          	  disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc                                                main            C         	  disabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon                0                	              /      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 {                                                 parent-clk sel-clk spi-clk        	  disabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap                              {                                                        <   =      $  lvts-calib-data-1 lvts-calib-data-2                             svs@1100bc00              mediatek,mt8195-svs                              {                                     main               >   <      (  svs-calibration-data t-calibration-data                        svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                                {                         3           #                 *       0        main mm         okay            default            ?                 pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                                {                     #                 +       N        main mm       	  disabled                     spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 {                                         3        parent-clk sel-clk spi-clk          okay               @        default         .            B      @      can@0             microchip,mcp2518fd                        A        K1-         /                 ]   B        h   B         spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 {                                         4        parent-clk sel-clk spi-clk          okay               C        default         .          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                0                {                                         5        parent-clk sel-clk spi-clk        	  disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                {                                         <        parent-clk sel-clk spi-clk        	  disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                {                                         =        parent-clk sel-clk spi-clk        	  disabled          spi@1101d000              mediatek,mt8195-spi-slave                               {                             R        spi                                   	  disabled          spi@1101e000              mediatek,mt8195-spi-slave                               {                             S        spi                                   	  disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a                      @         {                     wmacirq        .  axi apb mac_main ptp_ref rmii_internal mac_cg         0     /       /         R      S      T   /                 R      S      T                                     3                          D           E           F                                          okay            rgmii-rxid             G              ]                  '  '        *           ?        default sleep              H        P   I   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916                          G         stmmac-axi-config           Z           j           z                                    D      rx-queues-config                                   E   queue0                             queue1                             queue2                             queue3                                tx-queues-config                                   F   queue0                              	
          queue1                              	
         queue2                              	
         queue3                              	
               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3                       -     >              	  mac ippc                                 ?                      +           {                             /             B        sys_ck ref_ck mcu_ck            	   J      K            h        	   L      g        okay            	4otg         default            M         	<        	L   N   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 mac         {                            ,      -                          $         /                      B      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         okay          ports                        +       port@0                 endpoint            	Z   O           i         port@1                endpoint            	Z   P           j               mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              #                              {                                                  source hclk source_cg           okay            default state_uhs              Q        P   R        	j           O          	t         	         	         	         	         	        	 L        	   S        	   T         	      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              $                              {                                          $        source hclk source_cg                                       okay            default state_uhs              U        P   V        	j           O          	         

         
         
%         	        	   W        	   X         	      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              %                              {                                           I        source hclk source_cg                                      	  disabled          ufshci@11270000           mediatek,mt8195-ufshci              '        #         {                      	   Y      @         ?       @       A       6       7       8       Z       ]      X  ufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @  
,                                                                         
:      	  disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu                '                {                                                       <   =      $  lvts-calib-data-1 lvts-calib-data-2                             usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci               )             )>              	  mac ippc            {                     	   Z      [                 .      /                          $     /                     /         $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         	   L      h         h        okay            	L   N      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               *       -    *>              	  mac ippc                        *        ?                      +           {                           0                         /            /           sys_ck ref_ck mcu_ck            	   \            h        	   L      i        okay            	L   N   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 mac         {                           1                         /           sys_ck          okay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               +       -    +>              	  mac ippc                        +        ?                      +           {                           2                         /            /   	        sys_ck ref_ck mcu_ck            	   ]            h        	   L      j        okay            	L   N   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 mac         {                           3                         /   	        sys_ck          okay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +               /        @       	  pcie-mac            {                     
S             8                                                              
]       ^              
g          0         V       #       &       +       K   /         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                G                      	   _      	  
vpcie-phy               3                       
                     `  
                  `                      `                     `                     `           okay            default idle               a        P   b   interrupt-controller                                                `         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +               /       @       	  pcie-mac            {                     
S             8         $       $                  $       $                 
]       ^              
g          (         W          X          Q   /         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                H                      	   [         	  
vpcie-phy               3                      
                     `  
                  c                      c                     c                     c         	  disabled            default            d   interrupt-controller                                                c         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor             2                {      9                     o   /      /           spi sf axi                       +          	  disabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse                                              +      usb3-tx-imp@184,1                        
                  z      usb3-rx-imp@184,2                        
                 y      usb3-intr@185                        
                 x      usb3-tx-imp@186,1                        
                  w      usb3-rx-imp@186,2                        
                 v      usb3-intr@187                        
                 u      usb2-intr-p0@188,1                       
             usb2-intr-p1@188,2                       
            usb2-intr-p2@189,1                       
            usb2-intr-p3@189,2                       
            pciephy-rx-ln1@190,1                         
                        pciephy-tx-ln1-nmos@190,2                        
                       pciephy-tx-ln1-pmos@191,1                        
                        pciephy-rx-ln0@191,2                         
                 ~      pciephy-tx-ln0-nmos@192,1                        
                  }      pciephy-tx-ln0-pmos@192,2                        
                 |      pciephy-glb-intr@193                         
                  {      dp-data@1ac                               lvts1-calib@1bc                         <      lvts2-calib@1d0              8           =      svs-calib@580                d           >      socinfo-data1@7a0                         t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0                                        ref         
              \         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0                                        ref         
              ]         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx                                         2mipi_tx0_pll            	            
            okay                     dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx                                         2mipi_tx1_pll            	            
          	  disabled                     i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "               {                                    e           ;      	  main dma                         +          	  disabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                          "                {                                    e          ;      	  main dma                         +            okay            8            f        default    pmic@34           mediatek,mt6360            4                    {              wIRQB                                   g   charger           mediatek,mt6360-chg         
 @   usb-otg-vbus-regulator          usb-otg-vbus             C(         X         regulator             mediatek,mt6360-regulator           
   h   buck1         	  emi_vdd2                                                        buck2         	  emi_vddq                                                             h      ldo1          	  tp1_p3v0             2Z         2Z                                   p      ldo2            panel1_p1v8          w@         w@                                ldo3            vmc_pmu          O         6                          X      ldo5          	  vmch_pmu             )2         6                          W      ldo6            mt6360_ldo1                                           ldo7            emi_vmddr_en                                                          tcpc              mediatek,mt6360-tcpc            /                 wPD_IRQB    connector             usb-c-connector         
USB-C           
dual            
         
dual            sink            "d        ""        ,   altmodes       displayport         8          =  F         ports                        +       port@0                 endpoint            	Z   i           O         port@1                endpoint            	Z   j           P         port@2                endpoint            	Z   k           t                        i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "               {                                    e          ;      	  main dma                         +          	  disabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s              0                	              e      hdmi-phy@11d5f000             mediatek,mt8195-hdmi-phy                                       P                           pll_ref 26m pll1 pll2           2hdmi_txpll          	            
            A   
        P           okay            default            l                 i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "                {                                    m           ;      	  main dma                         +            okay            8            n        default       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                          "                {                                    m          ;      	  main dma                         +            okay            8            o        default    touchscreen@5d            goodix,gt9271              ]        /                 b                  l                  x   p        default            q         i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "               {                                    m          ;      	  main dma                         +            okay            8            r        default    typec-mux@48              ite,it5205             H           s                          okay       port       endpoint            	Z   t           k               i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              0            "               {                                    m          ;      	  main dma                         +          	  disabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              @            "                {                                    m          ;      	  main dma                         +          	  disabled          clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w              P                	              m      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                   3           okay       usb-phy@0                                           ref da_ref          
              Z      usb-phy@700                                           ref da_ref             u   v   w        intr rx_imp tx_imp          
                       [         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0                                           ref da_ref          
              J      usb-phy@700                                           ref da_ref             x   y   z        intr rx_imp tx_imp          
              K         phy@11e80000              mediatek,mt8195-pcie-phy                                 sif            {   |   }   ~               G  glb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1             3           
            okay               _      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy                                            
  unipro mp           
          	  disabled               Y      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm                        @                      0  {                                               wjob mmu gpu                  (     3   
   3      3      3      3           core0 core1 core2 core3 core4           okay                     clock-controller@13fbf000             mediatek,mt8195-mfgcfg                              	                    syscon@14000000           mediatek,mt8195-vppsys0 syscon                                	                                    "      dma-controller@14001000           mediatek,mt8195-mdp3-rdma                                                                   #              3           0                 "         <                                                       7         display@14002000              mediatek,mt8195-mdp3-fg                                                        "          display@14003000              mediatek,mt8195-mdp3-stitch              0                         0               "         display@14004000              mediatek,mt8195-mdp3-hdr                 @                         @               "   "      display@14005000              mediatek,mt8195-mdp3-aal                 P                {      F                        P               "   
           3         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                         `                %           "         display@14007000              mediatek,mt8195-mdp3-tdshp               p                         p               "   #      display@14008000              mediatek,mt8195-mdp3-color                               {      I                                       "   $           3         display@14009000              mediatek,mt8195-mdp3-ovl                                 {      J                                       "   %           3           0            display@1400a000              mediatek,mt8195-mdp3-padding                                                         "              3         display@1400b000              mediatek,mt8195-mdp3-tcc                                                         "         dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot                                                       +           "           0                 3           7         mutex@1400f000            mediatek,mt8195-vpp-mutex                                {      P                                       "              3         smi@14010000              mediatek,mt8195-smi-sub-common                                  "      "      "           apb smi gals0           B              3                    smi@14011000              mediatek,mt8195-smi-sub-common                                 "      "      "           apb smi gals0           B              3                    smi@14012000              mediatek,mt8195-smi-common-vpp                                   "      "      "      "           apb smi gals0 gals1            3                    larb@14013000             mediatek,mt8195-smi-larb                0                O           B              "      "           apb smi            3                    iommu@14018000            mediatek,mt8195-iommu-vpp                             8  `                                                  {      R                  "           bclk            v              3                    clock-controller@14e00000             mediatek,mt8195-wpesys                               	              %      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0                              	         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1             0                	         larb@14e04000             mediatek,mt8195-smi-larb                @                O           B              %      %           apb smi            3                    larb@14e05000             mediatek,mt8195-smi-larb                P                O           B              %      %      "           apb smi gals               3                    syscon@14f00000           mediatek,mt8195-vppsys1 syscon                               	                 	                  $      mutex@14f01000            mediatek,mt8195-vpp-mutex                               {      {                     	                 $   '           3         larb@14f02000             mediatek,mt8195-smi-larb                                 O           B              $      $      "           apb smi gals               3                    larb@14f03000             mediatek,mt8195-smi-larb                0                O           B              $      $      "           apb smi gals               3                    display@14f06000              mediatek,mt8195-mdp3-split              `                      	  `               $      $   +   $   ,           3         display@14f07000              mediatek,mt8195-mdp3-tcc                p                      	  p               $         dma-controller@14f08000           mediatek,mt8195-mdp3-rdma                                     	                             $           0                 3           7         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma                                     	                             $   
        0                 3           7         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma                                     	                             $           0                 3           7         display@14f0b000              mediatek,mt8195-mdp3-fg                                   	                 $   	      display@14f0c000              mediatek,mt8195-mdp3-fg                                   	                 $         display@14f0d000              mediatek,mt8195-mdp3-fg                                   	                 $         display@14f0e000              mediatek,mt8195-mdp3-hdr                                      	                 $         display@14f0f000              mediatek,mt8195-mdp3-hdr                                      	                 $         display@14f10000              mediatek,mt8195-mdp3-hdr                                       
                  $          display@14f11000              mediatek,mt8195-mdp3-aal                                {      i                     
                 $              3         display@14f12000              mediatek,mt8195-mdp3-aal                                 {      j                     
                  $              3         display@14f13000              mediatek,mt8195-mdp3-aal                0                {      k                     
  0               $   !           3         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               @                      
  @                           $         display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               P                      
  P                           $   $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               `                      
  `                           $   %      display@14f17000              mediatek,mt8195-mdp3-tdshp              p                      
  p               $         display@14f18000              mediatek,mt8195-mdp3-tdshp                                    
                 $   (      display@14f19000              mediatek,mt8195-mdp3-tdshp                                    
                 $   )      display@14f1a000              mediatek,mt8195-mdp3-merge                                    
                 $              3         display@14f1b000              mediatek,mt8195-mdp3-merge                                    
                 $              3         display@14f1c000              mediatek,mt8195-mdp3-color                              {      t                     
                 $              3         display@14f1d000              mediatek,mt8195-mdp3-color                                    
              {      u                  $              3         display@14f1e000              mediatek,mt8195-mdp3-color                              {      v                     
                 $              3         display@14f1f000              mediatek,mt8195-mdp3-ovl                                {      w                     
                 $               3           0            display@14f20000              mediatek,mt8195-mdp3-padding                                                         $              3         display@14f21000              mediatek,mt8195-mdp3-padding                                                       $              3         display@14f22000              mediatek,mt8195-mdp3-padding                                                         $              3         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             0                        0                           $           0                 3           7         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             @                        @                           $           0                 3           7         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             P                        P                           $           0                 3           7         clock-controller@15000000             mediatek,mt8195-imgsys                                	              ,      larb@15001000             mediatek,mt8195-smi-larb                                 O   	        B              ,       ,       ,   
        apb smi gals               3                    smi@15002000              mediatek,mt8195-smi-sub-common                                   ,      ,      "           apb smi gals0           B              3                    smi@15003000              mediatek,mt8195-smi-sub-common               0                   ,       ,       ,   
        apb smi gals0           B              3                    clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top                              	                    larb@15120000             mediatek,mt8195-smi-larb                                 O   
        B              ,                  apb smi            3                    clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr                               	         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe             "                 	                    larb@15230000             mediatek,mt8195-smi-larb                #                 O           B              ,                  apb smi            3                    clock-controller@15330000             mediatek,mt8195-ipesys              3                 	              -      larb@15340000             mediatek,mt8195-smi-larb                4                 O           B              -      -           apb smi            3                    clock-controller@16000000             mediatek,mt8195-camsys                                	              .      larb@16001000             mediatek,mt8195-smi-larb                                 O           B              .       .       .           apb smi gals               3                    larb@16002000             mediatek,mt8195-smi-larb                                  O           B              .      .           apb smi            3                    smi@16004000              mediatek,mt8195-smi-sub-common               @                   .       .       .           apb smi gals0           B              3                    smi@16005000              mediatek,mt8195-smi-sub-common               P                   .      .      "           apb smi gals0           B              3                    larb@16012000             mediatek,mt8195-smi-larb                                 O           B                                 apb smi            3                     larb@16013000             mediatek,mt8195-smi-larb                0                O           B                                 apb smi            3                     larb@16014000             mediatek,mt8195-smi-larb                @                O           B                                 apb smi            3   !                 larb@16015000             mediatek,mt8195-smi-larb                P                O           B                                 apb smi            3   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa                             	                    clock-controller@1606f000             mediatek,mt8195-camsys_yuva                             	                    clock-controller@1608f000             mediatek,mt8195-camsys_rawb                             	                    clock-controller@160af000             mediatek,mt8195-camsys_yuvb             
                	                    clock-controller@16140000             mediatek,mt8195-camsys_mraw                              	                    larb@16141000             mediatek,mt8195-smi-larb                                O           B              .              .           apb smi gals               3   "                 larb@16142000             mediatek,mt8195-smi-larb                                 O           B                                 apb smi            3   "                 clock-controller@17200000             mediatek,mt8195-ccusys                                	                    larb@17201000             mediatek,mt8195-smi-larb                                 O           B                                 apb smi            3                    video-codec@18000000              mediatek,mt8195-vcodec-dec          #           0                          +                               @                                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc                                0                         A   &      &                 sel vdec lat top                  A                         3         video-codec@10000             mediatek,mtk-vcodec-lat                               {                   0  0                                              A   &      &                 sel vdec lat top                  A                         3         video-codec@25000             mediatek,mtk-vcodec-core                 P                {                   P  0                                                                 A   '      '                 sel vdec lat top                  A                         3            larb@1800d000             mediatek,mt8195-smi-larb                                 O           B              &       &            apb smi            3                    larb@1800e000             mediatek,mt8195-smi-larb                                 O           B              "      &            apb smi            3                    clock-controller@1800f000             mediatek,mt8195-vdecsys_soc                              	              &      larb@1802e000             mediatek,mt8195-smi-larb                                O           B              '       '            apb smi            3                    clock-controller@1802f000             mediatek,mt8195-vdecsys                             	              '      larb@1803e000             mediatek,mt8195-smi-larb                                O           B              "      (            apb smi            3                    clock-controller@1803f000             mediatek,mt8195-vdecsys_core1                               	              (      clock-controller@190f3000             mediatek,mt8195-apusys_pll              0                	         clock-controller@1a000000             mediatek,mt8195-vencsys                               	              )      larb@1a010000             mediatek,mt8195-smi-larb                                 O           B              )      )           apb smi            3                    video-codec@1a020000              mediatek,mt8195-vcodec-enc                             H  0     `     a     b     c     d     v     w     x     y        {      U               #              )         	  venc_sel                  @                         3                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec             3         0  0     m     n     r     s     t     u                     +         0                                              jpgdec@0,0            mediatek,mt8195-jpgdec-hw                                0  0     m     n     r     s     t     u        {      W                  )           jpgdec             3         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw                               0  0     m     n     r     s     t     u        {      X                  )           jpgdec             3         jpgdec@1,0            mediatek,mt8195-jpgdec-hw                               0  0                                      {      \                  *           jpgdec             3            clock-controller@1b000000             mediatek,mt8195-vencsys_core1                                 	              *      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon                                                  	                                  #   port                         +       endpoint@0                      	Z                          jpeg-encoder@1a030000             mediatek,mt8195-jpgenc             3            0                                         +         0                                              jpgenc@0,0            mediatek,mt8195-jpgenc-hw                                   0     g     h     i     l        {      V                  )           jpgenc             3         jpgenc@1,0            mediatek,mt8195-jpgenc-hw                                  0                            {      [                  *           jpgenc             3            larb@1b010000             mediatek,mt8195-smi-larb                                 O           B              *      *      "            apb smi gals               3                    ovl@1c000000              mediatek,mt8195-disp-ovl                                  {      |                  3              #            0                              ports                        +       port@0                 endpoint            	Z                       port@1                endpoint            	Z                             rdma@1c002000             mediatek,mt8195-disp-rdma                                 {      ~                  3              #           0                               ports                        +       port@0                 endpoint            	Z                       port@1                endpoint            	Z                             color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color                0                {                        3              #                   0       ports                        +       port@0                 endpoint            	Z                       port@1                endpoint            	Z                             ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr                @                {                        3              #                   @       ports                        +       port@0                 endpoint            	Z                       port@1                endpoint            	Z                             aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal                P                {                        3              #                   P       ports                        +       port@0                 endpoint            	Z                       port@1                endpoint            	Z                             gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma                `                {                        3              #                   `       ports                        +       port@0                 endpoint            	Z                       port@1                endpoint            	Z                             dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither              p                {                        3              #   	                p       ports                        +       port@0                 endpoint            	Z                       port@1                endpoint            	Z                             dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                              {                        3              #      #   *           engine digital hs           	           
vdphy            okay                         +       panel@0       #    startek,kd070fhfid078 himax,hx8279                      o           y      0            l      l                       ]           default               port       endpoint            	Z                          ports                        +       port@0                 endpoint            	Z                       port@1                endpoint            	Z                             dsc@1c009000              mediatek,mt8195-disp-dsc                                 {                        3              #                             dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                              {                        3              #      #   +           engine digital hs           	           
vdphy          	  disabled          merge@1c014000            mediatek,mt8195-disp-merge              @                {                        3              #                   @          dp-intf@1c015000              mediatek,mt8195-dp-intf             P                {                        3              #   ,   #                 pixel engine pll          	  disabled          mutex@1c016000            mediatek,mt8195-disp-mutex              `                {                        3              #                   `              U      larb@1c018000             mediatek,mt8195-smi-larb                                O            B              #   (   #   (   "           apb smi gals               3                    larb@1c019000             mediatek,mt8195-smi-larb                                O           B              #   (   "       "           apb smi gals               3                    syscon@1c100000           mediatek,mt8195-vdosys1 syscon                                                                     	                         +   port                         +       endpoint@1                     	Z                          smi@1c01b000              mediatek,mt8195-smi-common-vdo                                  #   %   #   &   #   )   #   $        apb smi gals0 gals1            3                    iommu@1c01f000            mediatek,mt8195-iommu-vdo                             8  `                                                  {                     v              #   '        bclk               3                    mutex@1c101000            mediatek,mt8195-disp-mutex                              {                        3              +                                       larb@1c102000             mediatek,mt8195-smi-larb                                 O           B              +       +       +           apb smi gals               3                    larb@1c103000             mediatek,mt8195-smi-larb                0                O           B              +      +      "            apb smi gals               3                    dma-controller@1c104000           mediatek,mt8195-vdo1-rdma               @                {                        +              3           0      @                @            7         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma               P                {                        +              3           0      `                P            7         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma               `                {                        +              3           0      A                `            7         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma               p                {                        +              3           0      a                p            7         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma                               {                        +              3           0      B                            7         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma                               {                        +              3           0      b                            7         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma                               {                        +              3           0      C                            7         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma                               {                        +              3           0      c                            7         vpp-merge@1c10c000            mediatek,mt8195-disp-merge                              {                        +   	   +           merge merge_async              3                                           +         vpp-merge@1c10d000            mediatek,mt8195-disp-merge                              {                        +   
   +           merge merge_async              3                                           +         vpp-merge@1c10e000            mediatek,mt8195-disp-merge                              {                        +      +           merge merge_async              3                                           +         vpp-merge@1c10f000            mediatek,mt8195-disp-merge                              {                        +      +           merge merge_async              3                                           +         vpp-merge@1c110000            mediatek,mt8195-disp-merge                               {                        +      +           merge merge_async              3                                            +      ports                        +       port@0                       +                   endpoint@1                     	Z                       port@1                       +                  endpoint@1                     	Z                             dpi@1c112000              mediatek,mt8195-dpi                                 +   -   +      +   2        pixel engine pll            {                         3              +           okay       ports                        +       port@0                 endpoint            	Z                       port@1                endpoint            	Z                             dp-intf@1c113000              mediatek,mt8195-dp-intf             0                {                        3              +   /   +                 pixel engine pll          	  disabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p      @            P            p                                                              4  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p          @            P            p                                                          h     +   %   +       +   #   +   !   +   $   +   "   +   1   +   &   +   '   +   (   +   )   +   *              mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top             3           0      d      e        {                   (     +   3   +   4   +   5   +   6   +   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async       ports                        +       port@0                       +                   endpoint@1                     	Z                       port@1                       +                  endpoint@1                     	Z                             hdmi-tx@1c300000              mediatek,mt8195-hdmi-tx                        0                        Q      L      M   $   ,        bus hdcp hdcp24m hdmi-split               L                      {                        3           	           
vhdmi            okay            default                          i2c           mediatek,mt8195-hdmi-ddc                                ports                        +       port@0                 endpoint            	Z                       port@1                endpoint            	Z                             edp-tx@1c500000           mediatek,mt8195-edp-tx              P                            dp_calibration_data            3           {                             	  disabled          dp-tx@1c600000            mediatek,mt8195-dp-tx               `                            dp_calibration_data            3           {                             	  disabled             thermal-zones      cpu0-thermal                                          trips      trip-alert           L                  passive                  trip-crit                            	  critical             cooling-maps       map0                     0                          cpu1-thermal                                          trips      trip-alert           L                  passive                  trip-crit                            	  critical             cooling-maps       map0                     0                          cpu2-thermal                                          trips      trip-alert           L                  passive                  trip-crit                            	  critical             cooling-maps       map0                     0                          cpu3-thermal                                          trips      trip-alert           L                  passive                  trip-crit                            	  critical             cooling-maps       map0                     0                          cpu4-thermal                                           trips      trip-alert           L                  passive                  trip-crit                            	  critical             cooling-maps       map0                     0                          cpu5-thermal                                          trips      trip-alert           L                  passive                  trip-crit                            	  critical             cooling-maps       map0                     0                          cpu6-thermal                                          trips      trip-alert           L                  passive                  trip-crit                            	  critical             cooling-maps       map0                     0                          cpu7-thermal                                          trips      trip-alert           L                  passive                  trip-crit                            	  critical             cooling-maps       map0                     0                          vpu0-thermal                                          trips      trip-alert           L                  passive       trip-crit                            	  critical                vpu1-thermal                                       	   trips      trip-alert           L                  passive       trip-crit                            	  critical                gpu-thermal                                    
   trips      trip-alert           L                  passive       trip-crit                            	  critical                gpu1-thermal                                          trips      trip-alert           L                  passive       trip-crit                            	  critical                vdec-thermal                                          trips      trip-alert           L                  passive       trip-crit                            	  critical                img-thermal                                       trips      trip-alert           L                  passive       trip-crit                            	  critical                infra-thermal                                         trips      trip-alert           L                  passive       trip-crit                            	  critical                cam0-thermal                                          trips      trip-alert           L                  passive       trip-crit                            	  critical                cam1-thermal                                          trips      trip-alert           L                  passive       trip-crit                            	  critical                   chosen          .serial0:921600n8          connector             hdmi-connector          
hdmi            a           :           F      port       endpoint            	Z                          firmware       optee             linaro,optee-tz         smc          memory@40000000         memory              @                reserved-memory                      +               optee@43200000           V            C                memory@50000000           shared-dma-pool             P                  V           1      memory@53000000           shared-dma-pool             S       @        memory@54600000          V            T`                memory@60000000           shared-dma-pool             `                   V           7      memory@60f00000           shared-dma-pool             `                  V           9      memory@61000000           shared-dma-pool             a                   V           6      memory@62000000           shared-dma-pool             b       @           backlight-lcm0            pwm-backlight           ]              o  @                                            backlight-lcd1            pwm-backlight                            y      .            ]                        o  @      	  disabled          can-clk           fixed-clock         	            81-         2can-clk            A      regulator-0           regulator-fixed         edp_panel_3v3            2Z         2Z                                   default                  regulator-1           regulator-fixed         edp_backlight_12v                                              `            default                  gpio-keys         
    gpio-keys      button-volume-up             h           d        E      j         
  
volume_up              s         regulator-vio18-lcm0              regulator-fixed         vio18_lcm0                         /            default                                        regulator-vsys-lcm0           regulator-fixed       
  vsys_lcm0                                p                 regulator-2           regulator-fixed       	  wifi_3v3             2Z         2Z                                             	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dpi1 gce0 gce1 hdmi0 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 ethernet0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform pinctrl-names pinctrl-0 audio-routing mediatek,adsp link-name sound-dai #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux output-high drive-strength input-enable input-disable bias-disable bias-pull-up bias-pull-down drive-strength-microamp output-low #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells mediatek,mic-type-0 mediatek,mic-type-1 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes mediatek,long-press-mode power-off-time-sec linux,keycodes wakeup-source #iommu-cells #mbox-cells memory-region firmware-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select cs-gpios spi-max-frequency vdd-supply xceiver-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle snps,reset-gpio snps,reset-delays-us mediatek,tx-delay-ps mediatek,mac-wol pinctrl-1 snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys mediatek,syscon-wakeup dr_mode usb-role-switch vusb33-supply remote-endpoint bus-width cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc freq-table-hz mediatek,ufs-disable-mcq bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN3-supply label data-role op-sink-microwatt power-role try-power-role source-pdos sink-pdos pd-revision svid vdo mediatek,ibias mediatek,ibias_up irq-gpios reset-gpios AVDD28-supply vcc-supply mode-switch orientation-switch mediatek,force-mode operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs backlight enable-gpios iovcc-supply mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path ddc-i2c-bus hdmi-pwr-supply no-map brightness-levels default-brightness-level num-interpolated-steps pwms enable-active-high debounce-interval linux,code vin-supply regulator-boot-on 