 U   8 G,   (            W F                             4    mediatek,mt8390-evk mediatek,mt8390 mediatek,mt8188                                  +            7MediaTek Genio-700 EVK     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dpi@1c112000            T/soc/dsc@1c009000            Y/soc/ethdr@1c114000          `/soc/mailbox@10320000            e/soc/mailbox@10330000            j/soc/merge0@1c014000             q/soc/merge@1c10c000          x/soc/merge@1c10d000          /soc/merge@1c10e000          /soc/merge@1c10f000          /soc/merge@1c110000          /soc/mutex@1c016000          /soc/mutex@1c101000          /soc/padding@1c11d000            /soc/padding@1c11e000            /soc/padding@1c11f000            /soc/padding@1c120000            /soc/padding@1c121000            /soc/padding@1c122000            /soc/padding@1c123000            /soc/padding@1c124000            /soc/rdma@1c104000           /soc/rdma@1c105000           /soc/rdma@1c106000          /soc/rdma@1c107000          /soc/rdma@1c108000          !/soc/rdma@1c109000          ,/soc/rdma@1c10a000          7/soc/rdma@1c10b000          B/soc/dsi@1c008000           G/soc/ethernet@11021000          Q/soc/i2c@11280000           V/soc/i2c@11e00000           [/soc/i2c@11281000           `/soc/i2c@11282000           e/soc/i2c@11e01000           j/soc/i2c@11ec0000           o/soc/i2c@11ec1000           t/soc/mmc@11230000           y/soc/mmc@11240000           ~/soc/serial@11001100          cpus                         +       cpu@0           cpu           arm,cortex-a55                      psci            w5                                               @                                 @        "           /           @               T           c   	      cpu@100         cpu           arm,cortex-a55                     psci            w5                                               @                                 @        "           /           @               T           c   
      cpu@200         cpu           arm,cortex-a55                     psci            w5                                               @                                 @        "           /           @               T           c         cpu@300         cpu           arm,cortex-a55                     psci            w5                                               @                                 @        "           /           @               T           c         cpu@400         cpu           arm,cortex-a55                     psci            w5                                               @                                 @        "           /           @               T           c         cpu@500         cpu           arm,cortex-a55                     psci            w5                                               @                                 @        "           /           @               T           c         cpu@600         cpu           arm,cortex-a78                     psci                                                            @                                 @        "           /           @              T           c         cpu@700         cpu           arm,cortex-a78                     psci                                                            @                                 @        "           /           @              T           c         cpu-map    cluster0       core0           k   	      core1           k   
      core2           k         core3           k         core4           k         core5           k         core6           k         core7           k               idle-states         opsci       cpu-off-l             arm,idle-state          |                       2           _          D        c         cpu-off-b             arm,idle-state          |                       -                             c         cluster-off-l             arm,idle-state          |                     7                     H        c         cluster-off-b             arm,idle-state          |                     2                             c            l2-cache0             cache                                    @                   /                    c         l2-cache1             cache                                    @                   /                    c         l3-cache              cache                                     @                            c            oscillator-13m            fixed-clock                      ]@        clk13m          c   :      oscillator-26m            fixed-clock                             clk26m          c   <      oscillator-32k            fixed-clock                                clk32k        opp-table-gpu             operating-points-v2                  c      opp-390000000               >        "         0         opp-431000000                       "         0         opp-473000000               1h@        " 	'        0         opp-515000000               F        " 	X        0         opp-556000000               !#         " 	h        0         opp-598000000               #        " 	<        0         opp-640000000               &%         " 	        0         opp-670000000               'c        " 
        0         opp-700000000               )'         " 
L        0         opp-730000000               +        " 
}        0         opp-760000000               -L         " 
`        0         opp-790000000               /q        " 
4        0         opp-835000000               1        " (r        0         opp-880000000               4s         " q        0         opp-915000000               6        " X        0         opp-915000000-5             6        "         0   0      opp-915000000-6             6        " q        0   p      opp-950000000               8ـ        " 5         0         opp-950000000-5             8ـ        " X        0   0      opp-950000000-6             8ـ        " q        0   p         pmu-a55           arm,cortex-a55-pmu                      A                  pmu-a78           arm,cortex-a78-pmu                      A                  psci              arm,psci-1.0            smc       sound           L           ^okay          6    mediatek,mt8390-mt6359-evk mediatek,mt8188-mt6359-evb            7mt8390-evk          edefault         s         t  }Headphone Headphone L Headphone Headphone R DMIC_INPUT AP DMIC AP DMIC AUDGLB AP DMIC MIC_BIAS_0 AP DMIC MIC_BIAS_2               dai-link-0        
  DL_SRC_BE      codec                           dai-link-1          DMIC_BE    codec                       dai-link-2          ETDM3_OUT_BE       codec                              thermal-zones      cpu-little0-thermal                                        trips      trip-alert0          L                  passive         c         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                     H     	   
                        cpu-little1-thermal                                       trips      trip-alert0          L                  passive         c         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                     H     	   
                        cpu-little2-thermal                                       trips      trip-alert0          L                  passive         c         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                     H     	   
                        cpu-little3-thermal                                       trips      trip-alert0          L                  passive         c         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                     H     	   
                        cpu-big0-thermal                         d                 trips      trip-alert0          L                  passive         c         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                                         cpu-big1-thermal                         d                 trips      trip-alert0          L                  passive         c          trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                                          apu-thermal                                 !       trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                gpu-thermal                                 !      trips      trip-alert0          L                  passive         c   "      trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0               "           #            gpu1-thermal                                    !      trips      trip-alert0          L                  passive         c   $      trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0               $           #            adsp-thermal                                    !      trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                vdo-thermal                                 !      trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                infra-thermal                                   !      trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                cam1-thermal                                    !      trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                cam2-thermal                                    !      trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                   timer             arm,armv8-timer                   @  A                                             
                ]@      soc                      +             simple-bus                                             performance-controller@11bc10             mediatek,cpufreq-hw                           0                          c         interrupt-controller@c000000              arm,gic-v3          1           B                        Y                                             A      	               c      ppi-partitions     interrupt-partition-0           n   	   
                    c         interrupt-partition-1           n              c               syscon@10000000            mediatek,mt8188-topckgen syscon                                          c   (      syscon@10001000       #    mediatek,mt8188-infracfg-ao syscon                                          w           c   )      syscon@10003000           mediatek,mt8188-pericfg syscon               0                           c   L      pinctrl@10005000              mediatek,mt8188-pinctrl       `       P                                                                               0  iocfg0 iocfg_rm iocfg_lt iocfg_lm iocfg_rt eint                                %                    Y        A                      1           c   %   audio-default-pins          c      pins-cmd-dat          X    e  f  g  h  i  j  k  l  m  n  r  s  t  u  v  y  z  |  }  ~             disp-pwm1-pins          c   H   pins-pwm                       dptx-pins      pins-cmd-dat              .                  edp-panel-3v3-en-pins           c      pins1                                eth-default-pins            c   X   pins-cc                                  pins-mdio                                         pins-power                               pins-rxd                                     pins-txd                                        eth-sleep-pins          c   Y   pins-cc                           pins-mdio                                          pins-rxd                              pins-txd                                 hdmi-vreg-pins          c   t   pins-pwr              2                   hdmi-pins           c      pins-hotplug              3               pins-cec              4                pins-ddc              5  6           
         i2c0-pins           c   c   pins              8  7                              i2c1-pins           c   v   pins              :  9                              i2c2-pins           c   g   pins              <  ;                              i2c3-pins           c   h   pins              >  =                              i2c4-pins           c   y   pins              @  ?                              i2c5-pins           c      pins              B  A                              i2c6-pins           c      pins              D  C                              gpio-key-pins      pins              *  +  ,         mmc0-default-pins           c   Z   pins-clk                                    f      pins-cmd-dat          $                                                   e      pins-rst                                    e         mmc0-uhs-pins           c   [   pins-clk                                    f      pins-cmd-dat          $                                                   e      pins-ds                                 f      pins-rst                                    e         mmc1-default-pins           c   ^   pins-clk                                    f      pins-cmd-dat                                                     e      pins-insert                              mmc1-uhs-pins           c   _   pins-clk                                    f      pins-cmd-dat                                                     e         mmc2-default-pins      pins-clk                                    f      pins-cmd-dat                                                     e      pins-pcm              {         mmc2-uhs-pins      pins-clk                                    f      pins-cmd-dat                                                     e         mmc2-eint-pins     pins-dat1                                  e         mmc2-dat1-pins     pins-dat1                                            e         dsi0-vreg-en-pins           c      pins-pwr-en           o          4         panel-default-pins          c      pins-rst                        4      pins-en           -          4         pcie-default-pins           c   s   pins              /  0  1                  rt1715-int-pins    pins_cmd0_dat                                         spi0-pins      pins-spi              E  F  G  H                   spi1-pins      pins-spi              K  L  M  N                   spi2-pins           c   I   pins-spi              O  P  Q  R                   touch-avdd-pins         c      pins-power            x                   touch-pins          c   f   pins-irq                                        pins-reset                               tcpci-int-pins          c   z   pins-int-n                                        uart0-pins          c   D   pins                                   uart1-pins          c   E   pins              !  "                  uart2-pins          c   F   pins              #  $                  usb-default-pins            c   n   pins-iddig            S                         pins-valid            U               pins-vbus             T                  usb1-default-pins           c   N   pins-valid            X               pins-usb-hub-3v3-en           p                   usb2-default-pins           c   j   pins-iddig            Y                            wifi-pwrseq-pins       pins-wifi-enable                        4            syscon@10006000       )    mediatek,mt8188-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8188-power-controller                         +            ?           c   =   power-domain@0                                   +            ?           S   &   power-domain@1                     a   '      (           hmfg alt         t   )                     +            ?           S   *   power-domain@2                     ?          power-domain@3                     ?          power-domain@4                     ?                power-domain@15                    a   (      (      (      (   
   (   3   (   4   (   =   (      (      +      +      +      +      +      +      +      +      +      +      +      +      +      +      +      +      +      +      +            htop cam ccu img venc vdec wpe cfgck cfgxo ss-sram-cmn ss-sram-v0l0 ss-sram-v0l1 ss-sram-ve0 ss-sram-ve1 ss-sram-ifa ss-sram-cam ss-sram-v1l5 ss-sram-v1l6 ss-sram-rdr ss-iommu ss-imgcam ss-emi ss-subcmn-rdr ss-rsi ss-cmn-l4 ss-vdec1 ss-wpe ss-cvdo-ve1          t   )                     +            ?      power-domain@16                  H  a   (      (      ,      ,      ,      ,      ,      ,      ,         A  hcfgck cfgxo ss-gals ss-cmn ss-emi ss-iommu ss-larb ss-rsi ss-bus            t   )                     +            ?      power-domain@20                  0  a   (      (      -      -      -      -         8  hcfgck cfgxo ss-vpp1-g5 ss-vpp1-g6 ss-vpp1-l5 ss-vpp1-l6         t   )        ?          power-domain@22                    a   .            hss-vdec1-soc-l1         t   )                     +            ?      power-domain@23                    a   /            hss-vdec2-l1         t   )        ?             power-domain@29                     a   (      (      (   	   (           hcam ccu bus cfgck           t   )                     +            ?      power-domain@30                  (  a   0       0      0      0      0         6  hss-cam-l13 ss-cam-l14 ss-cam-mm0 ss-cam-mm1 ss-camsys           t   )                     +            ?      power-domain@32                     a   0      1       2          $  hss-camb-sub ss-camb-raw ss-camb-yuv         ?          power-domain@31                    a   0      3       4          $  hss-cama-sub ss-cama-raw ss-cama-yuv         ?                power-domain@17                  (  a   (      (      5       5      5         &  hcfgck cfgxo ss-larb2 ss-larb3 ss-gals           t   )                     +            ?      power-domain@9             	        a   (   @   (   ?      	  hbus hdcp            t   )        ?          power-domain@18                    t   )        ?          power-domain@19                    t   )        ?             power-domain@24                     a   6       6      6      6         0  hss-ve1-larb ss-ve1-core ss-ve1-gals ss-ve1-sram         t   )        ?          power-domain@21                    a   7      7           hss-wpe-l7 ss-wpe-l7pce          t   )        ?                power-domain@5                     t   )        a   8           hss-pextp-fmem           ?          power-domain@7                     a   (   0   (   1        hseninf0 seninf1         ?          power-domain@6                     ?          power-domain@10            
        a   (   E   (   D      	  hbus main            t   )                     +            ?      power-domain@11                    t   )                     +            ?      power-domain@14                    a   (   F        hasm         t   )        ?          power-domain@13                    a   (   S   (      9            ha1sys intbus adspck         t   )        ?          power-domain@12                    t   )        ?                power-domain@8                     a   8         	  hethermac            t   )        ?                watchdog@10007000             mediatek,mt8188-wdt              p                         w           c   >      syscon@1000c000       "    mediatek,mt8188-apmixedsys syscon                                           c   '      timer@10017000        ,    mediatek,mt8188-timer mediatek,mt6765-timer             p                A      	               a   :      pwrap@10024000        3    mediatek,mt8188-pwrap mediatek,mt8195-pwrap syscon              @                pwrap           A                      a   )      )          	  hspi wrap       pmic              mediatek,mt6359          Y        1                          %        A              c      adc           mediatek,mt6359-auxadc                   audio-codec           mediatek,mt6359-codec                               regulators            mediatek,mt6359-regulator      buck_vs1            vs1          5          !        (             D      buck_vgpu11       
  dvdd_core                     7        X          (           m                   D      buck_vmodem         vmodem                            X  *        (         buck_vpu          
  dvdd_adsp                     7        X          (           m                   D      buck_vcore          dvdd_proc_l                            X          (           m                   D      buck_vs2            vs2          5          j         (             D      buck_vpa            vpa_pmu                    /M`        (  ,        c   `      buck_vproc2         vgpu             dp         5         X  L        (           m                     *          j        c   &      buck_vproc1         vproc1                    7        X  L        (           m                buck_vcore_sshub            vcore_sshub                   7      buck_vgpu11_sshub           vgpu11_sshub                      7      ldo_vaud18          vaud18           w@         w@        (         ldo_vsim1         
  vsim1_pmu                     /M`        (          c   a      ldo_vibr            vibr             O         2Z      ldo_vrf12           va12_abb2_pmu                               D      ldo_vusb            vusb             -         -        (           D        c   M      ldo_vsram_proc2         vsram_proc2                            X  L        (            D      ldo_vio18           vio18                             (           D        c   e      ldo_vcamio          vcamio                          ldo_vcn18         
  vcn18_pmu            w@         w@        (            D      ldo_vfe28           vfe28            *         *        (   x      ldo_vcn13           vcn13                            ldo_vcn33_1_bt          vcn33_1_bt           *         5g        c   w      ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g      ldo_vaux18          vaux18           w@         w@        (            D      ldo_vsram_others          
  vsram_gpu            q         5         X          (              &          j        c   *      ldo_vefuse          vefuse                          ldo_vxo22           vxo22            w@         !         D      ldo_vrfck           vrfck            `               ldo_vrfck_1         vrfck                     j       ldo_vbif28          vbif28           *         *        (         ldo_vio28           vio28            *         2Z         D      ldo_vemc            vemc             ,@          2Z      ldo_vemc_1          vemc             &%         2Z        c   \      ldo_vcn33_2_bt          vcn33_2_pmu          *         5g         D      ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g      ldo_va12            va12             O                   D      ldo_va09            va09             5          O      ldo_vrf18           vrf18                     P      ldo_vsram_md          	  vsram_md                               X  *        (         ldo_vufs            vufs18_pmu                             D        c   ]      ldo_vm18            vm18                               D      ldo_vbbck           vbbck                     O         D      ldo_vsram_proc1         vsram_proc1                            X  L        (            D      ldo_vsim2           vsim2                     /M`      ldo_vsram_others_sshub          vsram_others_sshub                              rtc           mediatek,mt6358-rtc       keys              mediatek,mt6359-keys                              power-key              t               home               f               spmi@10027000         *    mediatek,mt8188-spmi mediatek,mt8195-spmi                p                            pmif spmimst               (   8           (           a   )      )       (   8      (  hpmif_sys_ck pmif_tmr_ck spmimst_clk_mux       iommu@10315000            mediatek,mt8188-iommu-infra             1P                A                     )           c   q      mailbox@10320000              mediatek,mt8188-gce             2        @         A                      6           a   )           c         mailbox@10330000              mediatek,mt8188-gce             3        @         A                      6           a   )           c         scp@10720000              mediatek,mt8188-scp-dual                r                 cfg                      +                   P             ^okay       scp@0             mediatek,scp-core                          sram            A                     ^okay            B   ;        c         scp@d0000             mediatek,scp-core                        sram            A                   	  ^disabled             audio-controller@10b10000             mediatek,mt8188-afe                                 (   S           (           a   <   '   	   '   
   (      (      (      (      (      (   S   (      (       (   E   (   Q   (   M   (   N   (   O   (   P   9       (      (      (      (   T   (   R        hclk26m apll1 apll2 apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 top_a1sys_hp top_aud_intbus top_audio_h top_audio_local_bus top_dptx top_i2so1 top_i2so2 top_i2si1 top_i2si2 adsp_audio_26m apll1_d4 apll2_d4 apll12_div4 top_a2sys top_aud_iec          A      6               P   =           ^   >         	  eaudiosys            t   )        q   (        ^okay            B   ?        c         adsp@10b80000             mediatek,mt8188-dsp       @                                                             cfg sram sec bus               (   D        a   (   D   (   E        haudiodsp adsp_bus              @   A        rx tx           P   =           ^okay            B   B   C        c         mailbox@10b86100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox             a                A                     6            c   @      mailbox@10b87100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox             q                A                     6            c   A      clock-controller@10b91100             mediatek,mt8188-adsp-audio26m                                          c   9      serial@11001100       *    mediatek,mt8188-uart mediatek,mt6577-uart                                A                      a   <   )         	  hbaud bus            ^okay            s   D        edefault       serial@11001200       *    mediatek,mt8188-uart mediatek,mt6577-uart                                A                      a   <   )         	  hbaud bus            ^okay            s   E        edefault       serial@11001300       *    mediatek,mt8188-uart mediatek,mt6577-uart                                A                      a   <   )         	  hbaud bus            ^okay            s   F        edefault       serial@11001400       *    mediatek,mt8188-uart mediatek,mt6577-uart                                A                     a   <   )         	  hbaud bus          	  ^disabled          adc@11002000          .    mediatek,mt8188-auxadc mediatek,mt8173-auxadc                                 a   )           hmain                     	  ^disabled          syscon@11003000       "    mediatek,mt8188-pericfg-ao syscon                0                           c   8      spi@1100a000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 A                      a   (   y   (      )           hparent-clk sel-clk spi-clk        	  ^disabled          thermal-sensor@1100b000           mediatek,mt8188-lvts-ap                              A                      a   )           ^   )              G        lvts-calib-data-1                      c   !      pwm@1100e000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm                                a   (   '   )   /        hmain mm         A                               	  ^disabled          pwm@1100f000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm                                a   (   (   )   F        hmain mm         A                                ^okay            edefault         s   H        c         spi@11010000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 A                      a   (   y   (      )   2        hparent-clk sel-clk spi-clk        	  ^disabled          spi@11012000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 A                      a   (   y   (      )   3        hparent-clk sel-clk spi-clk          ^okay            s   I        edefault                   spi@11013000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                0                A                      a   (   y   (      )   4        hparent-clk sel-clk spi-clk        	  ^disabled          spi@11018000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                A                      a   (   y   (      )   8        hparent-clk sel-clk spi-clk        	  ^disabled          spi@11019000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                A                      a   (   y   (      )   9        hparent-clk sel-clk spi-clk        	  ^disabled          usb@11201000          #    mediatek,mt8188-mtu3 mediatek,mtu3                       -     >              	  mac ippc                                 ?                      +           A                         (   )           (   v        a   8   	   (      8   
        hsys_ck ref_ck mcu_ck               J      K                       L  h           ^okay            otg                     M        s   N        edefault    usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 mac         A                         (   *           (   v        a   8   
        hsys_ck          ^okay               M                     +       hub@1             usb451,8025                    )   O        2   %               >   P        c   Q      hub@2             usb451,8027                    )   Q        2   %               >   P        c   O      port       endpoint            I   R        c   }            port       endpoint            I   S        c   |            ethernet@11021000         ;    mediatek,mt8188-gmac mediatek,mt8195-gmac snps,dwmac-5.10a                     @         A                     Ymacirq        0  a   8       8      (   A   (   B   (   C   8         .  haxi apb mac_main ptp_ref rmii_internal mac_cg              (   A   (   B   (   C           (      (      (           P   =           i   )        z   T           U           V                                          ^okay          	  rgmii-id               W        edefault sleep           s   X           Y                 	   %               	      '  '   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916                       c   W         stmmac-axi-config           	'                                 	1           	A           c   T      rx-queues-config            	Q            	g        c   U   queue0           	x        	          queue1           	x        	          queue2           	x        	          queue3           	x        	             tx-queues-config            	            	        c   V   queue0           	x        	            	         queue1           	x        	           	         queue2           	x        	           	         queue3           	x        	           	               mmc@11230000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              #                              	                          a   (      )      )      )   M      !  hsource hclk source_cg crypto_clk            ^okay            edefault state_uhs           s   Z           [        	           
          
         
#         
2         
A         
N         
_         
g        
m H        
|   \        
   ]         
      mmc@11240000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              $                              	                         a   (      )      )   $        hsource hclk source_cg              (              (           ^okay            edefault state_uhs           s   ^           _        	           
          
         
         
         
         
_        
   %              
|   `        
   a      mmc@11250000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              %                              	                         a   (      )      )   A        hsource hclk source_cg              (              (         	  ^disabled          thermal-sensor@11278000           mediatek,mt8188-lvts-mcu                '                A                      a   )           ^   )               G        lvts-calib-data-1                      c         i2c@11280000              mediatek,mt8188-i2c              (             "                A                      
           a   b       )   7      	  hmain dma                         +            ^okay            edefault         s   c            touchscreen@5d            goodix,gt9271              ]            %        	   %              
   %               2   %               
   d           e        edefault         s   f         i2c@11281000              mediatek,mt8188-i2c              (            "               A                      
           a   b      )   7      	  hmain dma                         +            ^okay            edefault         s   g               i2c@11282000              mediatek,mt8188-i2c              (             "               A                      
           a   b      )   7      	  hmain dma                         +            ^okay            edefault         s   h               clock-controller@11283000             mediatek,mt8188-imp-iic-wrap-c              (0                           c   b      usb@112a1000          #    mediatek,mt8188-mtu3 mediatek,mtu3               *       -    *>              	  mac ippc                        *        ?                      +           A                        (   -           (   v        a   8      (      8           hsys_ck ref_ck mcu_ck               i                       L  p           ^okay            otg         high-speed          host                        M        edefault         s   j   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 mac         A                        (   .           (   v        a   8           hsys_ck          ^okay               M        5   k      connector         %    gpio-usb-b-connector usb-b-connector            micro           A   %   Y           5   l         usb@112b1000          #    mediatek,mt8188-mtu3 mediatek,mtu3               +       -    +>              	  mac ippc                        +        ?                      +           A                        (   ,           (   v        a   8      (      8           hsys_ck ref_ck mcu_ck               m                       L  `           ^okay            otg         high-speed                      M        s   n        edefault    usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 mac         A                        (   +           (   v        a   8           hsys_ck          ^okay          connector         %    gpio-usb-b-connector usb-b-connector            micro           A   %   S            5   o         pcie@112f0000         *    mediatek,mt8188-pcie mediatek,mt8192-pcie               /                	  pcie-mac                                              J               pci         T                         +         0  a   )   L   )   #   )   &   )   +   )   C   8         /  hpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          1           A                   `  e                  p                      p                     p                     p           s                              q                             r         	  pcie-phy            P   =           ^   >           emac         ^okay            edefault         s   s   interrupt-controller                         1            Y        c   p         spi@1132c000          (    mediatek,mt8188-nor mediatek,mt8186-nor             2                a   (   X   8      8           hspi sf axi             (   X        A      9                            +          	  ^disabled          t-phy@11c20700        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                                            +           P   =           ^okay       pcie-phy@0                         a   (           href                    c   r         hdmi-phy@11d5f000         2    mediatek,mt8188-hdmi-phy mediatek,mt8195-hdmi-phy                               a   )           hpll_ref         hdmi_txpll                                     
                   ^okay            edefault         s   t        c         dsi-phy@11c80000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx                              a   <        mipi_tx0_pll                                    ^okay            c         dsi-phy@11c90000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx                              a   <        mipi_tx0_pll                                  	  ^disabled            c         i2c@11e00000              mediatek,mt8188-i2c                           "                A                      
           a   u       )   7      	  hmain dma                         +            ^okay            edefault         s   v            typec-mux@48              ite,it5205             H                             w   port       endpoint            I   x        c   ~               i2c@11e01000              mediatek,mt8188-i2c                          "               A                      
           a   u      )   7      	  hmain dma                         +            ^okay            edefault         s   y         B@   rt1715@4e             richtek,rt1715             N        	   %              edefault         s   z        5   {   connector             usb-c-connector         USB-C           dual                     !dual            ,sink            ;         G"        Q"   altmodes       displayport         ]          b G         ports                        +       port@0                 endpoint            I   |        c   S         port@1                endpoint            I   }        c   R         port@2                endpoint            I   ~        c   x                     clock-controller@11e02000             mediatek,mt8188-imp-iic-wrap-w                                          c   u      t-phy@11e30000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                ^okay       usb-phy@0                          a   (      '           href da_ref                     c   m         t-phy@11e40000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                ^okay       usb-phy@0                          a   (      '           href da_ref                     c   J      usb-phy@700                       a   '      <        href da_ref                     c   K         t-phy@11e80000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                ^okay       usb-phy@0                          a   (      '           href da_ref                     c   i         i2c@11ec0000              mediatek,mt8188-i2c                           "               A                      
           a          )   7      	  hmain dma                         +            ^okay            edefault         s                  i2c@11ec1000              mediatek,mt8188-i2c                          "                A                      
           a         )   7      	  hmain dma                         +            ^okay            edefault         s                  clock-controller@11ec2000              mediatek,mt8188-imp-iic-wrap-en                                         c         efuse@11f20000        ,    mediatek,mt8188-efuse mediatek,mt8186-efuse                                           +      dp-calib@1a0                         c         lvts1-calib@1ac              @        c   G      gpu-speedbin@581                         f               c         socinfo-data1@7a0                      socinfo-data2@7e0                         gpu@13000000          )    mediatek,mt8188-mali arm,mali-valhall-jm                         @         a             0  A                   ~             }               Yjob mmu gpu                  
  speed-bin           k           P   =      =      =           core0 core1 core2           T           ^okay               &        c   #      clock-controller@13fbf000             mediatek,mt8188-mfgcfg                                         c         syscon@14000000           mediatek,mt8188-vppsys0 syscon                                           c   +      dma-controller@14001000           mediatek,mt8188-mdp3-rdma                                           a   +         <                                                                     P   =                                                       display@14002000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                               a   +                                display@14004000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                @                a   +   "                 @          display@14005000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal                P                A      F               a   +   
        P   =                    P          display@14006000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                a   +                    `                %      display@14007000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                p                a   +   #                 p          display@14008000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                                A      I               a   +   $        P   =                              display@14009000          2    mediatek,mt8188-mdp3-ovl mediatek,mt8195-mdp3-ovl                                A      J               a   +   %        P   =                                            display@1400a000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                                a   +           P   =                              display@1400b000          2    mediatek,mt8188-mdp3-tcc mediatek,mt8195-mdp3-tcc                                a   +                              display@1400c000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot                                         a   +                         P   =                                    +      mutex@1400f000            mediatek,mt8188-vpp-mutex                                A      P               a   +           P   =                              smi@14012000              mediatek,mt8188-smi-common-vpp                               a   +      +           hapb smi         P   =           c         smi@14013000              mediatek,mt8188-smi-larb                0                a   +      +           hapb smi         P   =                                 c         iommu@14018000            mediatek,mt8188-iommu-vpp                      P         a   +           hbclk            A      R               P   =           )                                     c         dma-controller@14f09000           mediatek,mt8188-mdp3-rdma                                          a   -   
                      P   =                 	                        dma-controller@14f0a000           mediatek,mt8188-mdp3-rdma                                          a   -                         P   =                 	                        display@14f0c000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                             a   -                 	            display@14f0d000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                             a   -                 	            display@14f0f000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                               a   -   "              	            display@14f10000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                                a   -   $              
             display@14f12000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal                                A      j               a   -   #        P   =                 
             display@14f13000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal               0                A      k               a   -   %        P   =                 
  0          display@14f15000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz               P                a   -                 
  P                      display@14f16000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz               `                a   -                 
  `                      display@14f18000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                               a   -                 
            display@14f19000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                               a   -                 
            display@14f1a000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge                               a   -           P   =                 
            display@14f1b000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge                               a   -           P   =                 
            display@14f1d000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                               A      u               a   -           P   =                 
            display@14f1e000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                               A      v               a   -           P   =                 
            display@14f21000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                               a   -           P   =                             display@14f22000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                                a   -           P   =                              display@14f24000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot             @                           a   -                         P   =                   @                      display@14f25000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot             P                           a   -                         P   =                   P                      clock-controller@14e00000             mediatek,mt8188-wpesys                                          c   7      clock-controller@14e02000             mediatek,mt8188-wpesys-vpp0                                       smi@14e04000              mediatek,mt8188-smi-larb                @                a   7      7           hapb smi         P   =                                 c         syscon@14f00000           mediatek,mt8188-vppsys1 syscon                                          c   -      mutex@14f01000            mediatek,mt8188-vpp-mutex                               A      {               a   -   &        P   =                 	            smi@14f02000              mediatek,mt8188-smi-larb                                 a   -      -           hapb smi         P   =                                 c         smi@14f03000              mediatek,mt8188-smi-larb                0                a   -      -           hapb smi         P   =                                 c         clock-controller@15000000             mediatek,mt8188-imgsys                                         clock-controller@15110000              mediatek,mt8188-imgsys1-dip-top                                         w         clock-controller@15130000             mediatek,mt8188-imgsys1-dip-nr                                          w         clock-controller@15220000             mediatek,mt8188-imgsys-wpe1             "                            w         clock-controller@15330000             mediatek,mt8188-ipesys              3                            w         clock-controller@15520000             mediatek,mt8188-imgsys-wpe2             R                            w         clock-controller@15620000             mediatek,mt8188-imgsys-wpe3             b                            w         clock-controller@16000000             mediatek,mt8188-camsys                                           c   0      clock-controller@1604f000             mediatek,mt8188-camsys-rawa                                        w           c   3      clock-controller@1606f000             mediatek,mt8188-camsys-yuva                                        w           c   4      clock-controller@1608f000             mediatek,mt8188-camsys-rawb                                        w           c   1      clock-controller@160af000             mediatek,mt8188-camsys-yuvb             
                           w           c   2      clock-controller@17200000             mediatek,mt8188-ccusys                                         video-decoder@18000000            mediatek,mt8188-vcodec-dec                              @                                    `                                   +                 video-codec@10000             mediatek,mtk-vcodec-lat                                  (   4           (   x         a   (   4   .      .      (   x        hsel vdec lat top            A                   H                                                       P   =         video-codec@25000             mediatek,mtk-vcodec-core                 P                   (   4           (   x         a   (   4   /      /      (   x        hsel vdec lat top            A                   X                                                                 P   =            smi@1800d000              mediatek,mt8188-smi-larb                                 a   .       .            hapb smi         P   =                                 c         clock-controller@1800f000             mediatek,mt8188-vdecsys-soc                                         c   .      smi@1802e000              mediatek,mt8188-smi-larb                                a   /       /            hapb smi         P   =                                 c         clock-controller@1802f000             mediatek,mt8188-vdecsys                                        c   /      clock-controller@1a000000             mediatek,mt8188-vencsys                                          c   6      smi@1a010000              mediatek,mt8188-smi-larb                                 a   6      6           hapb smi         P   =                                 c         video-encoder@1a020000            mediatek,mt8188-vcodec-enc                                            +              (   3           (   p        a   6         	  hvenc_sel            A      a             X                                                                 P   =                    jpeg-encoder@1a030000         +    mediatek,mt8188-jpgenc mediatek,mtk-jpgenc                               a   6           hjpgenc          A      b                                            P   =         jpeg-decoder@1a040000         .    mediatek,mt8188-jpgdec mediatek,mt2701-jpgdec                                a   6       6           hjpgdec-smi jpgdec           A      c             0                                        P   =         ovl@1c000000          2    mediatek,mt8188-disp-ovl mediatek,mt8195-disp-ovl                                 a   ,            A      |                             P   =                           ports                        +       port@0                 endpoint            I           c            port@1                endpoint            I           c                  rdma@1c002000         4    mediatek,mt8188-disp-rdma mediatek,mt8195-disp-rdma                               a   ,           A      ~                              P   =                           ports                        +       port@0                 endpoint            I           c            port@1                endpoint            I           c                  color@1c003000        6    mediatek,mt8188-disp-color mediatek,mt8173-disp-color                0                a   ,           A                     P   =                   0       ports                        +       port@0                 endpoint            I           c            port@1                endpoint            I           c                  ccorr@1c004000        6    mediatek,mt8188-disp-ccorr mediatek,mt8192-disp-ccorr                @                a   ,           A                     P   =                   @       ports                        +       port@0                 endpoint            I           c            port@1                endpoint            I           c                  aal@1c005000          2    mediatek,mt8188-disp-aal mediatek,mt8183-disp-aal                P                a   ,           A                     P   =                   P       ports                        +       port@0                 endpoint            I           c            port@1                endpoint            I           c                  gamma@1c006000        6    mediatek,mt8188-disp-gamma mediatek,mt8195-disp-gamma                `                a   ,           A                     P   =                   `       ports                        +       port@0                 endpoint            I           c            port@1                endpoint            I           c                  dither@1c007000       8    mediatek,mt8188-disp-dither mediatek,mt8183-disp-dither              p                a   ,           A                     P   =                   p       ports                        +       port@0                 endpoint            I           c            port@1                endpoint            I           c                  dsi@1c008000              mediatek,mt8188-dsi                              a   ,      ,              hengine digital hs           A                                dphy            P   =           ^   ,           ^okay                         +       panel@0       #    startek,kd070fhfid078 himax,hx8279                                     %   -            2   %               -           >           edefault         s      port       endpoint            I           c               ports                        +       port@0                 endpoint            I           c            port@1                endpoint            I           c                  dsc@1c009000          2    mediatek,mt8188-disp-dsc mediatek,mt8195-disp-dsc                                a   ,   
        A                     P   =                             dsi@1c012000              mediatek,mt8188-dsi                              a   ,   	   ,              hengine digital hs           A                                dphy            P   =           ^   ,   	      	  ^disabled          merge0@1c014000       6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge               @                a   ,      5           hmerge merge_async           A                     P   =                   @          dp-intf@1c015000              mediatek,mt8188-dp-intf             P                a   ,       ,      '           hpixel engine pll            A                     P   =         	  ^disabled          mutex@1c016000            mediatek,mt8188-disp-mutex              `                a   ,           A                     P   =                   `              >      postmask@1c01a000         <    mediatek,mt8188-disp-postmask mediatek,mt8192-disp-postmask                             a   ,           A                     P   =                          ports                        +       port@0                 endpoint            I           c            port@1                endpoint            I           c                  syscon@1c01d000           mediatek,mt8188-vdosys0 syscon                                         w                                                 c   ,   port                         +       endpoint@0                      I           c               smi@1c022000              mediatek,mt8188-smi-larb                                 a   ,      ,           hapb smi         P   =                                  c         smi@1c023000              mediatek,mt8188-smi-larb                0                a   ,      ,           hapb smi         P   =                                 c         smi@1c024000              mediatek,mt8188-smi-common-vdo              @                a   ,      ,           hapb smi         P   =           c         iommu@1c028000            mediatek,mt8188-iommu-vdo                      P         a   ,           hbclk            A                     P   =           )                                  c         syscon@1c100000           mediatek,mt8188-vdosys1 syscon                                          w                                                 c   5   port                         +       endpoint@1                     I           c               mutex@1c101000            mediatek,mt8188-disp-mutex                              a   5           A                     P   =                                       smi@1c102000              mediatek,mt8188-smi-larb                                 a   5       5            hapb smi         P   =                                 c         smi@1c103000              mediatek,mt8188-smi-larb                0                a   5      5           hapb smi         P   =                                 c         rdma@1c104000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             @                a   5           A                           @        P   =                              @          rdma@1c105000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             P                a   5           A                           `        P   =                              P          rdma@1c106000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             `                a   5           A                           A        P   =                              `          rdma@1c107000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             p                a   5           A                           a        P   =                              p          rdma@1c108000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             a   5           A                           B        P   =                                        rdma@1c109000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             a   5           A                           b        P   =                                        rdma@1c10a000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             a   5           A                           C        P   =                                        rdma@1c10b000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             a   5           A                           c        P   =                                        merge@1c10c000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               a   5   	   5           hmerge merge_async           A                     P   =           ^   5                                :      merge@1c10d000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               a   5   
   5           hmerge merge_async           A                     P   =           ^   5                                :      merge@1c10e000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               a   5      5           hmerge merge_async           A                     P   =           ^   5                                :      merge@1c10f000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               a   5      5           hmerge merge_async           A                     P   =           ^   5                                :      merge@1c110000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                                a   5      5           hmerge merge_async           A                     P   =           ^   5                                 N   ports                        +       port@0                       +                   endpoint@1                     I           c            port@1                       +                  endpoint@1                     I           c                  dpi@1c112000          (    mediatek,mt8188-dpi mediatek,mt8195-dpi                              a   5   8   5      5   =        hpixel engine pll            A                     P   =           ^   5           ^okay       ports                        +       port@0                 endpoint            I           c            port@1                endpoint            I           c                  dp-intf@1c113000              mediatek,mt8188-dp-intf             0                a   5   :   5      '           hpixel engine pll            A                     P   =         	  ^disabled          ethdr@1c114000        6    mediatek,mt8188-disp-ethdr mediatek,mt8195-disp-ethdr         p      @            P            p                                                              4  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       h  a   5   0   5   +   5   .   5   ,   5   /   5   -   5   <   5   1   5   2   5   3   5   4   5   5   (           hmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          A      6                     d      e        P   =         (  ^   5   1   5   2   5   3   5   4   5   5      p          @            P            p                                                       ports                        +       port@0                       +                   endpoint@1                     I           c            port@1                       +                  endpoint@1                     I           c                  padding@1c11d000              mediatek,mt8188-disp-padding                                a   5           P   =                             padding@1c11e000              mediatek,mt8188-disp-padding                                a   5            P   =                             padding@1c11f000              mediatek,mt8188-disp-padding                                a   5   !        P   =                             padding@1c120000              mediatek,mt8188-disp-padding                                 a   5   "        P   =                              padding@1c121000              mediatek,mt8188-disp-padding                                a   5   #        P   =                             padding@1c122000              mediatek,mt8188-disp-padding                                 a   5   $        P   =                              padding@1c123000              mediatek,mt8188-disp-padding                0                a   5   %        P   =                   0          padding@1c124000              mediatek,mt8188-disp-padding                @                a   5   &        P   =                   @          hdmi@1c300000             mediatek,mt8188-hdmi-tx                        0                  a   (   @   (   >   (   ?   -   .        hbus hdcp hdcp24m hdmi-split            (   >           (   s        A                     P   =   	                   hdmi            ^okay            edefault         s           c      i2c       2    mediatek,mt8188-hdmi-ddc mediatek,mt8195-hdmi-ddc           a   <        c         ports                        +       port@0                 endpoint            I           c            port@1                endpoint            I           c                  edp-tx@1c500000           mediatek,mt8188-edp-tx              P                 A                                dp_calibration_data         P   =           e        	  ^disabled          dp-tx@1c600000            mediatek,mt8188-dp-tx               `                 A                                dp_calibration_data         P   =           e        	  ^disabled             backlight-lcm1            pwm-backlight           v                @                                              c         chosen          serial0:921600n8          dmic-codec                        dmic-codec                                c         connector             hdmi-connector          hdmi            a                            port       endpoint            I           c               firmware       optee             linaro,optee-tz         smc          reserved-memory                      +               optee@43200000                       C                memory@50000000           shared-dma-pool             P                          c   ;      memory@54600000                      T`                memory@55000000           shared-dma-pool             U       @        memory@57000000           shared-dma-pool             W       @        memory@60000000           shared-dma-pool             `                           c   C      memory@60f00000           shared-dma-pool             `                          c   ?      memory@61000000           shared-dma-pool             a                           c   B         regulator-0           regulator-fixed         vdd_5v           LK@         LK@        	   %   
                      D        )         regulator-1           regulator-fixed       	  vedp_3v3             2Z         2Z                 	   %               edefault         s           )         regulator-2           regulator-fixed         ext_3v3          2Z         2Z        	   %   	                      D        )         regulator-vsys            regulator-fixed         vsys             D         4        c         regulator-3           regulator-fixed         vio18_conn           w@         w@                  D      regulator-4           regulator-fixed       	  wifi_3v3             2Z         2Z        	   %   J                      D        )           c   k      regulator-5           regulator-fixed       
  vio33_tp1            2Z         2Z        	   %   w                     )           edefault         s           c   d      regulator-6           regulator-fixed       	  vhub_3v3             2Z         2Z        	   %   p            F  '                 )           c   P      regulator-7           regulator-fixed         vbus_p0          LK@         LK@        	   %   T                     )           c   o      regulator-8           regulator-fixed         vbus_p1          LK@         LK@        	   %   W                     )           c   {      regulator-9           regulator-fixed         vbus_p2          LK@         LK@                 c   l      regulator-vio18-lcm1              regulator-fixed         vio18_lcm1           w@         w@                 	   %   o            edefault         s           )           c         regulator-vsys-lcm1           regulator-fixed       
  vsys_lcm1            @@         @@         D         4        )           c         memory@40000000         memory              @                   	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dpi1 dsc0 ethdr0 gce0 gce1 merge0 merge1 merge2 merge3 merge4 merge5 mutex0 mutex1 padding0 padding1 padding2 padding3 padding4 padding5 padding6 padding7 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 dsi0 ethernet0 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 mmc0 mmc1 serial0 device_type reg enable-method clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-output-names opp-shared opp-hz opp-microvolt opp-supported-hw interrupts mediatek,platform status pinctrl-names pinctrl-0 audio-routing mediatek,adsp link-name sound-dai polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux bias-pull-up output-high drive-strength input-enable input-disable bias-disable bias-pull-down drive-strength-microamp output-low #power-domain-cells domain-supply clocks clock-names mediatek,infracfg mediatek,disable-extrst #sound-dai-cells #io-channel-cells mediatek,mic-type-0 mediatek,mic-type-1 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread mediatek,long-press-mode power-off-time-sec linux,keycodes wakeup-source assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells memory-region power-domains resets reset-names mediatek,topckgen mboxes mbox-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select phys mediatek,syscon-wakeup dr_mode usb-role-switch vusb33-supply peer-hub reset-gpios vdd-supply remote-endpoint interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,mac-wol snps,reset-gpio snps,reset-delays-us snps,blen snps,rd_osr_lmt snps,wr_osr_lmt snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,priority snps,weight interrupts-extended bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v supports-cqe cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc cd-gpios clock-div irq-gpios AVDD28-supply VDDIO-supply maximum-speed role-switch-default-mode vbus-supply id-gpios bus-range linux,pci-domain interrupt-map interrupt-map-mask iommu-map iommu-map-mask phy-names #phy-cells mediatek,ibias mediatek,ibias_up mode-switch orientation-switch vcc-supply label data-role op-sink-microwatt power-role try-power-role pd-revision sink-pdos source-pdos svid vdo bits operating-points-v2 power-domain-names mali-supply #dma-cells iommus mediatek,gce-client-reg mediatek,gce-events mediatek,scp mediatek,larb-id mediatek,smi mediatek,larbs backlight enable-gpios iovcc-supply mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz brightness-levels default-brightness-level num-interpolated-steps power-supply pwms stdout-path num-channels wakeup-delay-ms ddc-i2c-bus hdmi-pwr-supply no-map enable-active-high vin-supply regulator-boot-on startup-delay-us 