 PS   8 B   (            G A                             =    ezurio,mt8370-tungsten-smarc mediatek,mt8370 mediatek,mt8188                                     +         "   7Ezurio Tungsten510 SMARC (MT8370)      aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dpi@1c112000            T/soc/dsc@1c009000            Y/soc/ethdr@1c114000          `/soc/mailbox@10320000            e/soc/mailbox@10330000            j/soc/merge0@1c014000             q/soc/merge@1c10c000          x/soc/merge@1c10d000          /soc/merge@1c10e000          /soc/merge@1c10f000          /soc/merge@1c110000          /soc/mutex@1c016000          /soc/mutex@1c101000          /soc/padding@1c11d000            /soc/padding@1c11e000            /soc/padding@1c11f000            /soc/padding@1c120000            /soc/padding@1c121000            /soc/padding@1c122000            /soc/padding@1c123000            /soc/padding@1c124000            /soc/rdma@1c104000           /soc/rdma@1c105000           /soc/rdma@1c106000          /soc/rdma@1c107000          /soc/rdma@1c108000          !/soc/rdma@1c109000          ,/soc/rdma@1c10a000          7/soc/rdma@1c10b000          B/soc/dsi@1c008000           G/soc/ethernet@11021000          Q/soc/i2c@11280000           V/soc/i2c@11e00000           [/soc/i2c@11281000           `/soc/i2c@11282000           e/soc/i2c@11e01000           j/soc/i2c@11ec0000           o/soc/i2c@11ec1000           t/soc/mmc@11230000           y/soc/mmc@11240000           ~/soc/mmc@11250000         *  /soc/i2c@11280000/i2c-mux@73/i2c@0/rtc@52           /soc/pwrap@10024000/pmic/rtc            /soc/serial@11001100          cpus                         +       cpu@0           cpu           arm,cortex-a55                      psci            w5                                               @                                 @        1           >           O               c           r           }         cpu@100         cpu           arm,cortex-a55                     psci            w5                                               @                                 @        1           >           O               c           r           }         cpu@200         cpu           arm,cortex-a55                     psci            w5                                               @                                 @        1           >           O               c           r           }         cpu@300         cpu           arm,cortex-a55                     psci            w5                                               @                                 @        1           >           O               c           r           }         cpu@600         cpu           arm,cortex-a78                     psci            !V                                                @                                 @        1           >   	        O              c           r   
        }         cpu@700         cpu           arm,cortex-a78                     psci            !V                                                @                                 @        1           >   	        O              c           r   
        }         cpu-map    cluster0       core0                    core1                    core2                    core3                    core6                    core7                          idle-states         psci       cpu-off-l             arm,idle-state                                 2           _          D        }         cpu-off-b             arm,idle-state                                 -                             }         cluster-off-l             arm,idle-state                               7                     H        }         cluster-off-b             arm,idle-state                               2                             }            l2-cache0             cache                                    @                   >                    }         l2-cache1             cache                                    @                   >                    }   	      l3-cache              cache                                     @                            }            oscillator-13m            fixed-clock         
             ]@        clk13m          }   6      oscillator-26m            fixed-clock         
                    clk26m          }   8      oscillator-32k            fixed-clock         
                       clk32k        opp-table-gpu             operating-points-v2          *        }      opp-390000000           5    >        <         J         opp-431000000           5            <         J         opp-473000000           5    1h@        < 	'        J         opp-515000000           5    F        < 	X        J         opp-556000000           5    !#         < 	h        J         opp-598000000           5    #        < 	<        J         opp-640000000           5    &%         < 	        J         opp-670000000           5    'c        < 
        J         opp-700000000           5    )'         < 
L        J         opp-730000000           5    +        < 
}        J         opp-760000000           5    -L         < 
`        J         opp-790000000           5    /q        < 
4        J         opp-835000000           5    1        < (r        J         opp-880000000           5    4s         < q        J         opp-915000000           5    6        < X        J         opp-915000000-5         5    6        <         J   0      opp-915000000-6         5    6        < q        J   p      opp-950000000           5    8ـ        < 5         J         opp-950000000-5         5    8ـ        < X        J   0      opp-950000000-6         5    8ـ        < q        J   p         pmu-a55           arm,cortex-a55-pmu                      [                  pmu-a78           arm,cortex-a78-pmu                      [                  psci              arm,psci-1.0            smc       sound           f         	  xdisabled          thermal-zones      cpu-little0-thermal                                        trips      trip-alert0          L                  passive         }         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                     0                          cpu-little1-thermal                                       trips      trip-alert0          L                  passive         }         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                     0                          cpu-little2-thermal                                       trips      trip-alert0          L                  passive         }         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                     0                          cpu-little3-thermal                                       trips      trip-alert0          L                  passive         }         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                     0                          cpu-big0-thermal                         d                 trips      trip-alert0          L                  passive         }         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                                         cpu-big1-thermal                         d                 trips      trip-alert0          L                  passive         }         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                                         apu-thermal                                        trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                gpu-thermal                                       trips      trip-alert0          L                  passive         }         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                                      gpu1-thermal                                          trips      trip-alert0          L                  passive         }         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                                      adsp-thermal                                          trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                vdo-thermal                                       trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                infra-thermal                                         trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                cam1-thermal                                          trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                cam2-thermal                                          trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                   timer             arm,armv8-timer                   @  [                                             
                ]@      soc                      +             simple-bus                                             performance-controller@11bc10             mediatek,cpufreq-hw                           0                          }         interrupt-controller@c000000              arm,gic-v3                                             +                                             [      	               }      ppi-partitions     interrupt-partition-0           @                    }         interrupt-partition-1           @              }               syscon@10000000            mediatek,mt8188-topckgen syscon                               
           }   #      syscon@10001000       #    mediatek,mt8188-infracfg-ao syscon                               
           I           }   $      syscon@10003000           mediatek,mt8188-pericfg syscon               0                
           }   I      pinctrl@10005000              mediatek,mt8188-pinctrl       `       P                                                                               0  Viocfg0 iocfg_rm iocfg_lt iocfg_lm iocfg_rt eint          `        p           |                        +        [                                 }       audio-pins     pins-aud-pmic             e  f  g  h  i  j      pins-pcm-wifi             y  z  {  |      pins-i2s              w  p  x  q  n         disp-pwm0-pins          }   E   pins                                dsi0-sn65dsi84-pins         }   m   pins-irq                                       pins-enable                              eth-default-pins            }   Q   pins-txd                                     pins-cc                                pins-rxd                                            f      pins-mdio                                         pins-power                            pins-intr                         f                  eth-sleep-pins          }   R   pins-txd                              pins-cc                           pins-rxd                              pins-mdio                                            gpio-keys-pins     pins-keys                A   B                   hd3ss3320-pins          }   e   pins-irq              -            e                  hdmi-vreg-pins     pins-pwr              2                  hdmi-pins      pins-hotplug              3               pins-cec              4               pins-ddc              5  6           
         i2c0-pins           }   b   pins-bus              8  7                              i2c0-mux-pins           }   c   pins-reset                               i2c1-pins           }      pins-bus              :  9                              i2c2-pins           }   k   pins-bus              <  ;                              i2c3-pins           }   q   pins-bus              >  =                              i2c4-pins           }      pins-bus              @  ?                              i2c-mux-smarc-lcd-pins          }   l   pins-reset                               mmc0-default-pins           }   S   pins-cmd-dat          $                                                   e      pins-clk                                    f      pins-rst                                    e         mmc0-uhs-pins           }   T   pins-cmd-dat          $                                                   e      pins-clk                                    f      pins-ds                                 f      pins-rst                                    e         mmc1-default-pins           }   W   pins-cmd-dat                                                     e      pins-pwr              o                pins-pullup                           pins-clk                                    f      pins-insert                              mmc1-uhs-pins           }   X   pins-cmd-dat                                                     e      pins-clk                                    f         mmc2-default-pins           }   [   pins-clk                                    f      pins-cmd-dat                                                     e         mmc2-uhs-pins           }   \   pins-clk                                    f      pins-cmd-dat                                                     e         mmc2-eint-pins          }   ]   pins-dat1                                  e         rv3028-pins         }   d   pins-irq              *            e                  spi0-pins           }   C   pins-spi              E  F  G  H                  spi1-pins           }   F   pins-spi              K  L  M  N                  pcie-default-pins           }   ~   pins              /  0  1                  ts-dsi0-goodix-pins         }   p   pins-irq                          e               pins-reset                               uart0-pins          }   @   pins                                   uart1-pins          }   A   pins              !  "                  uart2-pins          }   B   pins              #  $                  usbotg-pins         }   u   pins-iddig            S                         pins-valid            U               pins-vbus             T                  usb1-hub-pins           }      pins                                 usb1-pins           }   K   pins              X                  usb2-eth-pins           }      pins              P                   wifi-pwrseq-pins            }      pins              Y                   watchdog-pins           }   5   pins              d                     syscon@10006000       )    mediatek,mt8188-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8188-power-controller                         +                       }   9   power-domain@0                                   +                       %   !   power-domain@1                     3   "      #           :mfg alt         F   $                     +                       %   %   power-domain@2                               power-domain@3                               power-domain@4                                     power-domain@15                    3   #      #      #      #   
   #   3   #   4   #   =   #      #      &      &      &      &      &      &      &      &      &      &      &      &      &      &      &      &      &      &      &            :top cam ccu img venc vdec wpe cfgck cfgxo ss-sram-cmn ss-sram-v0l0 ss-sram-v0l1 ss-sram-ve0 ss-sram-ve1 ss-sram-ifa ss-sram-cam ss-sram-v1l5 ss-sram-v1l6 ss-sram-rdr ss-iommu ss-imgcam ss-emi ss-subcmn-rdr ss-rsi ss-cmn-l4 ss-vdec1 ss-wpe ss-cvdo-ve1          F   $                     +                  power-domain@16                  H  3   #      #      '      '      '      '      '      '      '         A  :cfgck cfgxo ss-gals ss-cmn ss-emi ss-iommu ss-larb ss-rsi ss-bus            F   $                     +                  power-domain@20                  0  3   #      #      (      (      (      (         8  :cfgck cfgxo ss-vpp1-g5 ss-vpp1-g6 ss-vpp1-l5 ss-vpp1-l6         F   $                  power-domain@22                    3   )            :ss-vdec1-soc-l1         F   $                     +                  power-domain@23                    3   *            :ss-vdec2-l1         F   $                     power-domain@29                     3   #      #      #   	   #           :cam ccu bus cfgck           F   $                     +                  power-domain@30                  (  3   +       +      +      +      +         6  :ss-cam-l13 ss-cam-l14 ss-cam-mm0 ss-cam-mm1 ss-camsys           F   $                     +                  power-domain@32                     3   +      ,       -          $  :ss-camb-sub ss-camb-raw ss-camb-yuv                   power-domain@31                    3   +      .       /          $  :ss-cama-sub ss-cama-raw ss-cama-yuv                         power-domain@17                  (  3   #      #      0       0      0         &  :cfgck cfgxo ss-larb2 ss-larb3 ss-gals           F   $                     +                  power-domain@9             	        3   #   @   #   ?      	  :bus hdcp            F   $                  power-domain@18                    F   $                  power-domain@19                    F   $                     power-domain@24                     3   1       1      1      1         0  :ss-ve1-larb ss-ve1-core ss-ve1-gals ss-ve1-sram         F   $                  power-domain@21                    3   2      2           :ss-wpe-l7 ss-wpe-l7pce          F   $                        power-domain@5                     F   $        3   3           :ss-pextp-fmem                     power-domain@7                     3   #   0   #   1        :seninf0 seninf1                   power-domain@6                               power-domain@10            
        3   #   E   #   D      	  :bus main            F   $                     +                  power-domain@11                    F   $                     +                  power-domain@14                    3   #   F        :asm         F   $                  power-domain@13                    3   #   S   #      4            :a1sys intbus adspck         F   $                  power-domain@12                    F   $                        power-domain@8                     3   3         	  :ethermac            F   $                        watchdog@10007000             mediatek,mt8188-wdt              p                 X        I           pdefault         ~   5        }   :      syscon@1000c000       "    mediatek,mt8188-apmixedsys syscon                                
           }   "      timer@10017000        ,    mediatek,mt8188-timer mediatek,mt6765-timer             p                [      	               3   6      pwrap@10024000        3    mediatek,mt8188-pwrap mediatek,mt8195-pwrap syscon              @                Vpwrap           [                      3   $      $          	  :spi wrap       pmic              mediatek,mt6359          +                                           adc           mediatek,mt6359-auxadc                   audio-codec           mediatek,mt6359-codec                               regulators            mediatek,mt6359-regulator      buck_vs1            vs1          5          !        &             B      buck_vgpu11       
  dvdd_core                     7        V          &           k                   B      buck_vmodem         vmodem                            V  *        &            B      buck_vpu          
  dvdd_adsp                     7        V          &           k                   B      buck_vcore          dvdd_proc_l                            V          &           k                   B        }         buck_vs2            vs2          j          j         &             B               buck_vpa            vpa_pmu                    7        &  ,         B      buck_vproc2         vgpu             dp         5         V  L        &           k                     %         n        }   !      buck_vproc1         vproc1                    7        V  L        &           k                buck_vcore_sshub            vcore_sshub                   7      buck_vgpu11_sshub           vgpu11_sshub                      7      ldo_vaud18          vaud18           w@         w@        &         ldo_vsim1         
  vsim1_pmu                     w@        &          }   Y      ldo_vibr            vibr             O         2Z      ldo_vrf12           va12_abb2_pmu                               B      ldo_vusb            vusb             -         -        &           B        }   J      ldo_vsram_proc2         vsram_proc2                            V  L        &            B      ldo_vio18           vio18                             &           B      ldo_vcamio          vcamio                          ldo_vcn18         
  vcn18_pmu            w@         w@        &            B                 }   _      ldo_vfe28           vfe28            *         *        &   x      ldo_vcn13           vcn13                            ldo_vcn33_1_bt          vcn33_1_pmu          *         5g         B      ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g      ldo_vaux18          vaux18           w@         w@        &            B      ldo_vsram_others          
  vsram_gpu            q         5         V          &              !         n        }   %      ldo_vefuse          vefuse                            }         ldo_vxo22           vxo22            w@         !         B      ldo_vrfck           vrfck            `               ldo_vrfck_1         vrfck                     j       ldo_vbif28          vbif28           *         *        &         ldo_vio28           vio28            *         2Z         B      ldo_vemc            vemc             ,@          2Z      ldo_vemc_1          vemc             &%         2Z         B        }   U      ldo_vcn33_2_bt          vcn33_2_pmu          2Z         2Z         B                 }   ^      ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g      ldo_va12            va12             O                   B      ldo_va09            va09             5          O      ldo_vrf18           vrf18                     P      ldo_vsram_md          	  vsram_md                               V  *        &            B      ldo_vufs            vufs18_pmu                             B        }   V      ldo_vm18            vm18                               B      ldo_vbbck           vbbck                     O         B      ldo_vsram_proc1         vsram_proc1                            V  L        &            B      ldo_vsim2           vsim2                     /M`      ldo_vsram_others_sshub          vsram_others_sshub                              rtc           mediatek,mt6358-rtc       keys              mediatek,mt6359-keys                              power-key              t                        spmi@10027000         *    mediatek,mt8188-spmi mediatek,mt8195-spmi                p                            Vpmif spmimst               #   8        "   #           3   $      $       #   8      (  :pmif_sys_ck pmif_tmr_ck spmimst_clk_mux                      +       pmic@6            mediatek,mt6315-regulator                     regulators     vbuck1          vbuck1                    7        &           k                   B        }   
      vbuck3          vbuck3                    7        &           k                   B      vbuck4          vbuck4           7         7        &           k                   B   regulator-state-mem          9        Q 7                  iommu@10315000            mediatek,mt8188-iommu-infra             1P                [                     m           }   |      mailbox@10320000              mediatek,mt8188-gce             2        @         [                      z           3   $           }         mailbox@10330000              mediatek,mt8188-gce             3        @         [                      z           3   $           }         scp@10720000              mediatek,mt8188-scp-dual                r                 Vcfg                      +                   P             xokay       scp@0             mediatek,scp-core                          Vsram            [                     xokay               7        }         scp@d0000             mediatek,scp-core                        Vsram            [                   	  xdisabled             audio-controller@10b10000             mediatek,mt8188-afe                                 #   S        "   #           3   8   "   	   "   
   #      #      #      #      #      #   S   #      #       #   E   #   Q   #   M   #   N   #   O   #   P   4       #      #      #      #   T   #   R        :clk26m apll1 apll2 apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 top_a1sys_hp top_aud_intbus top_audio_h top_audio_local_bus top_dptx top_i2so1 top_i2so2 top_i2si1 top_i2si2 adsp_audio_26m apll1_d4 apll2_d4 apll12_div4 top_a2sys top_aud_iec          [      6                  9              :         	  audiosys            F   $           #        xokay               ;        }         adsp@10b80000             mediatek,mt8188-dsp       @                                                             Vcfg sram sec bus               #   D        3   #   D   #   E        :audiodsp adsp_bus              <   =        rx tx              9           xokay               >   ?      mailbox@10b86100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox             a                [                     z            }   <      mailbox@10b87100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox             q                [                     z            }   =      clock-controller@10b91100             mediatek,mt8188-adsp-audio26m                               
           }   4      serial@11001100       *    mediatek,mt8188-uart mediatek,mt6577-uart                                [                      3   8   $         	  :baud bus            xokay            ~   @        pdefault       serial@11001200       *    mediatek,mt8188-uart mediatek,mt6577-uart                                [                      3   8   $         	  :baud bus            xokay            ~   A        pdefault       serial@11001300       *    mediatek,mt8188-uart mediatek,mt6577-uart                                [                      3   8   $         	  :baud bus            xokay            ~   B        pdefault       serial@11001400       *    mediatek,mt8188-uart mediatek,mt6577-uart                                [                     3   8   $         	  :baud bus          	  xdisabled          adc@11002000          .    mediatek,mt8188-auxadc mediatek,mt8173-auxadc                                 3   $           :main                     	  xdisabled          syscon@11003000       "    mediatek,mt8188-pericfg-ao syscon                0                
           }   3      spi@1100a000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 [                      3   #   y   #      $           :parent-clk sel-clk spi-clk          xokay            ~   C        pdefault                   thermal-sensor@1100b000           mediatek,mt8188-lvts-ap                              [                      3   $              $              D        lvts-calib-data-1           
           }         pwm@1100e000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm                                3   #   '   $   /        :main mm         [                                  xokay            pdefault         ~   E        }         pwm@1100f000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm                                3   #   (   $   F        :main mm         [                               	  xdisabled          spi@11010000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 [                      3   #   y   #      $   2        :parent-clk sel-clk spi-clk          xokay            ~   F        pdefault                   spi@11012000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 [                      3   #   y   #      $   3        :parent-clk sel-clk spi-clk        	  xdisabled          spi@11013000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                0                [                      3   #   y   #      $   4        :parent-clk sel-clk spi-clk        	  xdisabled          spi@11018000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                [                      3   #   y   #      $   8        :parent-clk sel-clk spi-clk        	  xdisabled          spi@11019000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                [                      3   #   y   #      $   9        :parent-clk sel-clk spi-clk        	  xdisabled          usb@11201000          #    mediatek,mt8188-mtu3 mediatek,mtu3                       -     >              	  Vmac ippc                                 ?                      +           [                         #   )        "   #   v        3   3   	   #      3   
        :sys_ck ref_ck mcu_ck            +   G      H                    0   I  h           xokay            Ghost            O   J        ~   K        pdefault    usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 Vmac         [                         #   *        "   #   v        3   3   
        :sys_ck          xokay            ]   L        O   J         ethernet@11021000         ;    mediatek,mt8188-gmac mediatek,mt8195-gmac snps,dwmac-5.10a                     @         [                     imacirq        0  3   3       3      #   A   #   B   #   C   3         .  :axi apb mac_main ptp_ref rmii_internal mac_cg              #   A   #   B   #   C        "   #      #      #              9           y   $           M           N           O                                          xokay          	  rgmii-id               P        pdefault sleep           ~   Q           R         	        	                   	"        	8      *     mdio              snps,dwmac-mdio                      +       ethernet-phy@7            ethernet-phy-ieee802.3-c22                                       }   P         stmmac-axi-config           	M                                 	W           	g           }   M      rx-queues-config            	w            	        }   N   queue0           	        	          queue1           	        	          queue2           	        	          queue3           	        	             tx-queues-config            	            	        }   O   queue0           	        	            	         queue1           	        	           	         queue2           	        	           	         queue3           	        	           	               mmc@11230000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              #                                                        3   #      $      $      $   M      !  :source hclk source_cg crypto_clk            xokay            
            
         
'        
8 H        
G          
U         
d         
s         
         
         
        pdefault state_uhs           ~   S           T        
   U        
   V      mmc@11240000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              $                                                       3   #      $      $   $        :source hclk source_cg              #           "   #           xokay            
            
        
G          
         
        pdefault state_uhs           ~   W           X        
                  
   Y        
   Z      mmc@11250000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              %                                                                  3   #      $      $   A        :source hclk source_cg              #           "   #           xokay            
            
         
         
        
G                   
s         
         
                 pdefault state_uhs state_eint            ~   [           \           ]        imsdc sdio_wakeup            
   ^        
   _           `      thermal-sensor@11278000           mediatek,mt8188-lvts-mcu                '                [                      3   $              $               D        lvts-calib-data-1           
           }         i2c@11280000              mediatek,mt8188-i2c              (             "                [                      )           3   a       $   7      	  :main dma                         +            xokay            pdefault         ~   b            i2c-mux@73            nxp,pca9546            s        pdefault         ~   c        3                               +       i2c@0                                             +       rtc@52            microcrystal,rv3028            R               *           pdefault         ~   d        
                      i2c@1                                            +       usb-typec@60              ti,hd3ss3220               `               -           pdefault         ~   e   ports                        +       port@0                 endpoint            ?   f        }   x         port@1                endpoint            ?   g        }   z                  i2c@2                                            +       codec@1a              wlf,wm8962                     3   #   M        O   h        [   h        h   i        u   h           i           h           j           j                                     i2c@3                                            +                i2c@11281000              mediatek,mt8188-i2c              (            "               [                      )           3   a      $   7      	  :main dma                         +            xokay            pdefault         ~   k            i2c-mux@73            nxp,pca9546            s        pdefault         ~   l        3                               +       i2c@0                                             +          i2c@1                                            +          i2c@2                                            +       bridge@2c             ti,sn65dsi84               ,        pdefault         ~   m                      ports                        +       port@0                 endpoint            ?   n                            }            port@2                endpoint            ?   o        }                  touchscren@5d             goodix,gt911               ]        pdefault         ~   p                                             3                    i2c@3                                            +                i2c@11282000              mediatek,mt8188-i2c              (             "               [                      )           3   a      $   7      	  :main dma                         +            xokay            pdefault         ~   q               clock-controller@11283000             mediatek,mt8188-imp-iic-wrap-c              (0                
           }   a      usb@112a1000          #    mediatek,mt8188-mtu3 mediatek,mtu3               *       -    *>              	  Vmac ippc                        *        ?                      +           [                        #   -        "   #   v        3   3      #      3           :sys_ck ref_ck mcu_ck            +   r                    0   I  p           xokay            Ghost            high-speed          O   J   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 Vmac         [                        #   .        "   #   v        3   3           :sys_ck          xokay            ]   s        O   J                     +       ethernet@1            usb424,7850                                 +       mdio                         +       ethernet-phy@1                                                    usb@112b1000          #    mediatek,mt8188-mtu3 mediatek,mtu3               +       -    +>              	  Vmac ippc                        +        ?                      +           [                        #   ,        "   #   v        3   3      #      3           :sys_ck ref_ck mcu_ck            +   t                    0   I  `           xokay            Gotg         high-speed           	        O   J        ~   u        pdefault    usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 Vmac         [                        #   +        "   #   v        3   3           :sys_ck          xokay            ]   v        O   J      connector             usb-c-connector         USB-C           dual       ports                        +       port@0                 endpoint            ?   w        }   y         port@1                endpoint            ?   x        }   f               ports                        +       port@0                 endpoint            ?   y        }   w         port@1                endpoint            ?   z        }   g               pcie@112f0000         *    mediatek,mt8188-pcie mediatek,mt8192-pcie               /                	  Vpcie-mac                                              )               pci         3                         +         0  3   $   L   $   #   $   &   $   +   $   C   3         /  :pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                     [                   `  D                  {                      {                     {                     {           R                       e       |              o            +   }         	  ~pcie-phy               9              :           mac         xokay            pdefault         ~   ~   interrupt-controller                                     +        }   {         spi@1132c000          (    mediatek,mt8188-nor mediatek,mt8186-nor             2                3   #   X   3      3           :spi sf axi             #   X        [      9                            +          	  xdisabled          t-phy@11c20700        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                                            +              9           xokay       pcie-phy@0                         3   #           :ref                    }   }         hdmi-phy@11d5f000         2    mediatek,mt8188-hdmi-phy mediatek,mt8195-hdmi-phy                               3   $           :pll_ref         hdmi_txpll          
                           
                 	  xdisabled            }         dsi-phy@11c80000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx                              3   8        mipi_tx0_pll            
                        xokay            }         dsi-phy@11c90000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx                              3   8        mipi_tx0_pll            
                      	  xdisabled            }         i2c@11e00000              mediatek,mt8188-i2c                           "                [                      )           3          $   7      	  :main dma                         +            xokay            pdefault         ~                  i2c@11e01000              mediatek,mt8188-i2c                          "               [                      )           3         $   7      	  :main dma                         +            xokay            pdefault         ~                  clock-controller@11e02000             mediatek,mt8188-imp-iic-wrap-w                               
           }         t-phy@11e30000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                xokay       usb-phy@0                          3   #      "           :ref da_ref                     xokay            }   t         t-phy@11e40000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                xokay       usb-phy@0                          3   #      "           :ref da_ref                     xokay            }   G      usb-phy@700                       3   "      8        :ref da_ref                     xokay            }   H         t-phy@11e80000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                xokay       usb-phy@0                          3   #      "           :ref da_ref                     xokay            }   r         i2c@11ec0000              mediatek,mt8188-i2c                           "               [                      )           3          $   7      	  :main dma                         +          	  xdisabled          i2c@11ec1000              mediatek,mt8188-i2c                          "                [                      )           3         $   7      	  :main dma                         +          	  xdisabled          clock-controller@11ec2000              mediatek,mt8188-imp-iic-wrap-en                              
           }         efuse@11f20000        ,    mediatek,mt8188-efuse mediatek,mt8186-efuse                                           +      dp-calib@1a0                         }         lvts1-calib@1ac              @        }   D      gpu-speedbin@581                                        }         socinfo-data1@7a0                      socinfo-data2@7e0                         gpu@13000000          )    mediatek,mt8370-mali arm,mali-valhall-jm                         @         3             0  [                   ~             }               ijob mmu gpu                  
  speed-bin                         9      9           core0 core1         c           xokay               !        }         clock-controller@13fbf000             mediatek,mt8188-mfgcfg                              
           }         syscon@14000000           mediatek,mt8188-vppsys0 syscon                                
           }   &      dma-controller@14001000           mediatek,mt8188-mdp3-rdma                                           3   &         <                                                                        9                                              *         display@14002000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                               3   &                                display@14004000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                @                3   &   "                 @          display@14005000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal                P                [      F               3   &   
           9                    P          display@14006000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                3   &                    `                %      display@14007000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                p                3   &   #                 p          display@14008000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                                [      I               3   &   $           9                              display@14009000          2    mediatek,mt8188-mdp3-ovl mediatek,mt8195-mdp3-ovl                                [      J               3   &   %           9                                            display@1400a000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                                3   &              9                              display@1400b000          2    mediatek,mt8188-mdp3-tcc mediatek,mt8195-mdp3-tcc                                3   &                              display@1400c000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot                                         3   &                            9                                    +      mutex@1400f000            mediatek,mt8188-vpp-mutex                                [      P               3   &              9                              smi@14012000              mediatek,mt8188-smi-common-vpp                               3   &      &           :apb smi            9           }         smi@14013000              mediatek,mt8188-smi-larb                0                3   &      &           :apb smi            9           7           H           }         iommu@14018000            mediatek,mt8188-iommu-vpp                      P         3   &           :bclk            [      R                  9           m           U                          }         dma-controller@14f09000           mediatek,mt8188-mdp3-rdma                                          3   (   
                         9                 	                        dma-controller@14f0a000           mediatek,mt8188-mdp3-rdma                                          3   (                            9                 	                        display@14f0c000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                             3   (                 	            display@14f0d000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                             3   (                 	            display@14f0f000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                               3   (   "              	            display@14f10000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                                3   (   $              
             display@14f12000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal                                [      j               3   (   #           9                 
             display@14f13000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal               0                [      k               3   (   %           9                 
  0          display@14f15000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz               P                3   (                 
  P                      display@14f16000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz               `                3   (                 
  `                      display@14f18000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                               3   (                 
            display@14f19000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                               3   (                 
            display@14f1a000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge                               3   (              9                 
            display@14f1b000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge                               3   (              9                 
            display@14f1d000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                               [      u               3   (              9                 
            display@14f1e000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                               [      v               3   (              9                 
            display@14f21000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                               3   (              9                             display@14f22000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                                3   (              9                              display@14f24000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot             @                           3   (                            9                   @                      display@14f25000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot             P                           3   (                            9                   P                      clock-controller@14e00000             mediatek,mt8188-wpesys                               
           }   2      clock-controller@14e02000             mediatek,mt8188-wpesys-vpp0                              
         smi@14e04000              mediatek,mt8188-smi-larb                @                3   2      2           :apb smi            9           7           H           }         syscon@14f00000           mediatek,mt8188-vppsys1 syscon                               
           }   (      mutex@14f01000            mediatek,mt8188-vpp-mutex                               [      {               3   (   &           9                 	            smi@14f02000              mediatek,mt8188-smi-larb                                 3   (      (           :apb smi            9           7           H           }         smi@14f03000              mediatek,mt8188-smi-larb                0                3   (      (           :apb smi            9           7           H           }         clock-controller@15000000             mediatek,mt8188-imgsys                                
         clock-controller@15110000              mediatek,mt8188-imgsys1-dip-top                              
           I         clock-controller@15130000             mediatek,mt8188-imgsys1-dip-nr                               
           I         clock-controller@15220000             mediatek,mt8188-imgsys-wpe1             "                 
           I         clock-controller@15330000             mediatek,mt8188-ipesys              3                 
           I         clock-controller@15520000             mediatek,mt8188-imgsys-wpe2             R                 
           I         clock-controller@15620000             mediatek,mt8188-imgsys-wpe3             b                 
           I         clock-controller@16000000             mediatek,mt8188-camsys                                
           }   +      clock-controller@1604f000             mediatek,mt8188-camsys-rawa                             
           I           }   .      clock-controller@1606f000             mediatek,mt8188-camsys-yuva                             
           I           }   /      clock-controller@1608f000             mediatek,mt8188-camsys-rawb                             
           I           }   ,      clock-controller@160af000             mediatek,mt8188-camsys-yuvb             
                
           I           }   -      clock-controller@17200000             mediatek,mt8188-ccusys                                
         video-decoder@18000000            mediatek,mt8188-vcodec-dec                              @                                    `                                   +           *      video-codec@10000             mediatek,mtk-vcodec-lat                                  #   4        "   #   x         3   #   4   )      )      #   x        :sel vdec lat top            [                   H                                                          9         video-codec@25000             mediatek,mtk-vcodec-core                 P                   #   4        "   #   x         3   #   4   *      *      #   x        :sel vdec lat top            [                   X                                                                    9            smi@1800d000              mediatek,mt8188-smi-larb                                 3   )       )            :apb smi            9           7           H           }         clock-controller@1800f000             mediatek,mt8188-vdecsys-soc                              
           }   )      smi@1802e000              mediatek,mt8188-smi-larb                                3   *       *            :apb smi            9           7           H           }         clock-controller@1802f000             mediatek,mt8188-vdecsys                             
           }   *      clock-controller@1a000000             mediatek,mt8188-vencsys                               
           }   1      smi@1a010000              mediatek,mt8188-smi-larb                                 3   1      1           :apb smi            9           7           H           }         video-encoder@1a020000            mediatek,mt8188-vcodec-enc                                            +              #   3        "   #   p        3   1         	  :venc_sel            [      a             X                                                                    9           *         jpeg-encoder@1a030000         +    mediatek,mt8188-jpgenc mediatek,mtk-jpgenc                               3   1           :jpgenc          [      b                                               9         jpeg-decoder@1a040000         .    mediatek,mt8188-jpgdec mediatek,mt2701-jpgdec                                3   1       1           :jpgdec-smi jpgdec           [      c             0                                           9         ovl@1c000000          2    mediatek,mt8188-disp-ovl mediatek,mt8195-disp-ovl                                 3   '            [      |                                9                           ports                        +       port@0                 endpoint            ?           }            port@1                endpoint            ?           }                  rdma@1c002000         4    mediatek,mt8188-disp-rdma mediatek,mt8195-disp-rdma                               3   '           [      ~                                 9                           ports                        +       port@0                 endpoint            ?           }            port@1                endpoint            ?           }                  color@1c003000        6    mediatek,mt8188-disp-color mediatek,mt8173-disp-color                0                3   '           [                        9                   0       ports                        +       port@0                 endpoint            ?           }            port@1                endpoint            ?           }                  ccorr@1c004000        6    mediatek,mt8188-disp-ccorr mediatek,mt8192-disp-ccorr                @                3   '           [                        9                   @       ports                        +       port@0                 endpoint            ?           }            port@1                endpoint            ?           }                  aal@1c005000          2    mediatek,mt8188-disp-aal mediatek,mt8183-disp-aal                P                3   '           [                        9                   P       ports                        +       port@0                 endpoint            ?           }            port@1                endpoint            ?           }                  gamma@1c006000        6    mediatek,mt8188-disp-gamma mediatek,mt8195-disp-gamma                `                3   '           [                        9                   `       ports                        +       port@0                 endpoint            ?           }            port@1                endpoint            ?           }                  dither@1c007000       8    mediatek,mt8188-disp-dither mediatek,mt8183-disp-dither              p                3   '           [                        9                   p       ports                        +       port@0                 endpoint            ?           }            port@1                endpoint            ?           }                  dsi@1c008000              mediatek,mt8188-dsi                              3   '      '              :engine digital hs           [                     +           ~dphy               9              '           xokay                         +       ports                        +       port@0                 endpoint            ?           }            port@1                endpoint            ?           }   n               dsc@1c009000          2    mediatek,mt8188-disp-dsc mediatek,mt8195-disp-dsc                                3   '   
        [                        9                             dsi@1c012000              mediatek,mt8188-dsi                              3   '   	   '              :engine digital hs           [                     +           ~dphy               9              '   	      	  xdisabled          merge0@1c014000       6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge               @                3   '      0           :merge merge_async           [                        9                   @          dp-intf@1c015000              mediatek,mt8188-dp-intf             P                3   '       '      "           :pixel engine pll            [                        9         	  xdisabled          mutex@1c016000            mediatek,mt8188-disp-mutex              `                3   '           [                        9                   `              >      postmask@1c01a000         <    mediatek,mt8188-disp-postmask mediatek,mt8192-disp-postmask                             3   '           [                        9                          ports                        +       port@0                 endpoint            ?           }            port@1                endpoint            ?           }                  syscon@1c01d000           mediatek,mt8188-vdosys0 syscon                              
           I                                                 }   '   port                         +       endpoint@0                      ?           }               smi@1c022000              mediatek,mt8188-smi-larb                                 3   '      '           :apb smi            9           7            H           }         smi@1c023000              mediatek,mt8188-smi-larb                0                3   '      '           :apb smi            9           7           H           }         smi@1c024000              mediatek,mt8188-smi-common-vdo              @                3   '      '           :apb smi            9           }         iommu@1c028000            mediatek,mt8188-iommu-vdo                      P         3   '           :bclk            [                        9           m           U                       }         syscon@1c100000           mediatek,mt8188-vdosys1 syscon                               
           I                                                 }   0      mutex@1c101000            mediatek,mt8188-disp-mutex                              3   0           [                        9                                       smi@1c102000              mediatek,mt8188-smi-larb                                 3   0       0            :apb smi            9           7           H           }         smi@1c103000              mediatek,mt8188-smi-larb                0                3   0      0           :apb smi            9           7           H           }         rdma@1c104000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             @                3   0           [                           @           9                              @          rdma@1c105000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             P                3   0           [                           `           9                              P          rdma@1c106000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             `                3   0           [                           A           9                              `          rdma@1c107000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             p                3   0           [                           a           9                              p          rdma@1c108000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             3   0           [                           B           9                                        rdma@1c109000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             3   0           [                           b           9                                        rdma@1c10a000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             3   0           [                           C           9                                        rdma@1c10b000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             3   0           [                           c           9                                        merge@1c10c000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               3   0   	   0           :merge merge_async           [                        9              0                                d      merge@1c10d000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               3   0   
   0           :merge merge_async           [                        9              0                                d      merge@1c10e000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               3   0      0           :merge merge_async           [                        9              0                                d      merge@1c10f000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               3   0      0           :merge merge_async           [                        9              0                                d      merge@1c110000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                                3   0      0           :merge merge_async           [                        9              0                                 x      dpi@1c112000          (    mediatek,mt8188-dpi mediatek,mt8195-dpi                              3   0   8   0      0   =        :pixel engine pll            [                        9              0         	  xdisabled       ports                        +       port@0                 endpoint             port@1                endpoint                   dp-intf@1c113000              mediatek,mt8188-dp-intf             0                3   0   :   0      "           :pixel engine pll            [                        9         	  xdisabled          ethdr@1c114000        6    mediatek,mt8188-disp-ethdr mediatek,mt8195-disp-ethdr         p      @            P            p                                                              4  Vmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       h  3   0   0   0   +   0   .   0   ,   0   /   0   -   0   <   0   1   0   2   0   3   0   4   0   5   #           :mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          [      6                     d      e           9         (     0   1   0   2   0   3   0   4   0   5      p          @            P            p                                                          padding@1c11d000              mediatek,mt8188-disp-padding                                3   0              9                             padding@1c11e000              mediatek,mt8188-disp-padding                                3   0               9                             padding@1c11f000              mediatek,mt8188-disp-padding                                3   0   !           9                             padding@1c120000              mediatek,mt8188-disp-padding                                 3   0   "           9                              padding@1c121000              mediatek,mt8188-disp-padding                                3   0   #           9                             padding@1c122000              mediatek,mt8188-disp-padding                                 3   0   $           9                              padding@1c123000              mediatek,mt8188-disp-padding                0                3   0   %           9                   0          padding@1c124000              mediatek,mt8188-disp-padding                @                3   0   &           9                   @          hdmi@1c300000             mediatek,mt8188-hdmi-tx                        0                  3   #   @   #   >   #   ?   (   .        :bus hdcp hdcp24m hdmi-split            #   >        "   #   s        [                        9   	        +           ~hdmi          	  xdisabled       i2c       2    mediatek,mt8188-hdmi-ddc mediatek,mt8195-hdmi-ddc           3   8      ports                        +       port@0                 endpoint             port@1                endpoint                   edp-tx@1c500000           mediatek,mt8188-edp-tx              P                 [                                dp_calibration_data            9                   	  xdisabled          dp-tx@1c600000            mediatek,mt8188-dp-tx               `                 [                                dp_calibration_data            9                   	  xdisabled             backlight-lcd0            pwm-backlight                                                                          u0        }         chosen          serial0:115200n8          firmware       optee             linaro,optee-tz         smc          memory@40000000         memory              @                panel-dsi0            tianma,tm070jdhg30                        j   port       endpoint            ?           }   o            reserved-memory                      +               optee@43200000           
            C                memory@50000000           shared-dma-pool             P                  
        }   7      memory@54600000          
            T`                memory@55000000           shared-dma-pool             U       @        memory@57000000           shared-dma-pool             W       @        memory@60000000           shared-dma-pool             `                   
        }   ?      memory@60f00000           shared-dma-pool             `                  
        }   ;      memory@61000000           shared-dma-pool             a                   
        }   >         regulator-efuse           regulator-output                     regulator-1v8             regulator-fixed         reg_1v8          w@         w@         B        }   h      regulator-3v3             regulator-fixed         reg_3v3          2Z         2Z         B        }   i      regulator-5v              regulator-fixed         reg_5v           LK@         LK@         B        }   j      regulator-sdcard-en           regulator-fixed          B        sdcard_en_3v3            2Z         2Z        	       o                     }   Z      regulator-usb-p0-vbus             regulator-fixed         vbus_p0          LK@         LK@        	       T                     }   v      regulator-usb-p1-vbus             regulator-fixed         pdefault         ~           vbus_p1          w@         w@        	                            }   L      regulator-usb-p2-vbus             regulator-fixed         pdefault         ~           vbus_p2          w@         w@        	       P                     }   s      wifi-pwrseq           mmc-pwrseq-simple           pdefault         ~           0           3       Y           }   `         	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dpi1 dsc0 ethdr0 gce0 gce1 merge0 merge1 merge2 merge3 merge4 merge5 mutex0 mutex1 padding0 padding1 padding2 padding3 padding4 padding5 padding6 padding7 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 dsi0 ethernet0 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 mmc0 mmc1 mmc2 rtc0 rtc1 serial0 device_type reg enable-method clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-output-names opp-shared opp-hz opp-microvolt opp-supported-hw interrupts mediatek,platform status polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux bias-pull-down input-enable drive-strength bias-pull-up output-high input-disable bias-disable drive-strength-microamp output-low #power-domain-cells domain-supply clocks clock-names mediatek,infracfg mediatek,disable-extrst pinctrl-names pinctrl-0 #sound-dai-cells interrupts-extended #io-channel-cells mediatek,mic-type-0 mediatek,mic-type-1 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-boot-on regulator-coupled-with regulator-coupled-max-spread mediatek,long-press-mode power-off-time-sec linux,keycodes wakeup-source assigned-clocks assigned-clock-parents regulator-on-in-suspend regulator-suspend-microvolt #iommu-cells #mbox-cells memory-region power-domains resets reset-names mediatek,topckgen mboxes mbox-names mediatek,pad-select nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells phys mediatek,syscon-wakeup dr_mode vusb33-supply vbus-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,mac-wol snps,reset-gpio snps,reset-active-low snps,reset-delays-us snps,blen snps,rd_osr_lmt snps,wr_osr_lmt snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,priority snps,weight bus-width cap-mmc-highspeed cap-mmc-hw-reset hs400-ds-delay max-frequency mmc-hs200-1_8v mmc-hs400-1_8v non-removable no-sd no-sdio supports-cqe vmmc-supply vqmmc-supply cap-sd-highspeed sd-uhs-sdr104 sd-uhs-sdr50 cd-gpios cap-sdio-irq keep-power-in-suspend no-mmc pinctrl-2 mmc-pwrseq clock-div reset-gpios remote-endpoint AVDD-supply CPVDD-supply DBVDD-supply DCVDD-supply MICVDD-supply PLLVDD-supply SPKVDD1-supply SPKVDD2-supply gpio-cfg enable-gpios data-lanes irq-gpios maximum-speed microchip,led-modes usb-role-switch label data-role bus-range linux,pci-domain interrupt-map interrupt-map-mask iommu-map iommu-map-mask phy-names #phy-cells mediatek,ibias mediatek,ibias_up bits operating-points-v2 power-domain-names mali-supply #dma-cells iommus mediatek,gce-client-reg mediatek,gce-events mediatek,scp mediatek,larb-id mediatek,smi mediatek,larbs mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz brightness-levels default-brightness-level num-interpolated-steps pwms stdout-path backlight power-supply no-map vout-supply enable-active-high post-power-on-delay-ms 