 Q   8 F   (             F                             %    mediatek,mt8195-demo mediatek,mt8195                                     +            7MediaTek MT8195 demo board     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dpi@1c112000            T/soc/mailbox@10320000            Y/soc/mailbox@10330000            ^/soc/hdmi-tx@1c300000            d/soc/hdr-engine@1c114000             k/soc/mutex@1c016000          r/soc/mutex@1c101000          y/soc/vpp-merge@1c10c000          /soc/vpp-merge@1c10d000          /soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000             /soc/serial@11001100          cpus                         +       cpu@0            cpu           arm,cortex-a55                      psci                           .ec3@        >  4        Q              a           n   @                                 @                                            	      cpu@100          cpu           arm,cortex-a55                     psci                           .ec3@        >  4        Q              a           n   @                                 @                                            
      cpu@200          cpu           arm,cortex-a55                     psci                           .ec3@        >  4        Q              a           n   @                                 @                                                  cpu@300          cpu           arm,cortex-a55                     psci                           .ec3@        >  4        Q              a           n   @                                 @                                                  cpu@400          cpu           arm,cortex-a78                     psci                          .f        >           Q              a           n   @                                 @                                                  cpu@500          cpu           arm,cortex-a78                     psci                          .f        >           Q              a           n   @                                 @                                                  cpu@600          cpu           arm,cortex-a78                     psci                          .f        >           Q              a           n   @                                 @                                                  cpu@700          cpu           arm,cortex-a78                     psci                          .f        >           Q              a           n   @                                 @                                                  cpu-map    cluster0       core0              	      core1              
      core2                    core3                    core4                    core5                    core6                    core7                          idle-states         psci       cpu-retention-l           arm,idle-state                     	           2        +   _        ;  D                 cpu-retention-b           arm,idle-state                     	           -        +           ;                   cpu-off-l             arm,idle-state                    	           7        +           ;  H                 cpu-off-b             arm,idle-state                    	           2        +           ;                      l2-cache0             cache           L           c           p   @                               X                 l2-cache1             cache           L           c           p   @                               X                 l3-cache              cache           L           c            p   @                    X                    dsu-pmu           arm,dsu-pmu         f                       q   	   
                          vfail          dmic-codec            dmic-codec          }              2      mt8195-sound                     	  vdisabled          fixed-factor-clock-13m            fixed-factor-clock                                                       clk13m             (      oscillator-26m            fixed-clock                     .        clk26m                   oscillator-32k            fixed-clock                     .           clk32k        performance-controller@11bc10             mediatek,cpufreq-hw                           0                                   opp-table-gpu             operating-points-v2                     a   opp-390000000               >         	h      opp-410000000               p         	      opp-431000000                        	      opp-473000000               1h@         	<      opp-515000000               F         	<      opp-556000000               !#          	Ҧ      opp-598000000               #         	      opp-640000000               &%          	      opp-670000000               'c         
      opp-700000000               )'          
L      opp-730000000               +         
}      opp-760000000               -L          
`      opp-790000000               /q         
4      opp-820000000               05                opp-850000000               2         @      opp-880000000               4s          q         pmu-a55           arm,cortex-a55-pmu                      f                  pmu-a78           arm,cortex-a78-pmu                      f                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  f                                             
             soc                      +             simple-bus           "        )                          interrupt-controller@c000000              arm,gic-v3          4           E                        \                                             f      	                     ppi-partitions     interrupt-partition-0           q   	   
                       interrupt-partition-1           q                                   syscon@10000000            mediatek,mt8195-topckgen syscon                                                   syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon                                          z                    syscon@10003000           mediatek,mt8195-pericfg syscon               0                              ;      pinctrl@10005000              mediatek,mt8195-pinctrl              P                                                                                                         B  iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint                                                      \        f                      4                 eth-default-pins               7   pins-txd              M  N  O  P                 pins-cc           U  X  W  V                 pins-rxd              Q  R  S  T      pins-mdio             Y  Z               pins-power            [   \                   eth-sleep-pins             8   pins-txd              M   N   O   P       pins-cc           U   X   W   V       pins-rxd              Q   R   S   T       pins-mdio             Y   Z                            gpio-keys-pins                pins              j                   i2c6-pins              P   pins                                  mmc0-default-pins              >   pins-clk              z                      f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                               e      pins-rst              x                      e         mmc0-uhs-pins              ?   pins-clk              z                      f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                               e      pins-ds                                 f      pins-rst              x                      e         mmc1-default-pins              B   pins-clk              o                      f      pins-cmd-dat              n  p  q  r  s                               e      pins-insert                              mmc1-uhs-pins              C   pins-clk              o                      f      pins-cmd-dat              n  p  q  r  s                               e         uart0-pins             .   pins              b  c         uart1-pins             /   pins              f  g            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8195-power-controller                         +                          *   power-domain@8                                  +                  power-domain@9             	                            3mfg alt         ?                        +                  power-domain@10            
                  power-domain@11                              power-domain@12                              power-domain@13                              power-domain@14                                    power-domain@15                                            	      @      A      K                                                                                                                                3vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           ?                        +                  power-domain@16                  8              $      %      &      '      (      )      D  3vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         ?                        +                  power-domain@17                                              3vppsys1 vppsys1-0 vppsys1-1         ?                     power-domain@22                                                   $  3wepsys-0 wepsys-1 wepsys-2 wepsys-3         ?                     power-domain@23                                   3vdec0-0         ?                        +                   power-domain@24                                   3vdec1-0         ?                     power-domain@25                                    3vdec2-0         ?                        power-domain@26                       !            3venc0-larb          ?                        +                   power-domain@27                       "            3venc1-larb          ?                        power-domain@18                              #       #      #         &  3vdosys1 vdosys1-0 vdosys1-1 vdosys1-2           ?                        +                  power-domain@19                    ?                     power-domain@20                    ?                     power-domain@21                          Q        3hdmi_tx                      power-domain@28                       $       $   
        3img-0 img-1         ?                        +                  power-domain@29                              power-domain@30                             $      %           3ipe ipe-0 ipe-1         ?                        power-domain@31                  (     &       &      &      &      &           3cam-0 cam-1 cam-2 cam-3 cam-4           ?                        +                  power-domain@32                               power-domain@33            !                  power-domain@34            "                           power-domain@0                      ?                     power-domain@1                     ?                     power-domain@2                               power-domain@3                               power-domain@4                           5      7        3csi_rx_top csi_rx_top1                    power-domain@5                        '           3ether                     power-domain@6                           X      n        3adsp adsp1                       +            ?                 power-domain@7                            g      "      n      2        3audio audio1 audio2 audio3          ?                              watchdog@10007000             mediatek,mt8195-wdt          Q             p                z              -      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon                                                    timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer             p                f      	                  (      pwrap@10024000            mediatek,mt8195-pwrap syscon                @                pwrap           f                                         	  3spi wrap            i      $        y         pmic              mediatek,mt6359          \        4                                  adc           mediatek,mt6359-auxadc                   audio-codec           mediatek,mt6359-codec         regulators            mediatek,mt6359-regulator      buck_vs1            vs1          5          !                     "      buck_vgpu11         vgpu11                    7        6                     K                   "      buck_vmodem         vmodem                            6  *                 buck_vpu            vpu                   7        6                     K                   "      buck_vcore          vcore                              6                     K                   "      buck_vs2            vs2          5          j                      "      buck_vpa            vpa                    7          ,      buck_vproc2         vproc2                    7        6  L                   K                   "      buck_vproc1         vproc1                    7        6  L                   K                   "      buck_vcore_sshub            vcore_sshub                   7      buck_vgpu11_sshub           vgpu11_sshub                      7      ldo_vaud18          vaud18           w@         w@                 ldo_vsim1           vsim1                     /M`      ldo_vibr            vibr             O         2Z      ldo_vrf12           vrf12                               "      ldo_vusb            vusb             -         -                   "           <      ldo_vsram_proc2         vsram_proc2                            6  L                    "      ldo_vio18           vio18                                        "      ldo_vcamio          vcamio                          ldo_vcn18           vcn18            w@         w@                 ldo_vfe28           vfe28            *         *           x      ldo_vcn13           vcn13                            ldo_vcn33_1_bt          vcn33_1_bt           *         5g      ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g      ldo_vaux18          vaux18           w@         w@                    "      ldo_vsram_others            vsram_others                               6                      "      ldo_vefuse          vefuse                          ldo_vxo22           vxo22            w@         !         "      ldo_vrfck           vrfck            `               ldo_vrfck_1         vrfck                     j       ldo_vbif28          vbif28           *         *                 ldo_vio28           vio28            *         2Z         "      ldo_vemc            vemc             ,@          2Z      ldo_vemc_1          vemc             &%         2Z           @      ldo_vcn33_2_bt          vcn33_2_bt           *         5g      ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g      ldo_va12            va12             O                   "      ldo_va09            va09             5          O      ldo_vrf18           vrf18                     P      ldo_vsram_md          	  vsram_md                               6  *                    "      ldo_vufs            vufs                                 A      ldo_vm18            vm18                               "      ldo_vbbck           vbbck                     O         "      ldo_vsram_proc1         vsram_proc1                            6  L                    "      ldo_vsim2           vsim2                     /M`      ldo_vsram_others_sshub          vsram_others_sshub                              rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi                 p                            pmif spmimst                               E      (  3pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         i      $        y            infra-iommu@10315000              mediatek,mt8195-iommu-infra             1P       P       P  f                                                                         c              K      mailbox@10320000              mediatek,mt8195-gce             2        @         f                      p                                  mailbox@10330000              mediatek,mt8195-gce             3        @         f                      p                            b      scp@10500000              mediatek,mt8195-scp       0      P             r             p                 sram cfg l1tcm          f                   	  vdisabled               c      clock-controller@10720000             mediatek,mt8195-scp_adsp                r                               )      dsp@10803000              mediatek,mt8195-dsp              0                           	  cfg sram          ,        X         n         )          #      K  3adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          |   *           rx tx              +   ,      	  vdisabled          mailbox@10816000              mediatek,mt8195-adsp-mbox           p                `                f                        +      mailbox@10817000              mediatek,mt8195-adsp-mbox           p                p                f                        ,      mt8195-afe-pcm@10890000           mediatek,mt8195-audio                                           |   *           f      6                  -         	  audiosys                                                               g      "      #      n      e      a      b      c      d      2   )            3clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  vdisabled                     serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f                                     	  3baud bus            vokay            default            .      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f                                     	  3baud bus            vokay            default            /      serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f                                     	  3baud bus          	  vdisabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f                                    	  3baud bus          	  vdisabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f                                    	  3baud bus          	  vdisabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f                                    	  3baud bus          	  vdisabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc                                               3main                     	  vdisabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon                0                              '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 f                                                3parent-clk sel-clk spi-clk        	  vdisabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap                              f                                                      0   1      $  lvts-calib-data-1 lvts-calib-data-2                             svs@1100bc00              mediatek,mt8195-svs                              f                                    3main               2   0      (  svs-calibration-data t-calibration-data                       svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                                f                      |   *                            *      0        3main mm       	  vdisabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                                f                                      +      N        3main mm       	  vdisabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 f                                        3        3parent-clk sel-clk spi-clk        	  vdisabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 f                                        4        3parent-clk sel-clk spi-clk        	  vdisabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                0                f                                        5        3parent-clk sel-clk spi-clk        	  vdisabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                f                                        <        3parent-clk sel-clk spi-clk        	  vdisabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                f                                        =        3parent-clk sel-clk spi-clk        	  vdisabled          spi@1101d000              mediatek,mt8195-spi-slave                               f                            R        3spi         i              y            	  vdisabled          spi@1101e000              mediatek,mt8195-spi-slave                               f                            S        3spi         i              y            	  vdisabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a                      @         f                     macirq        .  3axi apb mac_main ptp_ref rmii_internal mac_cg         0     '       '         R      S      T   '           i      R      S      T        y                          |   *           '           8   3        H   4        [   5        n           y                       vokay          	  rgmii-id               6              ]                  ' 8        default sleep              7           8            mdio              snps,dwmac-mdio                      +       ethernet-phy@1                        6         stmmac-axi-config                                                                     3      rx-queues-config                        %           4   queue0           6        I          queue1           6        I          queue2           6        I          queue3           6        I             tx-queues-config            a            w           5   queue0                      6                  queue1                      6                 queue2                      6                 queue3                      6                       usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3                       -     >              	  mac ippc            "                     ?                      +           f                            /            B        3sys_ck ref_ck mcu_ck               9      :                       ;      g        vokay               <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 mac         f                      i      ,      -        y                  $        /                     B      $  3sys_ck ref_ck mcu_ck dma_ck xhci_ck         vokay               =         mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              #                              f                                                3source hclk source_cg           vokay            default state_uhs              >           ?                                                         /         @         H        N L        ]   @        i   A         v      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              $                              f                                        $        3source hclk source_cg           i              y              vokay            default state_uhs              B           C                                                                        ]   D        i   E      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              %                              f                                         I        3source hclk source_cg           i               y            	  vdisabled          ufshci@11270000           mediatek,mt8195-ufshci              '        #         f                         F      @        ?      @      A      6      7      8      Z      ]      X  3ufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @                                                                                 	  vdisabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu                '                f                                                     0   1      $  lvts-calib-data-1 lvts-calib-data-2                             usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci               )             )>              	  mac ippc            f                        G      H           i      .      /        y                  $     '                     '         $  3sys_ck ref_ck mcu_ck dma_ck xhci_ck            ;      h                 vokay               <      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               *       -    *>              	  mac ippc            "            *        ?                      +           f                     i      0        y                 '            '           3sys_ck ref_ck mcu_ck               I                       ;      i        vokay               <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 mac         f                     i      1        y                 '           3sys_ck          vokay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               +       -    +>              	  mac ippc            "            +        ?                      +           f                     i      2        y                 '            '   	        3sys_ck ref_ck mcu_ck               J                       ;      j        vokay               <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 mac         f                     i      3        y                 '   	        3sys_ck          vokay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            pci                      +               /        @       	  pcie-mac            f                                  8  "                                                                   K                        0        V      #      &      +      K   '         /  3pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          i      G        y                 L      	  	pcie-phy            |   *            4           	                     `  	                   M                      M                     M                     M         	  vdisabled       interrupt-controller             \                     4              M         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            pci                      +               /       @       	  pcie-mac            f                                  8  "       $       $                  $       $                        K                        (        W         X         Q   '         /  3pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          i      H        y                 H         	  	pcie-phy            |   *           4           	                     `  	                   N                      N                     N                     N         	  vdisabled       interrupt-controller             \                     4              N         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor             2                f      9                     o   '      '           3spi sf axi                       +          	  vdisabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse                                              +      usb3-tx-imp@184,1                        	.                  X      usb3-rx-imp@184,2                        	.                 W      usb3-intr@185                        	.                 V      usb3-tx-imp@186,1                        	.                  U      usb3-rx-imp@186,2                        	.                 T      usb3-intr@187                        	.                 S      usb2-intr-p0@188,1                       	.             usb2-intr-p1@188,2                       	.            usb2-intr-p2@189,1                       	.            usb2-intr-p3@189,2                       	.            pciephy-rx-ln1@190,1                         	.                  _      pciephy-tx-ln1-nmos@190,2                        	.                 ^      pciephy-tx-ln1-pmos@191,1                        	.                  ]      pciephy-rx-ln0@191,2                         	.                 \      pciephy-tx-ln0-nmos@192,1                        	.                  [      pciephy-tx-ln0-pmos@192,2                        	.                 Z      pciephy-glb-intr@193                         	.                  Y      dp-data@1ac                               lvts1-calib@1bc                         0      lvts2-calib@1d0              8           1      svs-calib@580                d           2      socinfo-data1@7a0                         t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           "                     vokay       usb-phy@0                                        3ref         	3              I         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           "                     vokay       usb-phy@0                                        3ref         	3              J         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx                                         mipi_tx0_pll                        	3          	  vdisabled                     dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx                                         mipi_tx1_pll                        	3          	  vdisabled                     i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "               f                                    O          ;      	  3main dma                         +          	  vdisabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                          "                f                                    O         ;      	  3main dma                         +            vokay            .            P        default    pmic@34           mediatek,mt6360            4         \        4                 e           IRQB       charger           mediatek,mt6360-chg         	> @   usb-otg-vbus-regulator          usb-otg-vbus             C(         X           =         regulator             mediatek,mt6360-regulator           	W   Q   buck1           mt6360,buck1                               K                   "      buck2           mt6360,buck2                               K                   "           Q      ldo1            mt6360,ldo1          O         6        K             ldo2            mt6360,ldo2          O         6        K             ldo3            mt6360,ldo3          O         6        K                  E      ldo5            mt6360,ldo5          )2         6        K                  D      ldo6            mt6360,ldo6                              K             ldo7            mt6360,ldo7                              K                "               i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "               f                                    O         ;      	  3main dma                         +          	  vdisabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s              0                              O      hdmi-phy@11d5f000             mediatek,mt8195-hdmi-phy                                       P                          3pll_ref 26m pll1 pll2           hdmi_txpll                      	3            	g   
        	v         	  vdisabled                     i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "                f                                    R          ;      	  3main dma                         +          	  vdisabled          i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                          "                f                                    R         ;      	  3main dma                         +          	  vdisabled          i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "               f                                    R         ;      	  3main dma                         +          	  vdisabled          i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              0            "               f                                    R         ;      	  3main dma                         +          	  vdisabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              @            "                f                                    R         ;      	  3main dma                         +          	  vdisabled          clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w              P                              R      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           "                     |   *           vokay       usb-phy@0                                           3ref da_ref          	3              G      usb-phy@700                                           3ref da_ref             S   T   U        intr rx_imp tx_imp          	3              H         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           "                     vokay       usb-phy@0                                           3ref da_ref          	3              9      usb-phy@700                                           3ref da_ref             V   W   X        intr rx_imp tx_imp          	3              :         phy@11e80000              mediatek,mt8195-pcie-phy                                 sif            Y   Z   [   \   ]   ^   _      G  glb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          |   *           	3          	  vdisabled               L      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy                                            
  3unipro mp           	3          	  vdisabled               F      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm                        @            `          0  f                                               job mmu gpu         	   a      (  |   *   
   *      *      *      *           	core0 core1 core2 core3 core4         	  vdisabled          clock-controller@13fbf000             mediatek,mt8195-mfgcfg                                            `      syscon@14000000           mediatek,mt8195-vppsys0 syscon                                           	   b                            dma-controller@14001000           mediatek,mt8195-mdp3-rdma                                	   b                  	              	   c        |   *           	   d                       <     b         b         b         b         b              	         display@14002000              mediatek,mt8195-mdp3-fg                               	   b                                display@14003000              mediatek,mt8195-mdp3-stitch              0                	   b      0                        display@14004000              mediatek,mt8195-mdp3-hdr                 @                	   b      @                  "      display@14005000              mediatek,mt8195-mdp3-aal                 P                f      F               	   b      P                  
        |   *         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                	   b      `            	    %                    display@14007000              mediatek,mt8195-mdp3-tdshp               p                	   b      p                  #      display@14008000              mediatek,mt8195-mdp3-color                               f      I               	   b                        $        |   *         display@14009000              mediatek,mt8195-mdp3-ovl                                 f      J               	   b                        %        |   *           	   d         display@1400a000              mediatek,mt8195-mdp3-padding                                 	   b                                |   *         display@1400b000              mediatek,mt8195-mdp3-tcc                                 	   b                              dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot                              	   b                  	    +                      	   d           |   *           	         mutex@1400f000            mediatek,mt8195-vpp-mutex                                f      P               	   b                                |   *         smi@14010000              mediatek,mt8195-smi-sub-common                                                         3apb smi gals0           	   e        |   *              f      smi@14011000              mediatek,mt8195-smi-sub-common                                                        3apb smi gals0           	   e        |   *                    smi@14012000              mediatek,mt8195-smi-common-vpp                                                                3apb smi gals0 gals1         |   *              e      larb@14013000             mediatek,mt8195-smi-larb                0                
           	   f                            3apb smi         |   *              i      iommu@14018000            mediatek,mt8195-iommu-vpp                             8  
   g   h   i   j   k   l   m   n   o   p   q   r   s   t        f      R                             3bclk            c           |   *              d      clock-controller@14e00000             mediatek,mt8195-wpesys                                                   clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0                                       clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1             0                         larb@14e04000             mediatek,mt8195-smi-larb                @                
           	   u                            3apb smi         |   *                    larb@14e05000             mediatek,mt8195-smi-larb                P                
           	   e                                  3apb smi gals            |   *              k      syscon@14f00000           mediatek,mt8195-vppsys1 syscon                                          	   b   	                        mutex@14f01000            mediatek,mt8195-vpp-mutex                               f      {               	   b   	                    '        |   *         larb@14f02000             mediatek,mt8195-smi-larb                                 
           	   u                                  3apb smi gals            |   *                    larb@14f03000             mediatek,mt8195-smi-larb                0                
           	   f                                  3apb smi gals            |   *              j      display@14f06000              mediatek,mt8195-mdp3-split              `                	   b   	  `                        +      ,        |   *         display@14f07000              mediatek,mt8195-mdp3-tcc                p                	   b   	  p                        dma-controller@14f08000           mediatek,mt8195-mdp3-rdma                               	   b   	              	                          	   v           |   *           	         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma                               	   b   	              	                  
        	   v           |   *           	         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma                               	   b   	              	                          	   d           |   *           	         display@14f0b000              mediatek,mt8195-mdp3-fg                             	   b   	                    	      display@14f0c000              mediatek,mt8195-mdp3-fg                             	   b   	                          display@14f0d000              mediatek,mt8195-mdp3-fg                             	   b   	                          display@14f0e000              mediatek,mt8195-mdp3-hdr                                	   b   	                          display@14f0f000              mediatek,mt8195-mdp3-hdr                                	   b   	                          display@14f10000              mediatek,mt8195-mdp3-hdr                                 	   b   
                            display@14f11000              mediatek,mt8195-mdp3-aal                                f      i               	   b   
                            |   *         display@14f12000              mediatek,mt8195-mdp3-aal                                 f      j               	   b   
                             |   *         display@14f13000              mediatek,mt8195-mdp3-aal                0                f      k               	   b   
  0                  !        |   *         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               @                	   b   
  @            	                        display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               P                	   b   
  P            	                  $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               `                	   b   
  `            	                  %      display@14f17000              mediatek,mt8195-mdp3-tdshp              p                	   b   
  p                        display@14f18000              mediatek,mt8195-mdp3-tdshp                              	   b   
                    (      display@14f19000              mediatek,mt8195-mdp3-tdshp                              	   b   
                    )      display@14f1a000              mediatek,mt8195-mdp3-merge                              	   b   
                            |   *         display@14f1b000              mediatek,mt8195-mdp3-merge                              	   b   
                            |   *         display@14f1c000              mediatek,mt8195-mdp3-color                              f      t               	   b   
                            |   *         display@14f1d000              mediatek,mt8195-mdp3-color                              	   b   
              f      u                             |   *         display@14f1e000              mediatek,mt8195-mdp3-color                              f      v               	   b   
                            |   *         display@14f1f000              mediatek,mt8195-mdp3-ovl                                f      w               	   b   
                             |   *           	   v         display@14f20000              mediatek,mt8195-mdp3-padding                                 	   b                                |   *         display@14f21000              mediatek,mt8195-mdp3-padding                                	   b                               |   *         display@14f22000              mediatek,mt8195-mdp3-padding                                 	   b                                |   *         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             0                	   b     0            	                          	   v           |   *           	         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             @                	   b     @            	                          	   v           |   *           	         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             P                	   b     P            	                          	   d           |   *           	         clock-controller@15000000             mediatek,mt8195-imgsys                                              $      larb@15001000             mediatek,mt8195-smi-larb                                 
   	        	   w           $       $       $   
        3apb smi gals            |   *                    smi@15002000              mediatek,mt8195-smi-sub-common                                   $      $                 3apb smi gals0           	   e        |   *              z      smi@15003000              mediatek,mt8195-smi-sub-common               0                   $       $       $   
        3apb smi gals0           	   u        |   *              w      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top                                            x      larb@15120000             mediatek,mt8195-smi-larb                                 
   
        	   w           $      x            3apb smi         |   *                    clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr                                        clock-controller@15220000             mediatek,mt8195-imgsys1_wpe             "                               y      larb@15230000             mediatek,mt8195-smi-larb                #                 
           	   w           $      y            3apb smi         |   *                    clock-controller@15330000             mediatek,mt8195-ipesys              3                               %      larb@15340000             mediatek,mt8195-smi-larb                4                 
           	   z           %      %           3apb smi         |   *              l      clock-controller@16000000             mediatek,mt8195-camsys                                              &      larb@16001000             mediatek,mt8195-smi-larb                                 
           	   {           &       &       &           3apb smi gals            |   *                    larb@16002000             mediatek,mt8195-smi-larb                                  
           	   |           &      &           3apb smi         |   *              m      smi@16004000              mediatek,mt8195-smi-sub-common               @                   &       &       &           3apb smi gals0           	   u        |   *              {      smi@16005000              mediatek,mt8195-smi-sub-common               P                   &      &                 3apb smi gals0           	   e        |   *              |      larb@16012000             mediatek,mt8195-smi-larb                                 
           	   |           }       }            3apb smi         |   *               n      larb@16013000             mediatek,mt8195-smi-larb                0                
           	   {           ~       ~            3apb smi         |   *                     larb@16014000             mediatek,mt8195-smi-larb                @                
           	   |                              3apb smi         |   *   !           t      larb@16015000             mediatek,mt8195-smi-larb                P                
           	   {                              3apb smi         |   *   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa                                           }      clock-controller@1606f000             mediatek,mt8195-camsys_yuva                                           ~      clock-controller@1608f000             mediatek,mt8195-camsys_rawb                                                 clock-controller@160af000             mediatek,mt8195-camsys_yuvb             
                                    clock-controller@16140000             mediatek,mt8195-camsys_mraw                                                  larb@16141000             mediatek,mt8195-smi-larb                                
           	   {           &              &           3apb smi gals            |   *   "                 larb@16142000             mediatek,mt8195-smi-larb                                 
           	   |                              3apb smi         |   *   "           s      clock-controller@17200000             mediatek,mt8195-ccusys                                                    larb@17201000             mediatek,mt8195-smi-larb                                 
           	   |                              3apb smi         |   *              o      video-codec@18000000              mediatek,mt8195-vcodec-dec          	   c        	   v                       +                               @                "                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc                                	   d     d                 A                          3sel vdec lat top            i      A        y              |   *         video-codec@10000             mediatek,mtk-vcodec-lat                               f                   0  	   v      v     v     v     v     v                 A                          3sel vdec lat top            i      A        y              |   *         video-codec@25000             mediatek,mtk-vcodec-core                 P                f                   P  	   v     v     v     v     v     v     v     v     v     v                 A                          3sel vdec lat top            i      A        y              |   *            larb@1800d000             mediatek,mt8195-smi-larb                                 
           	   u                              3apb smi         |   *                    larb@1800e000             mediatek,mt8195-smi-larb                                 
           	                                3apb smi         |   *              r      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc                                                  larb@1802e000             mediatek,mt8195-smi-larb                                
           	   u                              3apb smi         |   *                    clock-controller@1802f000             mediatek,mt8195-vdecsys                                                 larb@1803e000             mediatek,mt8195-smi-larb                                
           	                                 3apb smi         |   *              q      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1                                                    clock-controller@190f3000             mediatek,mt8195-apusys_pll              0                         clock-controller@1a000000             mediatek,mt8195-vencsys                                             !      larb@1a010000             mediatek,mt8195-smi-larb                                 
           	   u           !      !           3apb smi         |   *                    video-codec@1a020000              mediatek,mt8195-vcodec-enc                             H  	   v  `   v  a   v  b   v  c   v  d   v  v   v  w   v  x   v  y        f      U               	   c           !         	  3venc_sel            i      @        y              |   *                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec          |   *         0  	   v  m   v  n   v  r   v  s   v  t   v  u                     +         0  "                                            jpgdec@0,0            mediatek,mt8195-jpgdec-hw                                0  	   v  m   v  n   v  r   v  s   v  t   v  u        f      W                  !           3jpgdec          |   *         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw                               0  	   v  m   v  n   v  r   v  s   v  t   v  u        f      X                  !           3jpgdec          |   *         jpgdec@1,0            mediatek,mt8195-jpgdec-hw                               0  	   d     d     d     d     d     d          f      \                  "           3jpgdec          |   *            clock-controller@1b000000             mediatek,mt8195-vencsys_core1                                               "      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon                                                             	                             jpeg-encoder@1a030000             mediatek,mt8195-jpgenc          |   *            	   d     d     d     d                       +         0  "                                            jpgenc@0,0            mediatek,mt8195-jpgenc-hw                                   	   v  g   v  h   v  i   v  l        f      V                  !           3jpgenc          |   *         jpgenc@1,0            mediatek,mt8195-jpgenc-hw                                  	   d     d     d     d          f      [                  "           3jpgenc          |   *            larb@1b010000             mediatek,mt8195-smi-larb                                 
           	   e           "      "                  3apb smi gals            |   *              p      ovl@1c000000              mediatek,mt8195-disp-ovl                                  f      |               |   *                          	   v           	                ports                        +       port@0                 endpoint             port@1                endpoint            
'                             rdma@1c002000             mediatek,mt8195-disp-rdma                                 f      ~               |   *                         	   v            	                ports                        +       port@0                 endpoint            
'                       port@1                endpoint            
'                             color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color                0                f                     |   *                         	        0       ports                        +       port@0                 endpoint            
'                       port@1                endpoint            
'                             ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr                @                f                     |   *                         	        @       ports                        +       port@0                 endpoint            
'                       port@1                endpoint            
'                             aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal                P                f                     |   *                         	        P       ports                        +       port@0                 endpoint            
'                       port@1                endpoint            
'                             gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma                `                f                     |   *                         	        `       ports                        +       port@0                 endpoint            
'                       port@1                endpoint            
'                             dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither              p                f                     |   *                 	        	        p       ports                        +       port@0                 endpoint            
'                       port@1                endpoint                   dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                              f                     |   *                       *           3engine digital hs                      	dphy          	  vdisabled          dsc@1c009000              mediatek,mt8195-disp-dsc                                 f                     |   *                         	                  dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                              f                     |   *                       +           3engine digital hs                      	dphy          	  vdisabled          merge@1c014000            mediatek,mt8195-disp-merge              @                f                     |   *                         	        @          dp-intf@1c015000              mediatek,mt8195-dp-intf             P                f                     |   *                 ,                    3pixel engine pll          	  vdisabled          mutex@1c016000            mediatek,mt8195-disp-mutex              `                f                     |   *                         	        `            	  U      larb@1c018000             mediatek,mt8195-smi-larb                                
            	   u              (      (              3apb smi gals            |   *                    larb@1c019000             mediatek,mt8195-smi-larb                                
           	   e              (                     3apb smi gals            |   *              g      syscon@1c100000           mediatek,mt8195-vdosys1 syscon                                                	                                z              #      smi@1c01b000              mediatek,mt8195-smi-common-vdo                                     %      &      )      $        3apb smi gals0 gals1         |   *              u      iommu@1c01f000            mediatek,mt8195-iommu-vdo                             8  
                                                  f                     c                 '        3bclk            |   *              v      mutex@1c101000            mediatek,mt8195-disp-mutex                              f                     |   *              #           	                    	        larb@1c102000             mediatek,mt8195-smi-larb                                 
           	   u           #       #       #           3apb smi gals            |   *                    larb@1c103000             mediatek,mt8195-smi-larb                0                
           	   e           #      #                  3apb smi gals            |   *              h      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma               @                f                        #           |   *           	   v   @        	        @            	         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma               P                f                        #           |   *           	   d   `        	        P            	         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma               `                f                        #           |   *           	   v   A        	        `            	         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma               p                f                        #           |   *           	   d   a        	        p            	         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma                               f                        #           |   *           	   v   B        	                    	         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma                               f                        #           |   *           	   d   b        	                    	         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma                               f                        #           |   *           	   v   C        	                    	         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma                               f                        #           |   *           	   d   c        	                    	         vpp-merge@1c10c000            mediatek,mt8195-disp-merge                              f                        #   	   #           3merge merge_async           |   *           	                     
7           #         vpp-merge@1c10d000            mediatek,mt8195-disp-merge                              f                        #   
   #           3merge merge_async           |   *           	                     
7           #         vpp-merge@1c10e000            mediatek,mt8195-disp-merge                              f                        #      #           3merge merge_async           |   *           	                     
7           #         vpp-merge@1c10f000            mediatek,mt8195-disp-merge                              f                        #      #           3merge merge_async           |   *           	                     
7           #         vpp-merge@1c110000            mediatek,mt8195-disp-merge                               f                        #      #           3merge merge_async           |   *           	                      
K           #         dpi@1c112000              mediatek,mt8195-dpi                                 #   -   #      #   2        3pixel engine pll            f                      |   *              #         	  vdisabled       ports                        +       port@0                 endpoint             port@1                endpoint                   dp-intf@1c113000              mediatek,mt8195-dp-intf             0                f                     |   *              #   /   #                 3pixel engine pll          	  vdisabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p      @            P            p                                                              4  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  	        @            P            p                                                          h     #   %   #       #   #   #   !   #   $   #   "   #   1   #   &   #   '   #   (   #   )   #   *              3mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          |   *           	   d   d   d   e        f                   (     #   3   #   4   #   5   #   6   #   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          hdmi-tx@1c300000              mediatek,mt8195-hdmi-tx                        0                        Q      L      M      ,        3bus hdcp hdcp24m hdmi-split         i      L        y              f                     |   *                      	hdmi          	  vdisabled       i2c           mediatek,mt8195-hdmi-ddc                     ports                        +       port@0                 endpoint             port@1                endpoint                   edp-tx@1c500000           mediatek,mt8195-edp-tx              P                            dp_calibration_data         |   *           f                     
b        	  vdisabled          dp-tx@1c600000            mediatek,mt8195-dp-tx               `                            dp_calibration_data         |   *           f                     
b        	  vdisabled             thermal-zones      cpu0-thermal            
s          
           
         trips      trip-alert          
 L        
          passive                  trip-crit           
         
        	  critical             cooling-maps       map0            
         0  
   	   
                  cpu1-thermal            
s          
           
         trips      trip-alert          
 L        
          passive                  trip-crit           
         
        	  critical             cooling-maps       map0            
         0  
   	   
                  cpu2-thermal            
s          
           
         trips      trip-alert          
 L        
          passive                  trip-crit           
         
        	  critical             cooling-maps       map0            
         0  
   	   
                  cpu3-thermal            
s          
           
         trips      trip-alert          
 L        
          passive                  trip-crit           
         
        	  critical             cooling-maps       map0            
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   	   
                  cpu4-thermal            
s          
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 L        
          passive                  trip-crit           
         
        	  critical             cooling-maps       map0            
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                        cpu5-thermal            
s          
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         trips      trip-alert          
 L        
          passive                  trip-crit           
         
        	  critical             cooling-maps       map0            
         0  
                        cpu6-thermal            
s          
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 L        
          passive                  trip-crit           
         
        	  critical             cooling-maps       map0            
         0  
                        cpu7-thermal            
s          
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          passive                  trip-crit           
         
        	  critical             cooling-maps       map0            
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                        vpu0-thermal            
s          
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        	  critical                vpu1-thermal            
s          
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serial0:921600n8          firmware       optee             linaro,optee-tz         smc          gpio-keys         
    gpio-keys           default               key-0                 j         
  
volume_up           
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            memory@40000000          memory              @                reserved-memory                      +            "   optee@43200000                       C                memory@50000000           shared-dma-pool             P                        memory@53000000           shared-dma-pool             S       @        memory@54600000                      T`                memory@60000000           shared-dma-pool             `                        memory@62000000           shared-dma-pool             b       @              	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dpi1 gce0 gce1 hdmi0 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux drive-strength input-enable output-high input-disable bias-disable bias-pull-up bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle snps,reset-gpio snps,reset-delays-us pinctrl-1 mediatek,mac-wol snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup vusb33-supply vbus-supply bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 freq-table-hz mediatek,ufs-disable-mcq bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN3-supply mediatek,ibias mediatek,ibias_up operating-points-v2 power-domain-names mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path label linux,code debounce-interval no-map 