    8 x   (             x                             1    google,tomato-rev1 google,tomato mediatek,mt8195                                     +            7Acer Tomato (rev1) board       aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dpi@1c112000            T/soc/mailbox@10320000            Y/soc/mailbox@10330000            ^/soc/hdmi-tx@1c300000            d/soc/hdr-engine@1c114000             k/soc/mutex@1c016000          r/soc/mutex@1c101000          y/soc/vpp-merge@1c10c000          /soc/vpp-merge@1c10d000          /soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000             /soc/i2c@11e00000            /soc/i2c@11e01000            /soc/i2c@11e02000           /soc/i2c@11e03000           /soc/i2c@11e04000           /soc/i2c@11d00000           /soc/i2c@11d02000           /soc/mmc@11230000           /soc/mmc@11240000           !/soc/serial@11001100          cpus                         +       cpu@0           )cpu           arm,cortex-a55          5            9psci            G               [ec3@        k  4        ~                            @                                 @                                                             cpu@100         )cpu           arm,cortex-a55          5           9psci            G               [ec3@        k  4        ~                            @                                 @                                                             cpu@200         )cpu           arm,cortex-a55          5           9psci            G               [ec3@        k  4        ~                            @                                 @                                                             cpu@300         )cpu           arm,cortex-a55          5           9psci            G               [ec3@        k  4        ~                            @                                 @                                                             cpu@400         )cpu           arm,cortex-a78          5           9psci            G              [f        k           ~                            @                                 @                      	                      
                 cpu@500         )cpu           arm,cortex-a78          5           9psci            G              [f        k           ~                            @                                 @                      	                      
                 cpu@600         )cpu           arm,cortex-a78          5           9psci            G              [f        k           ~                            @                                 @                      	                      
                 cpu@700         )cpu           arm,cortex-a78          5           9psci            G              [f        k           ~                            @                                 @                      	                      
                 cpu-map    cluster0       core0                    core1                    core2                    core3                    core4                    core5                    core6                    core7                          idle-states         psci       cpu-retention-l           arm,idle-state          *           A        R   2        c   _        s  D                 cpu-retention-b           arm,idle-state          *           A        R   -        c           s                   cpu-off-l             arm,idle-state          *          A        R   7        c           s  H                 cpu-off-b             arm,idle-state          *          A        R   2        c           s                      l2-cache0             cache                                    @                                                l2-cache1             cache                                    @                                          	      l3-cache              cache                                     @                                        dsu-pmu           arm,dsu-pmu                                                                fail          dmic-codec            dmic-codec                        2      mt8195-sound                       okay                     }  DL10_FE DPTX_BE ETDM1_IN_BE ETDM2_IN_BE ETDM1_OUT_BE ETDM2_OUT_BE UL_SRC1_BE AFE_SOF_DL2 AFE_SOF_DL3 AFE_SOF_UL4 AFE_SOF_UL5            default                  ?  Headphone HPOL Headphone HPOR IN1P Headset Mic Ext Spk Speaker        %    mediatek,mt8195_mt6359_rt1019_rt5682             7mt8195_r1019_5682      mm-dai-link         *ETDM1_IN_BE         4cpu       hs-playback-dai-link            *ETDM1_OUT_BE            4cpu    codec           J                hs-capture-dai-link         *ETDM2_IN_BE         4cpu    codec           J                spk-playback-dai-link           *ETDM2_OUT_BE            4cpu    codec           J            displayport-dai-link            *DPTX_BE    codec           J               fixed-factor-clock-13m            fixed-factor-clock          T            a           h           r           }clk13m             2      oscillator-26m            fixed-clock         T            [        }clk26m                   oscillator-32k            fixed-clock         T            [           }clk32k        performance-controller@11bc10             mediatek,cpufreq-hw          5                 0                                   opp-table-gpu             operating-points-v2                     }   opp-390000000               >         	h      opp-410000000               p         	      opp-431000000                        	      opp-473000000               1h@         	<      opp-515000000               F         	<      opp-556000000               !#          	Ҧ      opp-598000000               #         	      opp-640000000               &%          	      opp-670000000               'c         
      opp-700000000               )'          
L      opp-730000000               +         
}      opp-760000000               -L          
`      opp-790000000               /q         
4      opp-820000000               05                opp-850000000               2         @      opp-880000000               4s          q         pmu-a55           arm,cortex-a55-pmu                                        pmu-a78           arm,cortex-a78-pmu                                        psci              arm,psci-1.0            @smc       timer             arm,armv8-timer                   @                                               
             soc                      +             simple-bus                                             interrupt-controller@c000000              arm,gic-v3                                                      5                                          	                              ppi-partitions     interrupt-partition-0           9                             interrupt-partition-1           9                                   syscon@10000000            mediatek,mt8195-topckgen syscon         5                      T              !      syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          5                     T           B              "      syscon@10003000           mediatek,mt8195-pericfg syscon          5     0                T              H      pinctrl@10005000              mediatek,mt8195-pinctrl         5     P                                                                                                         B  Oiocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            Y        i           u                                                                         default                 >  I2S_SPKR_MCLK I2S_SPKR_DATAIN I2S_SPKR_LRCK I2S_SPKR_BCLK EC_AP_INT_ODL AP_FLASH_WP_L TCHPAD_INT_ODL EDP_HPD_1V8 AP_I2C_CAM_SDA AP_I2C_CAM_SCL AP_I2C_TCHPAD_SDA_1V8 AP_I2C_TCHPAD_SCL_1V8 AP_I2C_AUD_SDA AP_I2C_AUD_SCL AP_I2C_TPM_SDA_1V8 AP_I2C_TPM_SCL_1V8 AP_I2C_TCHSCR_SDA_1V8 AP_I2C_TCHSCR_SCL_1V8 EC_AP_HPD_OD  PCIE_NVME_RST_L PCIE_NVME_CLKREQ_ODL PCIE_RST_1V8_L PCIE_CLKREQ_1V8_ODL PCIE_WAKE_1V8_ODL CLK_24M_CAM0 CAM1_SEN_EN AP_I2C_PWR_SCL_1V8 AP_I2C_PWR_SDA_1V8 AP_I2C_MISC_SCL AP_I2C_MISC_SDA EN_PP5000_HDMI_X AP_HDMITX_HTPLG  AP_HDMITX_SCL_1V8 AP_HDMITX_SDA_1V8 AP_RTC_CLK32K AP_EC_WATCHDOG_L SRCLKENA0 SRCLKENA1 PWRAP_SPI0_CS_L PWRAP_SPI0_CK PWRAP_SPI0_MOSI PWRAP_SPI0_MISO SPMI_SCL SPMI_SDA    I2S_HP_DATAIN I2S_HP_MCLK I2S_HP_BCK I2S_HP_LRCK I2S_HP_DATAOUT SD_CD_ODL EN_PP3300_DISP_X TCHSCR_RST_1V8_L TCHSCR_REPORT_DISABLE EN_PP3300_WLAN_X BT_KILL_1V8_L I2S_SPKR_DATAOUT WIFI_KILL_1V8_L BEEP_ON SCP_I2C_SENSOR_SCL_1V8 SCP_I2C_SENSOR_SDA_1V8     AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1 AUD_DAT_MISO2 SCP_VREQ_VAO AP_SPI_GSC_TPM_CLK AP_SPI_GSC_TPM_MOSI AP_SPI_GSC_TPM_CS_L AP_SPI_GSC_TPM_MISO EN_PP1000_CAM_X AP_EDP_BKLTEN  USB3_HUB_RST_L  WLAN_ALERT_ODL EC_IN_RW_ODL GSC_AP_INT_ODL HP_INT_ODL CAM0_RST_L CAM1_RST_L TCHSCR_INT_1V8_L CAM1_DET_L RST_ALC1011_L   BL_PWM_1V8 UART_AP_TX_DBG_RX UART_DBG_TX_AP_RX EN_SPKR AP_EC_WARM_RST_REQ UART_SCP_TX_DBGCON_RX UART_DBGCON_TX_SCP_RX   KPCOL0  MT6315_GPU_INT MT6315_PROC_BC_INT SD_CMD SD_CLK SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 EMMC_DAT7 EMMC_DAT6 EMMC_DAT5 EMMC_DAT4 EMMC_RSTB EMMC_CMD EMMC_CLK EMMC_DAT3 EMMC_DAT2 EMMC_DAT1 EMMC_DAT0 EMMC_DSL   MT6360_INT_ODL SCP_JTAG0_TRSTN AP_SPI_EC_CS_L AP_SPI_EC_CLK AP_SPI_EC_MOSI AP_SPI_EC_MISO SCP_JTAG0_TMS SCP_JTAG0_TCK SCP_JTAG0_TDO SCP_JTAG0_TDI AP_SPI_FLASH_CS_L AP_SPI_FLASH_CLK AP_SPI_FLASH_MOSI AP_SPI_FLASH_MISO                 audio-default-pins                pins-cmd-dat          D    E  F  G  H  I  J  K           <  1  2  3  4  5      pins-hp-jack-int-odl              Y                     e         cr50-irq-default-pins              l   pins-gsc-ap-int-odl           X                   cros-ec-irq-default-pins               >   pins-ec-ap-int-odl                        e                  edptx-default-pins                pins-cmd-dat                                disp-pwm0-default-pins             B   pins-disp-pwm             R   a         dptx-default-pins                 pins-cmd-dat                                i2c0-default-pins              c   pins-bus                	                            i2c1-default-pins              d   pins-bus              
                               i2c2-default-pins              g   pins-bus                                            i2c3-default-pins              k   pins-bus                                             i2c4-default-pins              m   pins-bus                                              i2c5-default-pins              _   pins-bus                                            i2c7-default-pins              `   pins-bus                                  mmc0-default-pins              K   pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                               e      pins-clk              z                   
   f      pins-rst              x                      e         mmc0-uhs-pins              L   pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                               e      pins-clk              z                   
   f      pins-ds                              
   f      pins-rst              x                      e         mmc1-detect-pins               P   pins-insert           6                   mmc1-default-pins              O   pins-cmd-dat              n  p  q  r  s                               e      pins-clk              o                   
   f         nor-default-pins               ]   pins-ck-io                                    
      pins-cs                                        pcie0-default-pins     pins-bus                                    pcie1-default-pins             \   pins-bus                                    panel-pwr-default-pins                pins-vreg-en              7          pio-default-pins                  pins-wifi-enable              :                           pins-low-power-pd         ,          .   /   0   A   B   C   D                         
      pins-low-power-pupd       <    M   N   O   P   S   U   Z   [   ]   ^   _   `   h   i   k                  
   e         rt1019p-default-pins                  pins-amp-sdb              d          %         scp-default-pins               4   pins-vreq             L                           spi0-default-pins              =   pins-cs-mosi-clk                                 pins-miso                      
         subpmic-default-pins               a   pins-subpmic-int-n                                        trackpad-default-pins              e   pins-int-n                                        touchscreen-default-pins               n   pins-int-n            \                     e      pins-rst              8                pins-report-sw            9          %            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            5     `           power-controller          !    mediatek,mt8195-power-controller                         +            0              6   power-domain@8          5                        +            0           D      power-domain@9          5   	        a          !           Rmfg alt         ^   "                     +            0           D   #   power-domain@10         5   
        0          power-domain@11         5           0          power-domain@12         5           0          power-domain@13         5           0          power-domain@14         5           0                power-domain@15         5           a   !      !      !      !   	   !   @   !   A   !   K   !      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $           Rvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           ^   "                     +            0      power-domain@16         5         8  a   !      %   $   %   %   %   &   %   '   %   (   %   )      D  Rvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         ^   "                     +            0      power-domain@17         5           a   !      &      &           Rvppsys1 vppsys1-0 vppsys1-1         ^   "        0          power-domain@22         5            a   '      '      '      '         $  Rwepsys-0 wepsys-1 wepsys-2 wepsys-3         ^   "        0          power-domain@23         5           a   (            Rvdec0-0         ^   "                     +            0       power-domain@24         5           a   )            Rvdec1-0         ^   "        0          power-domain@25         5           a   *            Rvdec2-0         ^   "        0             power-domain@26         5           a   +            Rvenc0-larb          ^   "                     +            0       power-domain@27         5           a   ,            Rvenc1-larb          ^   "        0             power-domain@18         5            a   !      -       -      -         &  Rvdosys1 vdosys1-0 vdosys1-1 vdosys1-2           ^   "                     +            0      power-domain@19         5           ^   "        0          power-domain@20         5           ^   "        0          power-domain@21         5           a   !   Q        Rhdmi_tx         0             power-domain@28         5           a   .       .   
        Rimg-0 img-1         ^   "                     +            0      power-domain@29         5           0          power-domain@30         5           a   !      .      /           Ripe ipe-0 ipe-1         ^   "        0             power-domain@31         5         (  a   0       0      0      0      0           Rcam-0 cam-1 cam-2 cam-3 cam-4           ^   "                     +            0      power-domain@32         5            0          power-domain@33         5   !        0          power-domain@34         5   "        0                   power-domain@0          5            ^   "        0          power-domain@1          5           ^   "        0          power-domain@2          5           0          power-domain@3          5           0          power-domain@4          5           a   !   5   !   7        Rcsi_rx_top csi_rx_top1          0          power-domain@5          5           a   1           Rether           0          power-domain@6          5           a   !   X   !   n        Radsp adsp1                       +            ^   "        0      power-domain@7          5            a   !   g   !   "   !   n   "   2        Raudio audio1 audio2 audio3          ^   "        0                   watchdog@10007000             mediatek,mt8195-wdt         5     p                B              ;      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           5                     T                     timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         5    p                      	               a   2      pwrap@10024000            mediatek,mt8195-pwrap syscon            5    @                Opwrap                                 a   "      "          	  Rspi wrap            p   !   $           !      pmic              mediatek,mt6359                                                    adc           mediatek,mt6359-auxadc                   audio-codec           mediatek,mt6359-codec                               regulators            mediatek,mt6359-regulator      buck_vs1            vs1          5          !        4             P      buck_vgpu11         vgpu11                    7        d          4           y                   P      buck_vmodem         vmodem                            d  *        4         buck_vpu            vpu                   7        d          4           y                   P      buck_vcore          vcore                              d          4           y                   P                 buck_vs2            vs2          5          j         4             P      buck_vpa            vpa                    7        4  ,      buck_vproc2         vproc2                    7        d  L        4           y                buck_vproc1         vproc1                    7        d  L        4           y                buck_vcore_sshub            vcore_sshub                   7      buck_vgpu11_sshub           vgpu11_sshub             dp         dp         P      ldo_vaud18          vaud18           w@         w@        4         ldo_vsim1           vsim1                     /M`      ldo_vibr            vibr             O         2Z      ldo_vrf12           vrf12                               P      ldo_vusb            vusb             -         -        4           P           I      ldo_vsram_proc2         vsram_proc2                            d  L        4            P      ldo_vio18           vio18                             4           P           h      ldo_vcamio          vcamio                          ldo_vcn18           vcn18            w@         w@        4         ldo_vfe28           vfe28            *         *        4   x      ldo_vcn13           vcn13                            ldo_vcn33_1_bt          vcn33_1_bt           *         5g      ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g      ldo_vaux18          vaux18           w@         w@        4            P      ldo_vsram_others            vsram_others             q         q        d          4              #      ldo_vefuse          vefuse                          ldo_vxo22           vxo22            w@         !         P      ldo_vrfck           vrfck            `               ldo_vrfck_1         vrfck                     j       ldo_vbif28          vbif28           *         *        4         ldo_vio28           vio28            *         2Z         P      ldo_vemc            vemc             ,@          2Z      ldo_vemc_1          vemc             &%         2Z           M      ldo_vcn33_2_bt          vcn33_2_bt           *         5g      ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g      ldo_va12            va12             O                   P      ldo_va09            va09             5          O      ldo_vrf18           vrf18                     P      ldo_vsram_md          	  vsram_md                               d  *        4         ldo_vufs            vufs                               P           N      ldo_vm18            vm18                               P      ldo_vbbck           vbbck                     O      ldo_vsram_proc1         vsram_proc1                            d  L        4            P      ldo_vsim2           vsim2                     /M`      ldo_vsram_others_sshub          vsram_others_sshub                              rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi             5    p                            Opmif spmimst            a   "      "       !   E      (  Rpmif_sys_ck pmif_tmr_ck spmimst_clk_mux         p   !   $           !                        +       mt6315@6              mediatek,mt6315-regulator           5          regulators     vbuck1          Vbcpu                     7        4           d  j        y                   P           
            mt6315@7              mediatek,mt6315-regulator           5          regulators     vbuck1          Vgpu                      7        4           d  j        y                                    infra-iommu@10315000              mediatek,mt8195-iommu-infra         5    1P       P       P                                                                                         W      mailbox@10320000              mediatek,mt8195-gce         5    2        @                                          a   "                    mailbox@10330000              mediatek,mt8195-gce         5    3        @                                          a   "              ~      scp@10500000              mediatek,mt8195-scp       0  5    P             r             p                 Osram cfg l1tcm                               okay            mediatek/mt8195/scp.img            3        default            4              cros-ec-rpmsg             google,cros-ec-rpmsg            cros-ec-rpmsg            clock-controller@10720000             mediatek,mt8195-scp_adsp            5    r                 T              5      dsp@10803000              mediatek,mt8195-dsp          5    0                           	  Ocfg sram          ,  a   !   X      !   n   !      5       !   #      K  Radsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             6           rx tx              7   8        okay               9   :                 mailbox@10816000              mediatek,mt8195-adsp-mbox                       5    `                                        7      mailbox@10817000              mediatek,mt8195-adsp-mbox                       5    p                                        8      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           5                        !           6                 6                  ;         	  audiosys            a                    !      !      !      !      !      !   g   !   "   !   #   !   n   !   e   !   a   !   b   !   c   !   d   "   2   5            Rclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp          okay                       ?               <                 serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           5                                           a      "         	  Rbaud bus            okay          serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           5                                           a      "         	  Rbaud bus          	  disabled          serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           5                                           a      "         	  Rbaud bus          	  disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           5                                          a      "         	  Rbaud bus          	  disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           5                                          a      "         	  Rbaud bus          	  disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           5                                          a      "         	  Rbaud bus          	  disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           5                      a   "           Rmain                       okay                     syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           5     0                T              1      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            5                                           a   !      !      "           Rparent-clk sel-clk spi-clk          okay            default            =        `       ec@0                         +              google,cros-ec-spi          5                             default            >        t -            i2c-tunnel            google,cros-ec-i2c-tunnel                                    +       sbs-battery@b             sbs,sbs-battery         5                                  regulator@0           google,cros-ec-regulator            5            mt_pmic_vmc_ldo          O         6           R      regulator@1           google,cros-ec-regulator            5           mt_pmic_vmch_ldo             )2         6           Q      typec             google,cros-ec-typec                         +       connector@0           usb-c-connector         5            dual            host            source        connector@1           usb-c-connector         5           dual            host            source           keyboard-controller           google,cros-ec-keyb                                     D  0   t x c  	 q	 r  s  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	  + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      4  =               	  	                        thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         5                                           a   "              "            R   ?   @      $  ^lvts-calib-data-1 lvts-calib-data-2         o                    svs@1100bc00              mediatek,mt8195-svs         5                                           a   "           Rmain            R   A   ?      (  ^svs-calibration-data t-calibration-data            "           svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           5                                              6                      a   !   *   "   0        Rmain mm         okay            default            B                 pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           5                                                     a   !   +   "   N        Rmain mm       	  disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            5                                           a   !      !      "   3        Rparent-clk sel-clk spi-clk        	  disabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            5                                           a   !      !      "   4        Rparent-clk sel-clk spi-clk        	  disabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            5    0                                      a   !      !      "   5        Rparent-clk sel-clk spi-clk        	  disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            5                                          a   !      !      "   <        Rparent-clk sel-clk spi-clk        	  disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            5                                          a   !      !      "   =        Rparent-clk sel-clk spi-clk        	  disabled          spi@1101d000              mediatek,mt8195-spi-slave           5                                          a   "   R        Rspi         p   !              !         	  disabled          spi@1101e000              mediatek,mt8195-spi-slave           5                                          a   "   S        Rspi         p   !              !         	  disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           5           @                              macirq        .  Raxi apb mac_main ptp_ref rmii_internal mac_cg         0  a   1       1      !   R   !   S   !   T   1           p   !   R   !   S   !   T           !      !      !              6              "           C           D           E                                        	  disabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config           	
           	           	*                                    C      rx-queues-config            	4            	J           D   queue0           	[        	n          queue1           	[        	n          queue2           	[        	n          queue3           	[        	n             tx-queues-config            	            	           E   queue0          	            	[        	          queue1          	            	[        	         queue2          	            	[        	         queue3          	            	[        	               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           5            -     >              	  Omac ippc                                 ?                      +                                 a   "   /   !      "   B        Rsys_ck ref_ck mcu_ck            	   F      G                    	   H      g        okay            	host            	   I   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          5                       Omac                               p   !   ,   !   -           !      !         $  a   "   /   !                "   B      $  Rsys_ck ref_ck mcu_ck dma_ck xhci_ck         okay            	           
   J         mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          5    #                                                    a   !      "      "           Rsource hclk source_cg           okay            
            
         
0        
A L        x          
P         
_         
n         
v         
|        default state_uhs              K        
   L        
   M        
   N      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          5    $                                                    a   !      "      "   $        Rsource hclk source_cg           p   !              !           okay            
            
        
      6           x          
         
n        default state_uhs              O   P        
   O         
         
        
   Q        
   R      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          5    %                                                    a   !       "      "   I        Rsource hclk source_cg           p   !               !         	  disabled          ufshci@11270000           mediatek,mt8195-ufshci          5    '        #                               	   S      @  a   "   ?   "   @   "   A   "   6   "   7   "   8   "   Z   "   ]      X  Rufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @  
                                                                         
      	  disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            5    '                                      a   "              "           R   ?   @      $  ^lvts-calib-data-1 lvts-calib-data-2         o                    usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           5    )             )>              	  Omac ippc                                 	   T           p   !   .   !   /           !      !         $  a   1      !                1         $  Rsys_ck ref_ck mcu_ck dma_ck xhci_ck         	   H      h                 okay            	           	   I        
   J                 usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           5    *       -    *>              	  Omac ippc                        *        ?                      +                                p   !   0           !           a   1      !      1           Rsys_ck ref_ck mcu_ck            	   U                    	   H      i        okay            	host            	   I   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          5                       Omac                              p   !   1           !           a   1           Rsys_ck          okay            
   J         usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           5    +       -    +>              	  Omac ippc                        +        ?                      +                                p   !   2           !           a   1      !      1   	        Rsys_ck ref_ck mcu_ck            	   V                    	   H      j        okay            	host            	   I   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          5                       Omac                              p   !   3           !           a   1   	        Rsys_ck          okay             %        
   J         pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           )pci                      +           5    /        @       	  Opcie-mac                                 6             8  ʁ                                                            @       W              J          0  a   "   V   "   #   "   &   "   +   "   K   1         /  Rpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          p   !   G           !           	   X      	  Ypcie-phy               6                       c                     `  v                  Y                      Y                     Y                     Y         	  disabled       interrupt-controller                                                Y         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           )pci                      +           5    /       @       	  Opcie-mac                                 6             8  ʁ       $       $                  $       $                 @       W              J          (  a   "   W      "   X      "   Q   1         /  Rpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          p   !   H           !           	   Z         	  Ypcie-phy               6                      c                     `  v                  [                      [                     [                     [           okay            default            \   interrupt-controller                                                [         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         5    2                      9               a   !   o   1      1           Rspi sf axi                       +            okay            default            ]   flash@0           jedec,spi-nor           5            tu                                efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            5                                  +      usb3-tx-imp@184,1           5                               t      usb3-rx-imp@184,2           5                              s      usb3-intr@185           5                              r      usb3-tx-imp@186,1           5                               q      usb3-rx-imp@186,2           5                              p      usb3-intr@187           5                              o      usb2-intr-p0@188,1          5                          usb2-intr-p1@188,2          5                         usb2-intr-p2@189,1          5                         usb2-intr-p3@189,2          5                         pciephy-rx-ln1@190,1            5                               {      pciephy-tx-ln1-nmos@190,2           5                              z      pciephy-tx-ln1-pmos@191,1           5                               y      pciephy-rx-ln0@191,2            5                              x      pciephy-tx-ln0-nmos@192,1           5                               w      pciephy-tx-ln0-pmos@192,2           5                              v      pciephy-glb-intr@193            5                               u      dp-data@1ac         5                      lvts1-calib@1bc         5                ?      lvts2-calib@1d0         5     8           @      svs-calib@580           5     d           A      socinfo-data1@7a0           5              t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0           5               a   !           Rref                       U         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0           5               a   !           Rref                       V         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         5                     a           }mipi_tx0_pll            T                      	  disabled                     dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         5                     a           }mipi_tx1_pll            T                      	  disabled                     i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          5                 "                                     h           a   ^       "   ;      	  Rmain dma                         +            okay            [         default            _      i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          5                "                                      h           a   ^      "   ;      	  Rmain dma                         +          	  disabled          i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          5                 "                                     h           a   ^      "   ;      	  Rmain dma                         +            okay            [         default            `   pmic@34                      mediatek,mt6360         5   4                                  IRQB            default            a                  clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          5    0                T              ^      hdmi-phy@11d5f000             mediatek,mt8195-hdmi-phy            5                     a   !   P   "                         Rpll_ref 26m pll1 pll2           }hdmi_txpll          T                           
                 	  disabled                     i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          5                 "                                      h           a   b       "   ;      	  Rmain dma                         +            okay            [         default            c      i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          5                "                                      h           a   b      "   ;      	  Rmain dma                         +            okay            [           0        default            d   trackpad@15           elan,ekth3000           5                            default            e           f                  i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          5                 "                                     h           a   b      "   ;      	  Rmain dma                         +            okay            [         default            g   codec@1a            5                 Y                                    h           h        $   i        2   h          realtek,rt5682i         A           V   j                    i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          5    0            "                                     h           a   b      "   ;      	  Rmain dma                         +            okay            [         default            k   tpm@50            google,cr50         5   P              X           default            l         i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          5    @            "                                      h           a   b      "   ;      	  Rmain dma                         +            okay            [         default            m   touchscreen@10            hid-over-i2c            5           b                 \           default            n        q   
           f        okay             clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          5    P                T              b      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                   6           okay       usb-phy@0           5               a   !              Rref da_ref                        T      usb-phy@700         5              a          !           Rref da_ref          R   o   p   q        ^intr rx_imp tx_imp                        Z         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0           5               a   !              Rref da_ref                        F      usb-phy@700         5              a          !           Rref da_ref          R   r   s   t        ^intr rx_imp tx_imp                        G         phy@11e80000              mediatek,mt8195-pcie-phy            5                     Osif         R   u   v   w   x   y   z   {      G  ^glb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1             6                     	  disabled               X      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           5                     a            
  Runipro mp                     	  disabled               S      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           5             @         a   |          0                                                 job mmu gpu            }      (     6   
   6      6      6      6           core0 core1 core2 core3 core4           okay                     clock-controller@13fbf000             mediatek,mt8195-mfgcfg          5                    T              |      syscon@14000000           mediatek,mt8195-vppsys0 syscon          5                      T              ~                      $      dma-controller@14001000           mediatek,mt8195-mdp3-rdma           5                        ~                                              6                         a   $         <     ~         ~         ~         ~         ~                       display@14002000              mediatek,mt8195-mdp3-fg         5                         ~                   a   $          display@14003000              mediatek,mt8195-mdp3-stitch         5     0                   ~      0            a   $         display@14004000              mediatek,mt8195-mdp3-hdr            5     @                   ~      @            a   $   "      display@14005000              mediatek,mt8195-mdp3-aal            5     P                      F                  ~      P            a   $   
           6         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           5     `                   ~      `                %        a   $         display@14007000              mediatek,mt8195-mdp3-tdshp          5     p                   ~      p            a   $   #      display@14008000              mediatek,mt8195-mdp3-color          5                           I                  ~                  a   $   $           6         display@14009000              mediatek,mt8195-mdp3-ovl            5                           J                  ~                  a   $   %           6                       display@1400a000              mediatek,mt8195-mdp3-padding            5                        ~                  a   $              6         display@1400b000              mediatek,mt8195-mdp3-tcc            5                        ~                  a   $         dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         5                        ~                      +        a   $                            6                    mutex@1400f000            mediatek,mt8195-vpp-mutex           5                           P                  ~                  a   $              6         smi@14010000              mediatek,mt8195-smi-sub-common          5                     a   $      $      $           Rapb smi gals0                         6                    smi@14011000              mediatek,mt8195-smi-sub-common          5                    a   $      $      $           Rapb smi gals0                         6                    smi@14012000              mediatek,mt8195-smi-common-vpp          5                      a   $      $      $      $           Rapb smi gals0 gals1            6                    larb@14013000             mediatek,mt8195-smi-larb            5    0                                      a   $      $           Rapb smi            6                    iommu@14018000            mediatek,mt8195-iommu-vpp           5                  8  /                                                        R               a   $           Rbclk                          6                    clock-controller@14e00000             mediatek,mt8195-wpesys          5                     T              '      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         5                     T         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         5    0                T         larb@14e04000             mediatek,mt8195-smi-larb            5    @                                      a   '      '           Rapb smi            6                    larb@14e05000             mediatek,mt8195-smi-larb            5    P                                      a   '      '      $           Rapb smi gals               6                    syscon@14f00000           mediatek,mt8195-vppsys1 syscon          5                     T              ~   	                  &      mutex@14f01000            mediatek,mt8195-vpp-mutex           5                          {                  ~   	              a   &   '           6         larb@14f02000             mediatek,mt8195-smi-larb            5                                           a   &      &      $           Rapb smi gals               6                    larb@14f03000             mediatek,mt8195-smi-larb            5    0                                      a   &      &      $           Rapb smi gals               6                    display@14f06000              mediatek,mt8195-mdp3-split          5    `                   ~   	  `            a   &      &   +   &   ,           6         display@14f07000              mediatek,mt8195-mdp3-tcc            5    p                   ~   	  p            a   &         dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           5                       ~   	                          a   &                            6                    dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           5                       ~   	                          a   &   
                         6                    dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           5                       ~   	                          a   &                            6                    display@14f0b000              mediatek,mt8195-mdp3-fg         5                       ~   	              a   &   	      display@14f0c000              mediatek,mt8195-mdp3-fg         5                       ~   	              a   &         display@14f0d000              mediatek,mt8195-mdp3-fg         5                       ~   	              a   &         display@14f0e000              mediatek,mt8195-mdp3-hdr            5                       ~   	              a   &         display@14f0f000              mediatek,mt8195-mdp3-hdr            5                       ~   	              a   &         display@14f10000              mediatek,mt8195-mdp3-hdr            5                        ~   
               a   &          display@14f11000              mediatek,mt8195-mdp3-aal            5                          i                  ~   
              a   &              6         display@14f12000              mediatek,mt8195-mdp3-aal            5                           j                  ~   
               a   &              6         display@14f13000              mediatek,mt8195-mdp3-aal            5    0                      k                  ~   
  0            a   &   !           6         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           5    @                   ~   
  @                        a   &         display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           5    P                   ~   
  P                        a   &   $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           5    `                   ~   
  `                        a   &   %      display@14f17000              mediatek,mt8195-mdp3-tdshp          5    p                   ~   
  p            a   &         display@14f18000              mediatek,mt8195-mdp3-tdshp          5                       ~   
              a   &   (      display@14f19000              mediatek,mt8195-mdp3-tdshp          5                       ~   
              a   &   )      display@14f1a000              mediatek,mt8195-mdp3-merge          5                       ~   
              a   &              6         display@14f1b000              mediatek,mt8195-mdp3-merge          5                       ~   
              a   &              6         display@14f1c000              mediatek,mt8195-mdp3-color          5                          t                  ~   
              a   &              6         display@14f1d000              mediatek,mt8195-mdp3-color          5                       ~   
                    u               a   &              6         display@14f1e000              mediatek,mt8195-mdp3-color          5                          v                  ~   
              a   &              6         display@14f1f000              mediatek,mt8195-mdp3-ovl            5                          w                  ~   
              a   &               6                       display@14f20000              mediatek,mt8195-mdp3-padding            5                        ~                  a   &              6         display@14f21000              mediatek,mt8195-mdp3-padding            5                       ~                 a   &              6         display@14f22000              mediatek,mt8195-mdp3-padding            5                        ~                  a   &              6         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         5    0                   ~     0                        a   &                            6                    dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         5    @                   ~     @                        a   &                            6                    dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         5    P                   ~     P                        a   &                            6                    clock-controller@15000000             mediatek,mt8195-imgsys          5                      T              .      larb@15001000             mediatek,mt8195-smi-larb            5                        	                   a   .       .       .   
        Rapb smi gals               6                    smi@15002000              mediatek,mt8195-smi-sub-common          5                      a   .      .      $           Rapb smi gals0                         6                    smi@15003000              mediatek,mt8195-smi-sub-common          5     0                a   .       .       .   
        Rapb smi gals0                         6                    clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         5                     T                    larb@15120000             mediatek,mt8195-smi-larb            5                        
                   a   .                  Rapb smi            6                    clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          5                     T         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         5    "                 T                    larb@15230000             mediatek,mt8195-smi-larb            5    #                                       a   .                  Rapb smi            6                    clock-controller@15330000             mediatek,mt8195-ipesys          5    3                 T              /      larb@15340000             mediatek,mt8195-smi-larb            5    4                                       a   /      /           Rapb smi            6                    clock-controller@16000000             mediatek,mt8195-camsys          5                      T              0      larb@16001000             mediatek,mt8195-smi-larb            5                                           a   0       0       0           Rapb smi gals               6                    larb@16002000             mediatek,mt8195-smi-larb            5                                            a   0      0           Rapb smi            6                    smi@16004000              mediatek,mt8195-smi-sub-common          5     @                a   0       0       0           Rapb smi gals0                         6                    smi@16005000              mediatek,mt8195-smi-sub-common          5     P                a   0      0      $           Rapb smi gals0                         6                    larb@16012000             mediatek,mt8195-smi-larb            5                                           a                      Rapb smi            6                     larb@16013000             mediatek,mt8195-smi-larb            5    0                                      a                      Rapb smi            6                     larb@16014000             mediatek,mt8195-smi-larb            5    @                                      a                      Rapb smi            6   !                 larb@16015000             mediatek,mt8195-smi-larb            5    P                                      a                      Rapb smi            6   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa         5                    T                    clock-controller@1606f000             mediatek,mt8195-camsys_yuva         5                    T                    clock-controller@1608f000             mediatek,mt8195-camsys_rawb         5                    T                    clock-controller@160af000             mediatek,mt8195-camsys_yuvb         5    
                T                    clock-controller@16140000             mediatek,mt8195-camsys_mraw         5                     T                    larb@16141000             mediatek,mt8195-smi-larb            5                                          a   0              0           Rapb smi gals               6   "                 larb@16142000             mediatek,mt8195-smi-larb            5                                           a                      Rapb smi            6   "                 clock-controller@17200000             mediatek,mt8195-ccusys          5                      T                    larb@17201000             mediatek,mt8195-smi-larb            5                                           a                      Rapb smi            6                    video-codec@18000000              mediatek,mt8195-vcodec-dec                                               +            5                   @                                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         5                                          a   !   A   (      (      !           Rsel vdec lat top            p   !   A           !              6         video-codec@10000             mediatek,mtk-vcodec-lat         5                                         0                                          a   !   A   (      (      !           Rsel vdec lat top            p   !   A           !              6         video-codec@25000             mediatek,mtk-vcodec-core            5     P                                   P                                                             a   !   A   )      )      !           Rsel vdec lat top            p   !   A           !              6            larb@1800d000             mediatek,mt8195-smi-larb            5                                           a   (       (            Rapb smi            6                    larb@1800e000             mediatek,mt8195-smi-larb            5                                           a   $      (            Rapb smi            6                    clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         5                     T              (      larb@1802e000             mediatek,mt8195-smi-larb            5                                          a   )       )            Rapb smi            6                    clock-controller@1802f000             mediatek,mt8195-vdecsys         5                    T              )      larb@1803e000             mediatek,mt8195-smi-larb            5                                          a   $      *            Rapb smi            6                    clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           5                    T              *      clock-controller@190f3000             mediatek,mt8195-apusys_pll          5    0                T         clock-controller@1a000000             mediatek,mt8195-vencsys         5                      T              +      larb@1a010000             mediatek,mt8195-smi-larb            5                                           a   +      +           Rapb smi            6                    video-codec@1a020000              mediatek,mt8195-vcodec-enc          5                   H       `     a     b     c     d     v     w     x     y              U                          a   +         	  Rvenc_sel            p   !   @           !              6                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec             6         0       m     n     r     s     t     u                     +         0                                              jpgdec@0,0            mediatek,mt8195-jpgdec-hw           5                     0       m     n     r     s     t     u              W               a   +           Rjpgdec             6         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw           5                    0       m     n     r     s     t     u              X               a   +           Rjpgdec             6         jpgdec@1,0            mediatek,mt8195-jpgdec-hw           5                    0                                              \               a   ,           Rjpgdec             6            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           5                      T              ,      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            5                                      T                                  %   port                         +       endpoint@0          5            >                          jpeg-encoder@1a030000             mediatek,mt8195-jpgenc             6                                                     +         0                                              jpgenc@0,0            mediatek,mt8195-jpgenc-hw           5                             g     h     i     l              V               a   +           Rjpgenc             6         jpgenc@1,0            mediatek,mt8195-jpgenc-hw           5                                                         [               a   ,           Rjpgenc             6            larb@1b010000             mediatek,mt8195-smi-larb            5                                           a   ,      ,      $            Rapb smi gals               6                    ovl@1c000000              mediatek,mt8195-disp-ovl            5                            |                  6           a   %                                          ports                        +       port@0          5       endpoint            >                       port@1          5      endpoint            >                             rdma@1c002000             mediatek,mt8195-disp-rdma           5                            ~                  6           a   %                                          ports                        +       port@0          5       endpoint            >                       port@1          5      endpoint            >                             color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           5     0                                        6           a   %                   0       ports                        +       port@0          5       endpoint            >                       port@1          5      endpoint            >                             ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           5     @                                        6           a   %                   @       ports                        +       port@0          5       endpoint            >                       port@1          5      endpoint            >                             aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           5     P                                        6           a   %                   P       ports                        +       port@0          5       endpoint            >                       port@1          5      endpoint            >                             gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           5     `                                        6           a   %                   `       ports                        +       port@0          5       endpoint            >                       port@1          5      endpoint            >                             dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         5     p                                        6           a   %   	                p       ports                        +       port@0          5       endpoint            >                       port@1          5      endpoint            >                             dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         5                                             6           a   %      %   *           Rengine digital hs           	           Ydphy          	  disabled          dsc@1c009000              mediatek,mt8195-disp-dsc            5                                             6           a   %                          ports                        +       port@0          5       endpoint            >                       port@1          5      endpoint            >                             dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         5                                             6           a   %      %   +           Rengine digital hs           	           Ydphy          	  disabled          merge@1c014000            mediatek,mt8195-disp-merge          5    @                                        6           a   %                   @       ports                        +       port@0          5       endpoint            >                       port@1          5      endpoint            >                             dp-intf@1c015000              mediatek,mt8195-dp-intf         5    P                                        6           a   %   ,   %                  Rpixel engine pll            okay       ports                        +       port@0          5       endpoint            >                       port@1          5      endpoint            >                             mutex@1c016000            mediatek,mt8195-disp-mutex          5    `                                        6           a   %                   `              U      larb@1c018000             mediatek,mt8195-smi-larb            5                                           a   %   (   %   (   $           Rapb smi gals               6                    larb@1c019000             mediatek,mt8195-smi-larb            5                                          a   %   (   $       $           Rapb smi gals               6                    syscon@1c100000           mediatek,mt8195-vdosys1 syscon          5                                                           T           B              -   port                         +       endpoint@1          5           >                          smi@1c01b000              mediatek,mt8195-smi-common-vdo          5                     a   %   %   %   &   %   )   %   $        Rapb smi gals0 gals1            6                    iommu@1c01f000            mediatek,mt8195-iommu-vdo           5                  8  /                                                                                  a   %   '        Rbclk               6                    mutex@1c101000            mediatek,mt8195-disp-mutex          5                                            6           a   -                                       larb@1c102000             mediatek,mt8195-smi-larb            5                                           a   -       -       -           Rapb smi gals               6                    larb@1c103000             mediatek,mt8195-smi-larb            5    0                                      a   -      -      $            Rapb smi gals               6                    dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           5    @                                     a   -              6                 @                @                     dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           5    P                                     a   -              6                 `                P                     dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           5    `                                     a   -              6                 A                `                     dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           5    p                                     a   -              6                 a                p                     dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           5                                         a   -              6                 B                                     dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           5                                         a   -              6                 b                                     dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           5                                         a   -              6                 C                                     dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           5                                         a   -              6                 c                                     vpp-merge@1c10c000            mediatek,mt8195-disp-merge          5                                         a   -   	   -           Rmerge merge_async              6                                N           -         vpp-merge@1c10d000            mediatek,mt8195-disp-merge          5                                         a   -   
   -           Rmerge merge_async              6                                N           -         vpp-merge@1c10e000            mediatek,mt8195-disp-merge          5                                         a   -      -           Rmerge merge_async              6                                N           -         vpp-merge@1c10f000            mediatek,mt8195-disp-merge          5                                         a   -      -           Rmerge merge_async              6                                N           -         vpp-merge@1c110000            mediatek,mt8195-disp-merge          5                                          a   -      -           Rmerge merge_async              6                                 b           -      ports                        +       port@0                       +            5       endpoint@1          5           >                       port@1                       +            5      endpoint@1          5           >                             dpi@1c112000              mediatek,mt8195-dpi         5                     a   -   -   -      -   2        Rpixel engine pll                                     6              -         	  disabled       ports                        +       port@0          5       endpoint             port@1          5      endpoint                   dp-intf@1c113000              mediatek,mt8195-dp-intf         5    0                                        6           a   -   /   -                  Rpixel engine pll            okay       ports                        +       port@0                       +            5       endpoint@1          5           >                       port@1                       +            5      endpoint@1          5           >                             hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  5    @            P            p                                                              4  Omixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p          @            P            p                                                          h  a   -   %   -       -   #   -   !   -   $   -   "   -   1   -   &   -   '   -   (   -   )   -   *   !           Rmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top             6                 d      e                           (     -   3   -   4   -   5   -   6   -   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async       ports                        +       port@0                       +            5       endpoint@1          5           >                       port@1                       +            5      endpoint@1          5           >                             hdmi-tx@1c300000              mediatek,mt8195-hdmi-tx                    5    0                  a   !   Q   !   L   !   M   &   ,        Rbus hdcp hdcp24m hdmi-split         p   !   L           !                                   6           	           Yhdmi          	  disabled       i2c           mediatek,mt8195-hdmi-ddc            a         ports                        +       port@0          5       endpoint             port@1          5      endpoint                   edp-tx@1c500000           mediatek,mt8195-edp-tx          5    P                 R           ^dp_calibration_data            6                                y          okay            default               ports                        +       port@0          5       endpoint            >                       port@1          5      endpoint                                 >                          aux-bus    panel         
    edp-panel                            port       endpoint            >                                dp-tx@1c600000            mediatek,mt8195-dp-tx           5    `                 R           ^dp_calibration_data            6                                y          okay                        default                          ports                        +       port@0                       +            5       endpoint@1          5           >                       port@1          5      endpoint                                           thermal-zones      cpu0-thermal                                          trips      trip-alert           L                  0passive                  trip-crit                            	  0critical             cooling-maps       map0                     0                          cpu1-thermal                                          trips      trip-alert           L                  0passive                  trip-crit                            	  0critical             cooling-maps       map0                     0                          cpu2-thermal                                          trips      trip-alert           L                  0passive                  trip-crit                            	  0critical             cooling-maps       map0                     0                          cpu3-thermal                                          trips      trip-alert           L                  0passive                  trip-crit                            	  0critical             cooling-maps       map0                     0                          cpu4-thermal                                           trips      trip-alert           L                  0passive                  trip-crit                            	  0critical             cooling-maps       map0                     0                          cpu5-thermal                                          trips      trip-alert           L                  0passive                  trip-crit                            	  0critical             cooling-maps       map0                     0                          cpu6-thermal                                          trips      trip-alert           L                  0passive                  trip-crit                            	  0critical             cooling-maps       map0                     0                          cpu7-thermal                                          trips      trip-alert           L                  0passive                  trip-crit                            	  0critical             cooling-maps       map0                     0                          vpu0-thermal                                          trips      trip-alert           L                  0passive       trip-crit                            	  0critical                vpu1-thermal                                       	   trips      trip-alert           L                  0passive       trip-crit                            	  0critical                gpu-thermal                                    
   trips      trip-alert           L                  0passive       trip-crit                            	  0critical                gpu1-thermal                                          trips      trip-alert           L                  0passive       trip-crit                            	  0critical                vdec-thermal                                          trips      trip-alert           L                  0passive       trip-crit                            	  0critical                img-thermal                                       trips      trip-alert           L                  0passive       trip-crit                            	  0critical                infra-thermal                                         trips      trip-alert           L                  0passive       trip-crit                            	  0critical                cam0-thermal                                          trips      trip-alert           L                  0passive       trip-crit                            	  0critical                cam1-thermal                                          trips      trip-alert           L                  0passive       trip-crit                            	  0critical                soc-area-thermal                                       trips      trip-crit            H                 	  0critical                pmic-area-thermal                                       trips      trip-crit            H                 	  0critical                   backlight-lcd0            pwm-backlight                           @        6      R            C          Z                                     chosen          _serial0:115200n8          memory@40000000         )memory          5    @                regulator-pp3300-disp-x           regulator-fixed         pp3300_disp_x            2Z         2Z        4  	         k        ~      7            default                       i                 regulator-pp3300-ldo-z5           regulator-fixed         pp3300_ldo_z5            P                  2Z         2Z                      j      regulator-pp3300-s3           regulator-fixed       
  pp3300_s3            P                  2Z         2Z           i           f      regulator-pp3300-z2           regulator-fixed       
  pp3300_z2            P                  2Z         2Z                      i      regulator-pp4200-z2           regulator-fixed       
  pp4200_z2            P                  @@         @@                 regulator-pp5000-s5           regulator-fixed       
  pp5000_s5            P                  LK@         LK@                 regulator-ppvar-sys           regulator-fixed       
  ppvar_sys            P                          thermal-sensor-t1             generic-adc-thermal         o                           sensor-channel            x        ~    %  '    :  [  N     a    u0        @  ]      P        `  G     p    $    8    L    _   } s   k    \ (   O    D 8   ;    3 H   ,                 thermal-sensor-t2             generic-adc-thermal         o                          sensor-channel            x        ~    %  '    :  [  N     a    u0        @  ]      P        `  G     p    $    8    L    _   } s   k    \ (   O    D 8   ;    3 H   ,                 regulator-5v0-usb-vbus            regulator-fixed       	  usb-vbus             LK@         LK@         k         P           J      reserved-memory                      +               memory@50000000           shared-dma-pool         5    P                             3      memory@60000000           shared-dma-pool         5    `                              :      memory@60d80000           shared-dma-pool         5    `                             <      memory@60e80000           shared-dma-pool         5    `       (                      9         rt1019p           realtek,rt1019p         rt1019p                     default                          d                        	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dpi1 gce0 gce1 hdmi0 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c7 mmc0 mmc1 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform mediatek,adsp mediatek,dai-link pinctrl-names pinctrl-0 audio-routing link-name mediatek,clk-provider sound-dai #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller mediatek,broken-save-restore-fw affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges mediatek,rsel-resistance-in-si-unit gpio-line-names pinmux input-enable bias-pull-up bias-disable drive-strength-microamp drive-strength bias-pull-down output-high output-low #power-domain-cells domain-supply clock-names mediatek,infracfg assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells mediatek,dmic-mode mediatek,mic-type-0 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells firmware-name memory-region mediatek,rpmsg-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names mediatek,etdm-in2-cowork-source mediatek,etdm-out2-cowork-source mediatek,pad-select spi-max-frequency wakeup-source google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count power-role data-role try-power-role keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys mediatek,syscon-wakeup dr_mode vusb33-supply rx-fifo-depth vbus-supply bus-width cap-mmc-highspeed cap-mmc-hw-reset hs400-ds-delay mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable pinctrl-1 vmmc-supply vqmmc-supply cap-sd-highspeed cd-gpios no-mmc sd-uhs-sdr50 sd-uhs-sdr104 freq-table-hz mediatek,ufs-disable-mcq mediatek,u3p-dis-msk usb2-lpm-disable bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map spi-rx-bus-width spi-tx-bus-width bits #phy-cells mediatek,ibias mediatek,ibias_up i2c-scl-internal-delay-ns vcc-supply realtek,jd-src AVDD-supply DBVDD-supply MICVDD-supply LDO1-IN-supply realtek,btndet-delay VBAT-supply hid-descr-addr post-power-on-delay-ms vdd-supply operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz data-lanes power-supply backlight polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device brightness-levels default-brightness-level enable-gpios num-interpolated-steps pwms stdout-path enable-active-high gpio vin-supply regulator-boot-on io-channels io-channel-names temperature-lookup-table no-map label sdb-gpios 