    8 {   (            % {                             `    google,dojo-sku7 google,dojo-sku5 google,dojo-sku3 google,dojo-sku1 google,dojo mediatek,mt8195                                  +            7HP Dojo (sku 1, 3, 5, 7) board           =convertible    aliases          J/soc/dp-intf@1c015000            S/soc/dp-intf@1c113000            \/soc/dpi@1c112000            a/soc/mailbox@10320000            f/soc/mailbox@10330000            k/soc/hdmi-tx@1c300000            q/soc/hdr-engine@1c114000             x/soc/mutex@1c016000          /soc/mutex@1c101000          /soc/vpp-merge@1c10c000          /soc/vpp-merge@1c10d000          /soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000            /soc/i2c@11e00000           /soc/i2c@11e01000           /soc/i2c@11e02000           /soc/i2c@11e03000           /soc/i2c@11e04000           /soc/i2c@11d00000           /soc/i2c@11d02000           $/soc/mmc@11230000           )/soc/mmc@11240000           ./soc/serial@11001100          cpus                         +       cpu@0           6cpu           arm,cortex-a55          B            Fpsci            T               hec3@        x  4                                    @                                 @                                                             cpu@100         6cpu           arm,cortex-a55          B           Fpsci            T               hec3@        x  4                                    @                                 @                                                             cpu@200         6cpu           arm,cortex-a55          B           Fpsci            T               hec3@        x  4                                    @                                 @                                                             cpu@300         6cpu           arm,cortex-a55          B           Fpsci            T               hec3@        x  4                                    @                                 @                                                             cpu@400         6cpu           arm,cortex-a78          B           Fpsci            T              hf        x                                       @                                 @                      	                      
                 cpu@500         6cpu           arm,cortex-a78          B           Fpsci            T              hf        x                                       @                                 @                      	                      
                 cpu@600         6cpu           arm,cortex-a78          B           Fpsci            T              hf        x                                       @                                 @                      	                      
                 cpu@700         6cpu           arm,cortex-a78          B           Fpsci            T              hf        x                                       @                                 @                      	                      
                 cpu-map    cluster0       core0           &         core1           &         core2           &         core3           &         core4           &         core5           &         core6           &         core7           &               idle-states         *psci       cpu-retention-l           arm,idle-state          7           N        _   2        p   _          D                 cpu-retention-b           arm,idle-state          7           N        _   -        p                              cpu-off-l             arm,idle-state          7          N        _   7        p             H                 cpu-off-b             arm,idle-state          7          N        _   2        p                                 l2-cache0             cache                                    @                                                l2-cache1             cache                                    @                                          	      l3-cache              cache                                     @                                        dsu-pmu           arm,dsu-pmu                                                                fail          dmic-codec            dmic-codec                        2      mt8195-sound                       okay                     }  DL10_FE DPTX_BE ETDM1_IN_BE ETDM2_IN_BE ETDM1_OUT_BE ETDM2_OUT_BE UL_SRC1_BE AFE_SOF_DL2 AFE_SOF_DL3 AFE_SOF_UL4 AFE_SOF_UL5            default                  [  )Headphone HPOL Headphone HPOR IN1P Headset Mic Right Spk Right BE_OUT Left Spk Left BE_OUT        '    mediatek,mt8195_mt6359_max98390_rt5682           7m8195_m98390_5682s     mm-dai-link         7ETDM1_IN_BE         Acpu       hs-playback-dai-link            7ETDM1_OUT_BE            Acpu    codec           W                hs-capture-dai-link         7ETDM2_IN_BE         Acpu    codec           W                spk-playback-dai-link           7ETDM2_OUT_BE            Acpu    codec           W               displayport-dai-link            7DPTX_BE    codec           W               fixed-factor-clock-13m            fixed-factor-clock          a            n           u                      clk13m             3      oscillator-26m            fixed-clock         a            h        clk26m                   oscillator-32k            fixed-clock         a            h           clk32k        performance-controller@11bc10             mediatek,cpufreq-hw          B                 0                                   opp-table-gpu             operating-points-v2                     ~   opp-390000000               >         	h      opp-410000000               p         	      opp-431000000                        	      opp-473000000               1h@         	<      opp-515000000               F         	<      opp-556000000               !#          	Ҧ      opp-598000000               #         	      opp-640000000               &%          	      opp-670000000               'c         
      opp-700000000               )'          
L      opp-730000000               +         
}      opp-760000000               -L          
`      opp-790000000               /q         
4      opp-820000000               05                opp-850000000               2         @      opp-880000000               4s          q         pmu-a55           arm,cortex-a55-pmu                                        pmu-a78           arm,cortex-a78-pmu                                        psci              arm,psci-1.0            Msmc       timer             arm,armv8-timer                   @                                               
             soc                      +             simple-bus                                             interrupt-controller@c000000              arm,gic-v3                                                      B                                          	                &              ppi-partitions     interrupt-partition-0           F                             interrupt-partition-1           F                                   syscon@10000000            mediatek,mt8195-topckgen syscon         B                      a              "      syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          B                     a           O              #      syscon@10003000           mediatek,mt8195-pericfg syscon          B     0                a              I      pinctrl@10005000              mediatek,mt8195-pinctrl         B     P                                                                                                         B  \iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            f        v                                                                                    default                 >  I2S_SPKR_MCLK I2S_SPKR_DATAIN I2S_SPKR_LRCK I2S_SPKR_BCLK EC_AP_INT_ODL AP_FLASH_WP_L TCHPAD_INT_ODL EDP_HPD_1V8 AP_I2C_CAM_SDA AP_I2C_CAM_SCL AP_I2C_TCHPAD_SDA_1V8 AP_I2C_TCHPAD_SCL_1V8 AP_I2C_AUD_SDA AP_I2C_AUD_SCL AP_I2C_TPM_SDA_1V8 AP_I2C_TPM_SCL_1V8 AP_I2C_TCHSCR_SDA_1V8 AP_I2C_TCHSCR_SCL_1V8 EC_AP_HPD_OD  PCIE_NVME_RST_L PCIE_NVME_CLKREQ_ODL PCIE_RST_1V8_L PCIE_CLKREQ_1V8_ODL PCIE_WAKE_1V8_ODL CLK_24M_CAM0 CAM1_SEN_EN AP_I2C_PWR_SCL_1V8 AP_I2C_PWR_SDA_1V8 AP_I2C_MISC_SCL AP_I2C_MISC_SDA EN_PP5000_HDMI_X AP_HDMITX_HTPLG  AP_HDMITX_SCL_1V8 AP_HDMITX_SDA_1V8 AP_RTC_CLK32K AP_EC_WATCHDOG_L SRCLKENA0 SRCLKENA1 PWRAP_SPI0_CS_L PWRAP_SPI0_CK PWRAP_SPI0_MOSI PWRAP_SPI0_MISO SPMI_SCL SPMI_SDA    I2S_HP_DATAIN I2S_HP_MCLK I2S_HP_BCK I2S_HP_LRCK I2S_HP_DATAOUT SD_CD_ODL EN_PP3300_DISP_X TCHSCR_RST_1V8_L TCHSCR_REPORT_DISABLE EN_PP3300_WLAN_X BT_KILL_1V8_L I2S_SPKR_DATAOUT WIFI_KILL_1V8_L BEEP_ON SCP_I2C_SENSOR_SCL_1V8 SCP_I2C_SENSOR_SDA_1V8     AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1 AUD_DAT_MISO2 SCP_VREQ_VAO AP_SPI_GSC_TPM_CLK AP_SPI_GSC_TPM_MOSI AP_SPI_GSC_TPM_CS_L AP_SPI_GSC_TPM_MISO EN_PP1000_CAM_X AP_EDP_BKLTEN  USB3_HUB_RST_L  WLAN_ALERT_ODL EC_IN_RW_ODL GSC_AP_INT_ODL HP_INT_ODL CAM0_RST_L CAM1_RST_L TCHSCR_INT_1V8_L CAM1_DET_L RST_ALC1011_L   BL_PWM_1V8 UART_AP_TX_DBG_RX UART_DBG_TX_AP_RX EN_SPKR AP_EC_WARM_RST_REQ UART_SCP_TX_DBGCON_RX UART_DBGCON_TX_SCP_RX   KPCOL0  MT6315_GPU_INT MT6315_PROC_BC_INT SD_CMD SD_CLK SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 EMMC_DAT7 EMMC_DAT6 EMMC_DAT5 EMMC_DAT4 EMMC_RSTB EMMC_CMD EMMC_CLK EMMC_DAT3 EMMC_DAT2 EMMC_DAT1 EMMC_DAT0 EMMC_DSL   MT6360_INT_ODL SCP_JTAG0_TRSTN AP_SPI_EC_CS_L AP_SPI_EC_CLK AP_SPI_EC_MOSI AP_SPI_EC_MISO SCP_JTAG0_TMS SCP_JTAG0_TCK SCP_JTAG0_TDO SCP_JTAG0_TDI AP_SPI_FLASH_CS_L AP_SPI_FLASH_CLK AP_SPI_FLASH_MOSI AP_SPI_FLASH_MISO                 audio-default-pins                pins-cmd-dat          D    E  F  G  H  I  J  K           <  1  2  3  4  5      pins-hp-jack-int-odl              Y                     e         cr50-irq-default-pins              m   pins-gsc-ap-int-odl           X                   cros-ec-irq-default-pins               ?   pins-ec-ap-int-odl                        e                  edptx-default-pins                pins-cmd-dat                                disp-pwm0-default-pins             C   pins-disp-pwm             R   a         dptx-default-pins                 pins-cmd-dat                                i2c0-default-pins              e   pins-bus                	                            i2c1-default-pins              f   pins-bus              
                               i2c2-default-pins              i   pins-bus                                            i2c3-default-pins              l   pins-bus                                             i2c4-default-pins              n   pins-bus                                              i2c5-default-pins              a   pins-bus                                            i2c7-default-pins              b   pins-bus                                  mmc0-default-pins              L   pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                               e      pins-clk              z                      f      pins-rst              x                      e         mmc0-uhs-pins              M   pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                               e      pins-clk              z                      f      pins-ds                                 f      pins-rst              x                      e         mmc1-detect-pins               Q   pins-insert           6                   mmc1-default-pins              P   pins-cmd-dat              n  p  q  r  s                               e      pins-clk              o                      f         nor-default-pins               _   pins-ck-io                                          pins-cs                                        pcie0-default-pins             [   pins-bus                                    pcie1-default-pins             ^   pins-bus                                    panel-pwr-default-pins                pins-vreg-en              7          pio-default-pins                  pins-wifi-enable              :          &                 pins-low-power-pd         ,          .   /   0   A   B   C   D                               pins-low-power-pupd       <    M   N   O   P   S   U   Z   [   ]   ^   _   `   h   i   k                     e      pins-low-power-hdmi-disable                  !                         pins-low-power-hdmi-rsel-disable              "   #                   $         rt1019p-default-pins                  pins-amp-sdb              d          2         scp-default-pins               5   pins-vreq             L                           spi0-default-pins              >   pins-cs-mosi-clk                                 pins-miso                               subpmic-default-pins               c   pins-subpmic-int-n                                        trackpad-default-pins              g   pins-int-n                                        touchscreen-default-pins               o   pins-int-n            \                     e      pins-rst              8          &      pins-report-sw            9          2            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            B     `           power-controller          !    mediatek,mt8195-power-controller                         +            =              7   power-domain@8          B                        +            =           Q       power-domain@9          B   	        n   !      "           _mfg alt         k   #                     +            =           Q   $   power-domain@10         B   
        =          power-domain@11         B           =          power-domain@12         B           =          power-domain@13         B           =          power-domain@14         B           =                power-domain@15         B           n   "      "      "      "   	   "   @   "   A   "   K   "      %      %      %      %      %      %      %      %      %      %      %      %      %      %      %      %      %      %      %           _vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           k   #                     +            =      power-domain@16         B         8  n   "      &   $   &   %   &   &   &   '   &   (   &   )      D  _vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         k   #                     +            =      power-domain@17         B           n   "      '      '           _vppsys1 vppsys1-0 vppsys1-1         k   #        =          power-domain@22         B            n   (      (      (      (         $  _wepsys-0 wepsys-1 wepsys-2 wepsys-3         k   #        =          power-domain@23         B           n   )            _vdec0-0         k   #                     +            =       power-domain@24         B           n   *            _vdec1-0         k   #        =          power-domain@25         B           n   +            _vdec2-0         k   #        =             power-domain@26         B           n   ,            _venc0-larb          k   #                     +            =       power-domain@27         B           n   -            _venc1-larb          k   #        =             power-domain@18         B            n   "      .       .      .         &  _vdosys1 vdosys1-0 vdosys1-1 vdosys1-2           k   #                     +            =      power-domain@19         B           k   #        =          power-domain@20         B           k   #        =          power-domain@21         B           n   "   Q        _hdmi_tx         =             power-domain@28         B           n   /       /   
        _img-0 img-1         k   #                     +            =      power-domain@29         B           =          power-domain@30         B           n   "      /      0           _ipe ipe-0 ipe-1         k   #        =             power-domain@31         B         (  n   1       1      1      1      1           _cam-0 cam-1 cam-2 cam-3 cam-4           k   #                     +            =      power-domain@32         B            =          power-domain@33         B   !        =          power-domain@34         B   "        =                   power-domain@0          B            k   #        =          power-domain@1          B           k   #        =          power-domain@2          B           =          power-domain@3          B           =          power-domain@4          B           n   "   5   "   7        _csi_rx_top csi_rx_top1          =          power-domain@5          B           n   2           _ether           =          power-domain@6          B           n   "   X   "   n        _adsp adsp1                       +            k   #        =      power-domain@7          B            n   "   g   "   "   "   n   #   2        _audio audio1 audio2 audio3          k   #        =                   watchdog@10007000             mediatek,mt8195-wdt          }        B     p                O              <      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           B                     a              !      timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         B    p                      	               n   3      pwrap@10024000            mediatek,mt8195-pwrap syscon            B    @                \pwrap                                 n   #      #          	  _spi wrap               "   $           "      pmic              mediatek,mt6359                                                    adc           mediatek,mt6359-auxadc                   audio-codec           mediatek,mt6359-codec                               regulators            mediatek,mt6359-regulator      buck_vs1            vs1         ) 5         A !        Y             u      buck_vgpu11         vgpu11          )         A 7                  Y                              u      buck_vmodem         vmodem          )         A           *        Y         buck_vpu            vpu         )         A 7                  Y                              u      buck_vcore          vcore           )         A                    Y                              u                 buck_vs2            vs2         ) 5         A j         Y             u      buck_vpa            vpa         )          A 7        Y  ,      buck_vproc2         vproc2          )         A 7          L        Y                           buck_vproc1         vproc1          )         A 7          L        Y                           buck_vcore_sshub            vcore_sshub         )         A 7      buck_vgpu11_sshub           vgpu11_sshub            ) dp        A dp         u      ldo_vaud18          vaud18          ) w@        A w@        Y         ldo_vsim1           vsim1           )         A /M`      ldo_vibr            vibr            ) O        A 2Z      ldo_vrf12           vrf12           )         A           u      ldo_vusb            vusb            ) -        A -        Y           u           J      ldo_vsram_proc2         vsram_proc2         )          A           L        Y            u      ldo_vio18           vio18           )         A         Y           u           j      ldo_vcamio          vcamio          )         A       ldo_vcn18           vcn18           ) w@        A w@        Y         ldo_vfe28           vfe28           ) *        A *        Y   x      ldo_vcn13           vcn13           )         A        ldo_vcn33_1_bt          vcn33_1_bt          ) *        A 5g      ldo_vcn33_1_wifi            vcn33_1_wifi            ) *        A 5g      ldo_vaux18          vaux18          ) w@        A w@        Y            u      ldo_vsram_others            vsram_others            ) q        A q                  Y              $      ldo_vefuse          vefuse          )         A       ldo_vxo22           vxo22           ) w@        A !         u      ldo_vrfck           vrfck           ) `        A       ldo_vrfck_1         vrfck           )         A j       ldo_vbif28          vbif28          ) *        A *        Y         ldo_vio28           vio28           ) *        A 2Z         u      ldo_vemc            vemc            ) ,@         A 2Z      ldo_vemc_1          vemc            ) &%        A 2Z           N      ldo_vcn33_2_bt          vcn33_2_bt          ) *        A 5g      ldo_vcn33_2_wifi            vcn33_2_wifi            ) *        A 5g      ldo_va12            va12            ) O        A           u      ldo_va09            va09            ) 5         A O      ldo_vrf18           vrf18           )         A P      ldo_vsram_md          	  vsram_md            )          A           *        Y         ldo_vufs            vufs            )         A          u           O      ldo_vm18            vm18            )         A          u      ldo_vbbck           vbbck           )         A O      ldo_vsram_proc1         vsram_proc1         )          A           L        Y            u      ldo_vsim2           vsim2           )         A /M`      ldo_vsram_others_sshub          vsram_others_sshub          )          A          rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi             B    p                            \pmif spmimst            n   #      #       "   E      (  _pmif_sys_ck pmif_tmr_ck spmimst_clk_mux            "   $           "                        +       mt6315@6              mediatek,mt6315-regulator           B          regulators     vbuck1          Vbcpu           )         A 7        Y             j                           u           
            mt6315@7              mediatek,mt6315-regulator           B          regulators     vbuck1          Vgpu            )         A 7        Y             j                                             infra-iommu@10315000              mediatek,mt8195-iommu-infra         B    1P       P       P                                                                                         X      mailbox@10320000              mediatek,mt8195-gce         B    2        @                                          n   #                    mailbox@10330000              mediatek,mt8195-gce         B    3        @                                          n   #                    scp@10500000              mediatek,mt8195-scp       0  B    P             r             p                 \sram cfg l1tcm                               okay            mediatek/mt8195/scp.img            4        default            5              cros-ec-rpmsg             google,cros-ec-rpmsg            cros-ec-rpmsg            clock-controller@10720000             mediatek,mt8195-scp_adsp            B    r                 a              6      dsp@10803000              mediatek,mt8195-dsp          B    0                           	  \cfg sram          ,  n   "   X      "   n   "      6       "   #      K  _adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             7           rx tx              8   9        okay               :   ;                 mailbox@10816000              mediatek,mt8195-adsp-mbox                       B    `                                        8      mailbox@10817000              mediatek,mt8195-adsp-mbox                       B    p                                        9      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           B                        "           7                 6               1   <         	  8audiosys            n      !      !      "      "      "      "      "      "   g   "   "   "   #   "   n   "   e   "   a   "   b   "   c   "   d   #   2   6            _clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp          okay            D           d               =                 serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           B                                           n      #         	  _baud bus            okay          serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           B                                           n      #         	  _baud bus          	  disabled          serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           B                                           n      #         	  _baud bus          	  disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           B                                          n      #         	  _baud bus          	  disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           B                                          n      #         	  _baud bus          	  disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           B                                          n      #         	  _baud bus          	  disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           B                      n   #           _main                       okay                     syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           B     0                a              2      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            B                                           n   "      "      #           _parent-clk sel-clk spi-clk          okay            default            >               ec@0                         +              google,cros-ec-spi          B                             default            ?         -            i2c-tunnel            google,cros-ec-i2c-tunnel                                    +       sbs-battery@b             sbs,sbs-battery         B                                  regulator@0           google,cros-ec-regulator            B            mt_pmic_vmc_ldo         ) O        A 6           S      regulator@1           google,cros-ec-regulator            B           mt_pmic_vmch_ldo            ) )2        A 6           R      typec             google,cros-ec-typec                         +       connector@0           usb-c-connector         B            dual            host            	source        connector@1           usb-c-connector         B           dual            host            	source           keyboard-controller           google,cros-ec-keyb                    (            ;     P  U  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	  + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i   t x c  	 	     q r s      4  b               	  	                        thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         B                                           n   #           1   #            w   @   A      $  lvts-calib-data-1 lvts-calib-data-2                             svs@1100bc00              mediatek,mt8195-svs         B                                           n   #           _main            w   B   @      (  svs-calibration-data t-calibration-data         1   #           8svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           B                                              7                      n   "   *   #   0        _main mm         okay            default            C                 pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           B                                                     n   "   +   #   N        _main mm       	  disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            B                                           n   "      "      #   3        _parent-clk sel-clk spi-clk        	  disabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            B                                           n   "      "      #   4        _parent-clk sel-clk spi-clk        	  disabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            B    0                                      n   "      "      #   5        _parent-clk sel-clk spi-clk        	  disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            B                                          n   "      "      #   <        _parent-clk sel-clk spi-clk        	  disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            B                                          n   "      "      #   =        _parent-clk sel-clk spi-clk        	  disabled          spi@1101d000              mediatek,mt8195-spi-slave           B                                          n   #   R        _spi            "              "         	  disabled          spi@1101e000              mediatek,mt8195-spi-slave           B                                          n   #   S        _spi            "              "         	  disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           B           @                              macirq        .  _axi apb mac_main ptp_ref rmii_internal mac_cg         0  n   2       2      "   R   "   S   "   T   2              "   R   "   S   "   T           "      "      "              7              #           D           E           F        	           	           	"          	  disabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config           	/           	?           	O                                    D      rx-queues-config            	Y            	o           E   queue0           	        	          queue1           	        	          queue2           	        	          queue3           	        	             tx-queues-config            	            	           F   queue0          	            	        	          queue1          	            	        	         queue2          	            	        	         queue3          	            	        	               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           B            -     >              	  \mac ippc                                 ?                      +                                 n   #   /   "      #   B        _sys_ck ref_ck mcu_ck            	   G      H                    	   I      g        okay            
	host            
   J   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          B                       \mac                                  "   ,   "   -           "      "         $  n   #   /   "      !         #   B      $  _sys_ck ref_ck mcu_ck dma_ck xhci_ck         okay            
           
-   K         mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          B    #                                                    n   "      #      #           _source hclk source_cg           okay            
9            
C         
U        
f L                  
u         
         
         
         
        default state_uhs              L        
   M        
   N        
   O      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          B    $                                                    n   "      #      #   $        _source hclk source_cg              "              "           okay            
9            
        
      6                     
         
        default state_uhs              P   Q        
   P         
                  
   R        
   S      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          B    %                                                    n   "       #      #   I        _source hclk source_cg              "               "         	  disabled          ufshci@11270000           mediatek,mt8195-ufshci          B    '        #                               	   T      @  n   #   ?   #   @   #   A   #   6   #   7   #   8   #   Z   #   ]      X  _ufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @                                                                                 	  disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            B    '                                      n   #           1   #           w   @   A      $  lvts-calib-data-1 lvts-calib-data-2                             usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           B    )             )>              	  \mac ippc                                 	   U              "   .   "   /           "      "         $  n   2      "      !         2         $  _sys_ck ref_ck mcu_ck dma_ck xhci_ck         	   I      h                 okay            
           
   J        
-   K        5         usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           B    *       -    *>              	  \mac ippc                        *        ?                      +                                   "   0           "           n   2      "      2           _sys_ck ref_ck mcu_ck            	   V                    	   I      i        okay            
	host            
   J   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          B                       \mac                                 "   1           "           n   2           _sys_ck          okay            
-   K         usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           B    +       -    +>              	  \mac ippc                        +        ?                      +                                   "   2           "           n   2      "      2   	        _sys_ck ref_ck mcu_ck            	   W                    	   I      j        okay            
	host            
   J   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          B                       \mac                                 "   3           "           n   2   	        _sys_ck          okay             J        
-   K         pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           6pci                      +           B    /        @       	  \pcie-mac                                 [             8  ׁ                                                            e       X              o          0  n   #   V   #   #   #   &   #   +   #   K   2         /  _pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem             "   G           "           	   Y      	  ~pcie-phy               7                                            `                    Z                      Z                     Z                     Z           okay            default            [   interrupt-controller                                                Z         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           6pci                      +           B    /       @       	  \pcie-mac                                 [             8  ׁ       $       $                  $       $                 e       X              o          (  n   #   W      #   X      #   Q   2         /  _pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem             "   H           "           	   \         	  ~pcie-phy               7                                           `                    ]                      ]                     ]                     ]           okay            default            ^   interrupt-controller                                                ]         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         B    2                      9               n   "   o   2      2           _spi sf axi                       +            okay            default            _   flash@0           jedec,spi-nor           B            u                                efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            B                                  +      usb3-tx-imp@184,1           B                               u      usb3-rx-imp@184,2           B                              t      usb3-intr@185           B                              s      usb3-tx-imp@186,1           B                               r      usb3-rx-imp@186,2           B                              q      usb3-intr@187           B                              p      usb2-intr-p0@188,1          B                          usb2-intr-p1@188,2          B                         usb2-intr-p2@189,1          B                         usb2-intr-p3@189,2          B                         pciephy-rx-ln1@190,1            B                               |      pciephy-tx-ln1-nmos@190,2           B                              {      pciephy-tx-ln1-pmos@191,1           B                               z      pciephy-rx-ln0@191,2            B                              y      pciephy-tx-ln0-nmos@192,1           B                               x      pciephy-tx-ln0-pmos@192,2           B                              w      pciephy-glb-intr@193            B                               v      dp-data@1ac         B                      lvts1-calib@1bc         B                @      lvts2-calib@1d0         B     8           A      svs-calib@580           B     d           B      socinfo-data1@7a0           B              t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0           B               n   "           _ref                       V         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0           B               n   "           _ref                       W         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         B                     n           mipi_tx0_pll            a                      	  disabled                     dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         B                     n           mipi_tx1_pll            a                      	  disabled                     i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B                 "                                     u           n   `       #   ;      	  _main dma                         +            okay            h         default            a      i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B                "                                      u           n   `      #   ;      	  _main dma                         +          	  disabled          i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B                 "                                     u           n   `      #   ;      	  _main dma                         +            okay            h         default            b   pmic@34                      mediatek,mt6360         B   4                                  IRQB            default            c                  clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          B    0                a              `      hdmi-phy@11d5f000             mediatek,mt8195-hdmi-phy            B                     n   "   P   #      !      !           _pll_ref 26m pll1 pll2           hdmi_txpll          a                           
                 	  disabled                     i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B                 "                                      u           n   d       #   ;      	  _main dma                         +            okay            h         default            e      i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B                "                                      u           n   d      #   ;      	  _main dma                         +            okay            h           0        default            f   trackpad@15           elan,ekth3000           B                            default            g           h                  i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B                 "                                     u           n   d      #   ;      	  _main dma                         +            okay            h         default            i   codec@1a            B                 Y                      !           0   j        <   j        I   k        W   j          realtek,rt5682s         f                    amplifier@38              maxim,max98390          B   8        |      d           Right                                amplifier@39              maxim,max98390          B   9        Left                                    i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B    0            "                                     u           n   d      #   ;      	  _main dma                         +            okay            h         default            l   tpm@50            google,cr50         B   P              X           default            m         i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B    @            "                                      u           n   d      #   ;      	  _main dma                         +            okay            h         default            n   touchscreen@10            hid-over-i2c            B                            \           default            o           
           h      	  disabled          touchscreen@15            hid-over-i2c            B                            \           default            o           
           h         clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          B    P                a              d      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                   7           okay       usb-phy@0           B               n   "              _ref da_ref                        U      usb-phy@700         B              n   !      "           _ref da_ref          w   p   q   r        intr rx_imp tx_imp                        \         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0           B               n   "              _ref da_ref                        G      usb-phy@700         B              n   !      "           _ref da_ref          w   s   t   u        intr rx_imp tx_imp                        H         phy@11e80000              mediatek,mt8195-pcie-phy            B                     \sif         w   v   w   x   y   z   {   |      G  glb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1             7                       okay               Y      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           B                     n            
  _unipro mp                     	  disabled               T      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           B             @         n   }          0                                                 job mmu gpu            ~      (     7   
   7      7      7      7           core0 core1 core2 core3 core4           okay                      clock-controller@13fbf000             mediatek,mt8195-mfgcfg          B                    a              }      syscon@14000000           mediatek,mt8195-vppsys0 syscon          B                      a                                    %      dma-controller@14001000           mediatek,mt8195-mdp3-rdma           B                                                        *              7           7              n   %         <                                                       >         display@14002000              mediatek,mt8195-mdp3-fg         B                                            n   %          display@14003000              mediatek,mt8195-mdp3-stitch         B     0                         0            n   %         display@14004000              mediatek,mt8195-mdp3-hdr            B     @                         @            n   %   "      display@14005000              mediatek,mt8195-mdp3-aal            B     P                      F                        P            n   %   
           7         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           B     `                         `                %        n   %         display@14007000              mediatek,mt8195-mdp3-tdshp          B     p                         p            n   %   #      display@14008000              mediatek,mt8195-mdp3-color          B                           I                                    n   %   $           7         display@14009000              mediatek,mt8195-mdp3-ovl            B                           J                                    n   %   %           7           7            display@1400a000              mediatek,mt8195-mdp3-padding            B                                          n   %              7         display@1400b000              mediatek,mt8195-mdp3-tcc            B                                          n   %         dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         B                                              +        n   %           7                 7           >         mutex@1400f000            mediatek,mt8195-vpp-mutex           B                           P                                    n   %              7         smi@14010000              mediatek,mt8195-smi-sub-common          B                     n   %      %      %           _apb smi gals0           I              7                    smi@14011000              mediatek,mt8195-smi-sub-common          B                    n   %      %      %           _apb smi gals0           I              7                    smi@14012000              mediatek,mt8195-smi-common-vpp          B                      n   %      %      %      %           _apb smi gals0 gals1            7                    larb@14013000             mediatek,mt8195-smi-larb            B    0                V           I           n   %      %           _apb smi            7                    iommu@14018000            mediatek,mt8195-iommu-vpp           B                  8  g                                                        R               n   %           _bclk                          7                    clock-controller@14e00000             mediatek,mt8195-wpesys          B                     a              (      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         B                     a         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         B    0                a         larb@14e04000             mediatek,mt8195-smi-larb            B    @                V           I           n   (      (           _apb smi            7                    larb@14e05000             mediatek,mt8195-smi-larb            B    P                V           I           n   (      (      %           _apb smi gals               7                    syscon@14f00000           mediatek,mt8195-vppsys1 syscon          B                     a                 	                  '      mutex@14f01000            mediatek,mt8195-vpp-mutex           B                          {                     	              n   '   '           7         larb@14f02000             mediatek,mt8195-smi-larb            B                     V           I           n   '      '      %           _apb smi gals               7                    larb@14f03000             mediatek,mt8195-smi-larb            B    0                V           I           n   '      '      %           _apb smi gals               7                    display@14f06000              mediatek,mt8195-mdp3-split          B    `                      	  `            n   '      '   +   '   ,           7         display@14f07000              mediatek,mt8195-mdp3-tcc            B    p                      	  p            n   '         dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           B                          	                          n   '           7                 7           >         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           B                          	                          n   '   
        7                 7           >         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           B                          	                          n   '           7                 7           >         display@14f0b000              mediatek,mt8195-mdp3-fg         B                          	              n   '   	      display@14f0c000              mediatek,mt8195-mdp3-fg         B                          	              n   '         display@14f0d000              mediatek,mt8195-mdp3-fg         B                          	              n   '         display@14f0e000              mediatek,mt8195-mdp3-hdr            B                          	              n   '         display@14f0f000              mediatek,mt8195-mdp3-hdr            B                          	              n   '         display@14f10000              mediatek,mt8195-mdp3-hdr            B                           
               n   '          display@14f11000              mediatek,mt8195-mdp3-aal            B                          i                     
              n   '              7         display@14f12000              mediatek,mt8195-mdp3-aal            B                           j                     
               n   '              7         display@14f13000              mediatek,mt8195-mdp3-aal            B    0                      k                     
  0            n   '   !           7         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           B    @                      
  @                        n   '         display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           B    P                      
  P                        n   '   $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           B    `                      
  `                        n   '   %      display@14f17000              mediatek,mt8195-mdp3-tdshp          B    p                      
  p            n   '         display@14f18000              mediatek,mt8195-mdp3-tdshp          B                          
              n   '   (      display@14f19000              mediatek,mt8195-mdp3-tdshp          B                          
              n   '   )      display@14f1a000              mediatek,mt8195-mdp3-merge          B                          
              n   '              7         display@14f1b000              mediatek,mt8195-mdp3-merge          B                          
              n   '              7         display@14f1c000              mediatek,mt8195-mdp3-color          B                          t                     
              n   '              7         display@14f1d000              mediatek,mt8195-mdp3-color          B                          
                    u               n   '              7         display@14f1e000              mediatek,mt8195-mdp3-color          B                          v                     
              n   '              7         display@14f1f000              mediatek,mt8195-mdp3-ovl            B                          w                     
              n   '               7           7            display@14f20000              mediatek,mt8195-mdp3-padding            B                                          n   '              7         display@14f21000              mediatek,mt8195-mdp3-padding            B                                        n   '              7         display@14f22000              mediatek,mt8195-mdp3-padding            B                                          n   '              7         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         B    0                        0                        n   '           7                 7           >         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         B    @                        @                        n   '           7                 7           >         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         B    P                        P                        n   '           7                 7           >         clock-controller@15000000             mediatek,mt8195-imgsys          B                      a              /      larb@15001000             mediatek,mt8195-smi-larb            B                     V   	        I           n   /       /       /   
        _apb smi gals               7                    smi@15002000              mediatek,mt8195-smi-sub-common          B                      n   /      /      %           _apb smi gals0           I              7                    smi@15003000              mediatek,mt8195-smi-sub-common          B     0                n   /       /       /   
        _apb smi gals0           I              7                    clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         B                     a                    larb@15120000             mediatek,mt8195-smi-larb            B                     V   
        I           n   /                  _apb smi            7                    clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          B                     a         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         B    "                 a                    larb@15230000             mediatek,mt8195-smi-larb            B    #                 V           I           n   /                  _apb smi            7                    clock-controller@15330000             mediatek,mt8195-ipesys          B    3                 a              0      larb@15340000             mediatek,mt8195-smi-larb            B    4                 V           I           n   0      0           _apb smi            7                    clock-controller@16000000             mediatek,mt8195-camsys          B                      a              1      larb@16001000             mediatek,mt8195-smi-larb            B                     V           I           n   1       1       1           _apb smi gals               7                    larb@16002000             mediatek,mt8195-smi-larb            B                      V           I           n   1      1           _apb smi            7                    smi@16004000              mediatek,mt8195-smi-sub-common          B     @                n   1       1       1           _apb smi gals0           I              7                    smi@16005000              mediatek,mt8195-smi-sub-common          B     P                n   1      1      %           _apb smi gals0           I              7                    larb@16012000             mediatek,mt8195-smi-larb            B                     V           I           n                      _apb smi            7                     larb@16013000             mediatek,mt8195-smi-larb            B    0                V           I           n                      _apb smi            7                     larb@16014000             mediatek,mt8195-smi-larb            B    @                V           I           n                      _apb smi            7   !                 larb@16015000             mediatek,mt8195-smi-larb            B    P                V           I           n                      _apb smi            7   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa         B                    a                    clock-controller@1606f000             mediatek,mt8195-camsys_yuva         B                    a                    clock-controller@1608f000             mediatek,mt8195-camsys_rawb         B                    a                    clock-controller@160af000             mediatek,mt8195-camsys_yuvb         B    
                a                    clock-controller@16140000             mediatek,mt8195-camsys_mraw         B                     a                    larb@16141000             mediatek,mt8195-smi-larb            B                    V           I           n   1              1           _apb smi gals               7   "                 larb@16142000             mediatek,mt8195-smi-larb            B                     V           I           n                      _apb smi            7   "                 clock-controller@17200000             mediatek,mt8195-ccusys          B                      a                    larb@17201000             mediatek,mt8195-smi-larb            B                     V           I           n                      _apb smi            7                    video-codec@18000000              mediatek,mt8195-vcodec-dec          *           7                          +            B                   @                                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         B                       7                   n   "   A   )      )      "           _sel vdec lat top               "   A           "              7         video-codec@10000             mediatek,mtk-vcodec-lat         B                                         0  7                                        n   "   A   )      )      "           _sel vdec lat top               "   A           "              7         video-codec@25000             mediatek,mtk-vcodec-core            B     P                                   P  7                                                           n   "   A   *      *      "           _sel vdec lat top               "   A           "              7            larb@1800d000             mediatek,mt8195-smi-larb            B                     V           I           n   )       )            _apb smi            7                    larb@1800e000             mediatek,mt8195-smi-larb            B                     V           I           n   %      )            _apb smi            7                    clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         B                     a              )      larb@1802e000             mediatek,mt8195-smi-larb            B                    V           I           n   *       *            _apb smi            7                    clock-controller@1802f000             mediatek,mt8195-vdecsys         B                    a              *      larb@1803e000             mediatek,mt8195-smi-larb            B                    V           I           n   %      +            _apb smi            7                    clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           B                    a              +      clock-controller@190f3000             mediatek,mt8195-apusys_pll          B    0                a         clock-controller@1a000000             mediatek,mt8195-vencsys         B                      a              ,      larb@1a010000             mediatek,mt8195-smi-larb            B                     V           I           n   ,      ,           _apb smi            7                    video-codec@1a020000              mediatek,mt8195-vcodec-enc          B                   H  7     `     a     b     c     d     v     w     x     y              U               *           n   ,         	  _venc_sel               "   @           "              7                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec             7         0  7     m     n     r     s     t     u                     +         0                                              jpgdec@0,0            mediatek,mt8195-jpgdec-hw           B                     0  7     m     n     r     s     t     u              W               n   ,           _jpgdec             7         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw           B                    0  7     m     n     r     s     t     u              X               n   ,           _jpgdec             7         jpgdec@1,0            mediatek,mt8195-jpgdec-hw           B                    0  7                                            \               n   -           _jpgdec             7            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           B                      a              -      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            B                                      a                                  &   port                         +       endpoint@0          B            v                          jpeg-encoder@1a030000             mediatek,mt8195-jpgenc             7            7                                         +         0                                              jpgenc@0,0            mediatek,mt8195-jpgenc-hw           B                        7     g     h     i     l              V               n   ,           _jpgenc             7         jpgenc@1,0            mediatek,mt8195-jpgenc-hw           B                       7                                  [               n   -           _jpgenc             7            larb@1b010000             mediatek,mt8195-smi-larb            B                     V           I           n   -      -      %            _apb smi gals               7                    ovl@1c000000              mediatek,mt8195-disp-ovl            B                            |                  7           n   &            7                              ports                        +       port@0          B       endpoint            v                       port@1          B      endpoint            v                             rdma@1c002000             mediatek,mt8195-disp-rdma           B                            ~                  7           n   &           7                               ports                        +       port@0          B       endpoint            v                       port@1          B      endpoint            v                             color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           B     0                                        7           n   &                   0       ports                        +       port@0          B       endpoint            v                       port@1          B      endpoint            v                             ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           B     @                                        7           n   &                   @       ports                        +       port@0          B       endpoint            v                       port@1          B      endpoint            v                             aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           B     P                                        7           n   &                   P       ports                        +       port@0          B       endpoint            v                       port@1          B      endpoint            v                             gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           B     `                                        7           n   &                   `       ports                        +       port@0          B       endpoint            v                       port@1          B      endpoint            v                             dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         B     p                                        7           n   &   	                p       ports                        +       port@0          B       endpoint            v                       port@1          B      endpoint            v                             dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         B                                             7           n   &      &   *           _engine digital hs           	           ~dphy          	  disabled          dsc@1c009000              mediatek,mt8195-disp-dsc            B                                             7           n   &                          ports                        +       port@0          B       endpoint            v                       port@1          B      endpoint            v                             dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         B                                             7           n   &      &   +           _engine digital hs           	           ~dphy          	  disabled          merge@1c014000            mediatek,mt8195-disp-merge          B    @                                        7           n   &                   @       ports                        +       port@0          B       endpoint            v                       port@1          B      endpoint            v                             dp-intf@1c015000              mediatek,mt8195-dp-intf         B    P                                        7           n   &   ,   &      !           _pixel engine pll            okay       ports                        +       port@0          B       endpoint            v                       port@1          B      endpoint            v                             mutex@1c016000            mediatek,mt8195-disp-mutex          B    `                                        7           n   &                   `              U      larb@1c018000             mediatek,mt8195-smi-larb            B                    V            I           n   &   (   &   (   %           _apb smi gals               7                    larb@1c019000             mediatek,mt8195-smi-larb            B                    V           I           n   &   (   %       %           _apb smi gals               7                    syscon@1c100000           mediatek,mt8195-vdosys1 syscon          B                                                           a           O              .   port                         +       endpoint@1          B           v                          smi@1c01b000              mediatek,mt8195-smi-common-vdo          B                     n   &   %   &   &   &   )   &   $        _apb smi gals0 gals1            7                    iommu@1c01f000            mediatek,mt8195-iommu-vdo           B                  8  g                                                                                  n   &   '        _bclk               7                    mutex@1c101000            mediatek,mt8195-disp-mutex          B                                            7           n   .                                       larb@1c102000             mediatek,mt8195-smi-larb            B                     V           I           n   .       .       .           _apb smi gals               7                    larb@1c103000             mediatek,mt8195-smi-larb            B    0                V           I           n   .      .      %            _apb smi gals               7                    dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           B    @                                     n   .              7           7      @                @            >         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           B    P                                     n   .              7           7      `                P            >         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           B    `                                     n   .              7           7      A                `            >         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           B    p                                     n   .              7           7      a                p            >         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           B                                         n   .              7           7      B                            >         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           B                                         n   .              7           7      b                            >         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           B                                         n   .              7           7      C                            >         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           B                                         n   .              7           7      c                            >         vpp-merge@1c10c000            mediatek,mt8195-disp-merge          B                                         n   .   	   .           _merge merge_async              7                                        1   .         vpp-merge@1c10d000            mediatek,mt8195-disp-merge          B                                         n   .   
   .           _merge merge_async              7                                        1   .         vpp-merge@1c10e000            mediatek,mt8195-disp-merge          B                                         n   .      .           _merge merge_async              7                                        1   .         vpp-merge@1c10f000            mediatek,mt8195-disp-merge          B                                         n   .      .           _merge merge_async              7                                        1   .         vpp-merge@1c110000            mediatek,mt8195-disp-merge          B                                          n   .      .           _merge merge_async              7                                         1   .      ports                        +       port@0                       +            B       endpoint@1          B           v                       port@1                       +            B      endpoint@1          B           v                             dpi@1c112000              mediatek,mt8195-dpi         B                     n   .   -   .      .   2        _pixel engine pll                                     7           1   .         	  disabled       ports                        +       port@0          B       endpoint             port@1          B      endpoint                   dp-intf@1c113000              mediatek,mt8195-dp-intf         B    0                                        7           n   .   /   .      !           _pixel engine pll            okay       ports                        +       port@0                       +            B       endpoint@1          B           v                       port@1                       +            B      endpoint@1          B           v                             hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  B    @            P            p                                                              4  \mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p          @            P            p                                                          h  n   .   %   .       .   #   .   !   .   $   .   "   .   1   .   &   .   '   .   (   .   )   .   *   "           _mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top             7           7      d      e                           (  1   .   3   .   4   .   5   .   6   .   7      E  8vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async       ports                        +       port@0                       +            B       endpoint@1          B           v                       port@1                       +            B      endpoint@1          B           v                             hdmi-tx@1c300000              mediatek,mt8195-hdmi-tx                    B    0                  n   "   Q   "   L   "   M   '   ,        _bus hdcp hdcp24m hdmi-split            "   L           "                                   7           	           ~hdmi          	  disabled       i2c           mediatek,mt8195-hdmi-ddc            n         ports                        +       port@0          B       endpoint             port@1          B      endpoint                   edp-tx@1c500000           mediatek,mt8195-edp-tx          B    P                 w           dp_calibration_data            7                                          okay            default               ports                        +       port@0          B       endpoint            v                       port@1          B      endpoint                                 v                          aux-bus    panel         
    edp-panel                            port       endpoint            v                                dp-tx@1c600000            mediatek,mt8195-dp-tx           B    `                 w           dp_calibration_data            7                                          okay                        default                          ports                        +       port@0                       +            B       endpoint@1          B           v                       port@1          B      endpoint                                           thermal-zones      cpu0-thermal                                          trips      trip-alert           L        $           Epassive                  trip-crit                    $        	   Ecritical             cooling-maps       map0            /         0  4                        cpu1-thermal                                          trips      trip-alert           L        $           Epassive                  trip-crit                    $        	   Ecritical             cooling-maps       map0            /         0  4                        cpu2-thermal                                          trips      trip-alert           L        $           Epassive                  trip-crit                    $        	   Ecritical             cooling-maps       map0            /         0  4                        cpu3-thermal                                          trips      trip-alert           L        $           Epassive                  trip-crit                    $        	   Ecritical             cooling-maps       map0            /         0  4                        cpu4-thermal                                           trips      trip-alert           L        $           Epassive                  trip-crit                    $        	   Ecritical             cooling-maps       map0            /         0  4                        cpu5-thermal                                          trips      trip-alert           L        $           Epassive                  trip-crit                    $        	   Ecritical             cooling-maps       map0            /         0  4                        cpu6-thermal                                          trips      trip-alert           L        $           Epassive                  trip-crit                    $        	   Ecritical             cooling-maps       map0            /         0  4                        cpu7-thermal                                          trips      trip-alert           L        $           Epassive                  trip-crit                    $        	   Ecritical             cooling-maps       map0            /         0  4                        vpu0-thermal                                          trips      trip-alert           L        $           Epassive       trip-crit                    $        	   Ecritical                vpu1-thermal                                       	   trips      trip-alert           L        $           Epassive       trip-crit                    $        	   Ecritical                gpu-thermal                                    
   trips      trip-alert           L        $           Epassive       trip-crit                    $        	   Ecritical                gpu1-thermal                                          trips      trip-alert           L        $           Epassive       trip-crit                    $        	   Ecritical                vdec-thermal                                          trips      trip-alert           L        $           Epassive       trip-crit                    $        	   Ecritical                img-thermal                                       trips      trip-alert           L        $           Epassive       trip-crit                    $        	   Ecritical                infra-thermal                                         trips      trip-alert           L        $           Epassive       trip-crit                    $        	   Ecritical                cam0-thermal                                          trips      trip-alert           L        $           Epassive       trip-crit                    $        	   Ecritical                cam1-thermal                                          trips      trip-alert           L        $           Epassive       trip-crit                    $        	   Ecritical                soc-area-thermal                                       trips      trip-crit            H         $        	   Ecritical                pmic-area-thermal                                       trips      trip-crit            H         $        	   Ecritical                   backlight-lcd0            pwm-backlight           C              U  @        n      R            {                                               chosen          serial0:115200n8          memory@40000000         6memory          B    @                regulator-pp3300-disp-x           regulator-fixed         pp3300_disp_x           ) 2Z        A 2Z        Y  	                       7            default                       k                 regulator-pp3300-ldo-z5           regulator-fixed         pp3300_ldo_z5            u                 ) 2Z        A 2Z                 regulator-pp3300-s3           regulator-fixed       
  pp3300_s3            u                 ) 2Z        A 2Z           k           h      regulator-pp3300-z2           regulator-fixed       
  pp3300_z2            u                 ) 2Z        A 2Z                      k      regulator-pp4200-z2           regulator-fixed       
  pp4200_z2            u                 ) @@        A @@                 regulator-pp5000-s5           regulator-fixed       
  pp5000_s5            u                 ) LK@        A LK@                 regulator-ppvar-sys           regulator-fixed       
  ppvar_sys            u                          thermal-sensor-t1             generic-adc-thermal                                    sensor-channel            x        ~    %  '    :  [  N     a    u0        @  ]      P        `  G     p    $    8    L    _   } s   k    \ (   O    D 8   ;    3 H   ,                 thermal-sensor-t2             generic-adc-thermal                                   sensor-channel            x        ~    %  '    :  [  N     a    u0        @  ]      P        `  G     p    $    8    L    _   } s   k    \ (   O    D 8   ;    3 H   ,                 regulator-5v0-usb-vbus            regulator-fixed       	  usb-vbus            ) LK@        A LK@                  u           K      reserved-memory                      +               memory@50000000           shared-dma-pool         B    P                             4      memory@60000000           shared-dma-pool         B    `                              ;      memory@60d80000           shared-dma-pool         B    `                             =      memory@60e80000           shared-dma-pool         B    `       (                      :         rt1019p           realtek,rt1019p         rt1019p                     default                          d          	  disabled             	compatible interrupt-parent #address-cells #size-cells model chassis-type dp-intf0 dp-intf1 dpi1 gce0 gce1 hdmi0 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c7 mmc0 mmc1 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform mediatek,adsp mediatek,dai-link pinctrl-names pinctrl-0 audio-routing link-name mediatek,clk-provider sound-dai #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller mediatek,broken-save-restore-fw affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges mediatek,rsel-resistance-in-si-unit gpio-line-names pinmux input-enable bias-pull-up bias-disable drive-strength-microamp drive-strength bias-pull-down output-high output-low #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells mediatek,dmic-mode mediatek,mic-type-0 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells firmware-name memory-region mediatek,rpmsg-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names mediatek,etdm-in2-cowork-source mediatek,etdm-out2-cowork-source mediatek,pad-select spi-max-frequency wakeup-source google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count power-role data-role try-power-role keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys mediatek,syscon-wakeup dr_mode vusb33-supply rx-fifo-depth vbus-supply bus-width cap-mmc-highspeed cap-mmc-hw-reset hs400-ds-delay mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable pinctrl-1 vmmc-supply vqmmc-supply cap-sd-highspeed cd-gpios no-mmc sd-uhs-sdr50 sd-uhs-sdr104 freq-table-hz mediatek,ufs-disable-mcq mediatek,u3p-dis-msk usb2-lpm-disable bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map spi-rx-bus-width spi-tx-bus-width bits #phy-cells mediatek,ibias mediatek,ibias_up i2c-scl-internal-delay-ns vcc-supply realtek,jd-src AVDD-supply DBVDD-supply MICVDD-supply LDO1-IN-supply realtek,amic-delay-ms reset-gpios sound-name-prefix hid-descr-addr post-power-on-delay-ms vdd-supply operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz data-lanes power-supply backlight polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device brightness-levels default-brightness-level enable-gpios num-interpolated-steps pwms stdout-path enable-active-high gpio vin-supply regulator-boot-on io-channels io-channel-names temperature-lookup-table no-map label sdb-gpios 