 Q   8 C   (            * C                             -    google,ciri-sku1 google,ciri mediatek,mt8188                                     +            7Google Ciri sku1 board     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dpi@1c112000            T/soc/dsc@1c009000            Y/soc/ethdr@1c114000          `/soc/mailbox@10320000            e/soc/mailbox@10330000            j/soc/merge0@1c014000             q/soc/merge@1c10c000          x/soc/merge@1c10d000          /soc/merge@1c10e000          /soc/merge@1c10f000          /soc/merge@1c110000          /soc/mutex@1c016000          /soc/mutex@1c101000          /soc/padding@1c11d000            /soc/padding@1c11e000            /soc/padding@1c11f000            /soc/padding@1c120000            /soc/padding@1c121000            /soc/padding@1c122000            /soc/padding@1c123000            /soc/padding@1c124000            /soc/rdma@1c104000           /soc/rdma@1c105000           /soc/rdma@1c106000          /soc/rdma@1c107000          /soc/rdma@1c108000          !/soc/rdma@1c109000          ,/soc/rdma@1c10a000          7/soc/rdma@1c10b000          B/soc/dsi@1c008000           G/soc/i2c@11280000           L/soc/i2c@11e00000           Q/soc/i2c@11281000           V/soc/i2c@11282000           [/soc/i2c@11e01000           `/soc/i2c@11ec0000           e/soc/i2c@11ec1000           j/soc/mmc@11230000           o/soc/serial@11001100          cpus                         +       cpu@0           wcpu           arm,cortex-a55                      psci            w5                                               @                                 @                               1               E           T   	      cpu@100         wcpu           arm,cortex-a55                     psci            w5                                               @                                 @                               1               E           T   
      cpu@200         wcpu           arm,cortex-a55                     psci            w5                                               @                                 @                               1               E           T         cpu@300         wcpu           arm,cortex-a55                     psci            w5                                               @                                 @                               1               E           T         cpu@400         wcpu           arm,cortex-a55                     psci            w5                                               @                                 @                               1               E           T         cpu@500         wcpu           arm,cortex-a55                     psci            w5                                               @                                 @                               1               E           T         cpu@600         wcpu           arm,cortex-a78                     psci                                                            @                                 @                               1              E           T         cpu@700         wcpu           arm,cortex-a78                     psci                                                            @                                 @                               1              E           T         cpu-map    cluster0       core0           \   	      core1           \   
      core2           \         core3           \         core4           \         core5           \         core6           \         core7           \               idle-states         `psci       cpu-off-l             arm,idle-state          m                       2           _          D        T         cpu-off-b             arm,idle-state          m                       -                             T         cluster-off-l             arm,idle-state          m                     7                     H        T         cluster-off-b             arm,idle-state          m                     2                             T            l2-cache0             cache                                    @                                        T         l2-cache1             cache                                    @                                        T         l3-cache              cache                                     @                            T            oscillator-13m            fixed-clock                      ]@        clk13m          T   A      oscillator-26m            fixed-clock                             clk26m          T   D      oscillator-32k            fixed-clock                                clk32k        opp-table-gpu             operating-points-v2                  T   y   opp-390000000               >                 !         opp-431000000                                !         opp-473000000               1h@         	'        !         opp-515000000               F         	X        !         opp-556000000               !#          	h        !         opp-598000000               #         	<        !         opp-640000000               &%          	        !         opp-670000000               'c         
        !         opp-700000000               )'          
L        !         opp-730000000               +         
}        !         opp-760000000               -L          
`        !         opp-790000000               /q         
4        !         opp-835000000               1         (r        !         opp-880000000               4s          q        !         opp-915000000               6         X        !         opp-915000000-5             6                 !   0      opp-915000000-6             6         q        !   p      opp-950000000               8ـ         5         !         opp-950000000-5             8ـ         X        !   0      opp-950000000-6             8ـ         q        !   p         pmu-a55           arm,cortex-a55-pmu                      2                  pmu-a78           arm,cortex-a78-pmu                      2                  psci              arm,psci-1.0            smc       sound           =           Ookay          ]  Vaud_etdm_hp_on aud_etdm_hp_off aud_etdm_spk_on aud_etdm_spk_off aud_mtkaif_on aud_mtkaif_off            d           n           x                                                         mediatek,mt8188-es8326           7mt8188_m98390_8326          ETDM1_OUT ETDM_SPK_PIN ETDM2_OUT ETDM_HP_PIN ETDM1_IN ETDM_SPK_PIN ETDM2_IN ETDM_HP_PIN ADDA Capture MTKAIF_PIN Headphone Jack HPOL Headphone Jack HPOR MIC1 Headset Mic Left Spk Front Left BE_OUT Right Spk Front Right BE_OUT       dai-link-0          ETDM1_IN_BE         i2s         cpu       dai-link-1          ETDM1_OUT_BE            i2s         cpu    codec                          dai-link-2          ETDM2_IN_BE         cpu    codec                       dai-link-3          ETDM2_OUT_BE            cpu    codec                       dai-link-4          DPTX_BE    codec                          thermal-zones      cpu-little0-thermal                                         trips      trip-alert0         % _        1          ~passive         T   !      trip-alert1         % s        1          ~hot       trip-crit           %         1          	  ~critical             cooling-maps       map0            <   !      H  A   	   
                        cpu-little1-thermal                                        trips      trip-alert0         % _        1          ~passive         T   "      trip-alert1         % s        1          ~hot       trip-crit           %         1          	  ~critical             cooling-maps       map0            <   "      H  A   	   
                        cpu-little2-thermal                                        trips      trip-alert0         % _        1          ~passive         T   #      trip-alert1         % s        1          ~hot       trip-crit           %         1          	  ~critical             cooling-maps       map0            <   #      H  A   	   
                        cpu-little3-thermal                                        trips      trip-alert0         % _        1          ~passive         T   $      trip-alert1         % s        1          ~hot       trip-crit           %         1          	  ~critical             cooling-maps       map0            <   $      H  A   	   
                        cpu-big0-thermal                         d                  trips      trip-alert0         % _        1          ~passive         T   %      trip-alert1         % s        1          ~hot       trip-crit           %         1          	  ~critical             cooling-maps       map0            <   %        A                  cpu-big1-thermal                         d                  trips      trip-alert0         % _        1          ~passive         T   &      trip-alert1         % s        1          ~hot       trip-crit           %         1          	  ~critical             cooling-maps       map0            <   &        A                  apu-thermal                                 '       trips      trip-alert0         % L        1          ~passive       trip-alert1         % s        1          ~hot       trip-crit           %         1          	  ~critical                gpu-thermal                                 '      trips      trip-alert0         % L        1          ~passive         T   (      trip-alert1         % s        1          ~hot       trip-crit           %         1          	  ~critical             cooling-maps       map0            <   (        A   )            gpu1-thermal                                    '      trips      trip-alert0         % L        1          ~passive         T   *      trip-alert1         % s        1          ~hot       trip-crit           %         1          	  ~critical             cooling-maps       map0            <   *        A   )            adsp-thermal                                    '      trips      trip-alert0         % L        1          ~passive       trip-alert1         % s        1          ~hot       trip-crit           %         1          	  ~critical                vdo-thermal                                 '      trips      trip-alert0         % L        1          ~passive       trip-alert1         % s        1          ~hot       trip-crit           %         1          	  ~critical                infra-thermal                                   '      trips      trip-alert0         % L        1          ~passive       trip-alert1         % s        1          ~hot       trip-crit           %         1          	  ~critical                cam1-thermal                                    '      trips      trip-alert0         % L        1          ~passive       trip-alert1         % s        1          ~hot       trip-crit           %         1          	  ~critical                cam2-thermal                                    '      trips      trip-alert0         % L        1          ~passive       trip-alert1         % s        1          ~hot       trip-crit           %         1          	  ~critical                   timer             arm,armv8-timer                   @  2                                             
                ]@      soc                      +             simple-bus          P                                T   performance-controller@11bc10             mediatek,cpufreq-hw                           0               [           T         interrupt-controller@c000000              arm,gic-v3          u                                                                                2      	               T      ppi-partitions     interrupt-partition-0              	   
                    T         interrupt-partition-1                         T               syscon@10000000            mediatek,mt8188-topckgen syscon                                          T   .      syscon@10001000       #    mediatek,mt8188-infracfg-ao syscon                                                     T   /      syscon@10003000           mediatek,mt8188-pericfg syscon               0                           T   X      pinctrl@10005000              mediatek,mt8188-pinctrl       `       P                                                                               0  iocfg0 iocfg_rm iocfg_lt iocfg_lm iocfg_rt eint                                +                            2                      u        B  GSC_AP_INT_ODL AP_DISP_BKLTEN  EN_PPVAR_MIPI_DISP EN_PPVAR_MIPI_DISP_150MA TCHSCR_RST_1V8_L      I2S_SPKR_DATAOUT EN_PP3300_WLAN_X WIFI_KILL_1V8_L BT_KILL_1V8_L AP_FLASH_WP_L   WCAM_PWDN_L WCAM_RST_L UCAM_PWDM_L UCAM_RST_L WCAM_24M_CLK UCAM_24M_CLK MT6319_INT DISP_RST_1V8_L DSIO_DSI_TE  TP MIPI_BL_PWM_1V8  UART_AP_TX_GSC_RX UART_GSC_TX_AP_RX UART_SSPM_TX_DBGCON_RX UART_DBGCON_TX_SSPM_RX UART_ADSP_TX_DBGCON_RX UART_DBGCON_TX_ADSP_RX JTAG_AP_TMS JTAG_AP_TCK JTAG_AP_TDI JTAG_AP_TDO JTAG_AP_TRST AP_KPCOL0 TP  TP EC_AP_HPD_OD PCIE_WAKE_1V8_ODL PCIE_RST_1V8_L PCIE_CLKREQ_1V8_ODL      AP_I2C_AUD_SCL_1V8 AP_I2C_AUD_SDA_1V8 AP_I2C_TPM_SCL_1V8 AP_I2C_TPM_SDA_1V8 AP_I2C_TCHSCR_SCL_1V8 AP_I2C_TCHSCR_SDA_1V8 AP_I2C_PMIC_SAR_SCL_1V8 AP_I2C_PMIC_SAR_SDA_1V8 AP_I2C_EC_HID_KB_SCL_1V8 AP_I2C_EC_HID_KB_SDA_1V8 AP_I2C_UCAM_SCL_1V8 AP_I2C_UCAM_SDA_1V8 AP_I2C_WCAM_SCL_1V8 AP_I2C_WCAM_SDA_1V8 SPI_AP_CS_EC_L SPI_AP_CLK_EC SPI_AP_DO_EC_DI SPI_AP_DI_EC_DO TP TP SPI_AP_CS_TCHSCR_L SPI_AP_CLK_TCHSCR SPI_AP_DO_TCHSCR_DI SPI_AP_DI_TCHSCR_DO TP TP TP TP    TP      PWRAP_SPI_CS_L PWRAP_SPI_CK PWRAP_SPI_MOSI PWRAP_SPI_MISO SRCLKENA0 SRCLKENA1 SCP_VREQ_VAO AP_RTC_CLK32K AP_PMIC_WDTRST_L AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1  HP_INT_ODL SPKR_INT_ODL I2S_HP_DATAIN EN_SPKR I2S_SPKR_MCLK I2S_SPKR_BCLK I2S_HP_MCLK I2S_HP_BCLK I2S_HP_LRCK I2S_HP_DATAOUT RST_SPKR_L I2S_SPKR_LRCK I2S_SPKR_DATAIN     SPI_AP_CLK_ROM SPI_AP_CS_ROM_L SPI_AP_DO_ROM_DI SPI_AP_DI_ROM_DO TP TP         EN_PP2800A_UCAM_X EN_PP1200_UCAM_X EN_PP2800A_WCAM_X EN_PP1100_WCAM_X TCHSCR_INT_1V8_L  MT7921_PMU_EN_1V8  AP_EC_WARM_RST_REQ EC_AP_HID_INT_ODL EC_AP_INT_ODL AP_XHCI_INIT_DONE EMMC_DAT7 EMMC_DAT6 EMMC_DAT5 EMMC_DAT4 EMMC_RST_L EMMC_CMD EMMC_CLK EMMC_DAT3 EMMC_DAT2 EMMC_DAT1 EMMC_DAT0 EMMC_DSL         USB3_HUB_RST_L EC_AP_RSVD0_ODL   SPMI_SCL SPMI_SDA           T   +   adsp-uart-pins          T   L   pins-bus            
  #  $         aud-etdm-hp-on-pins         T      pins-bus            
  n  s  t  u      pins-mclk           
  r         aud-etdm-hp-off-pins            T      pins-bus            
  n   s   t   u                          pins-mclk           
  r                             aud-etdm-spk-on-pins            T      pins-bus            
    q  w  x        -            aud-etdm-spk-off-pins           T      pins-bus            
     q   w   x                             aud-mtkaif-on-pins          T      pins-bus            
  e  f  g  h  i  j         aud-mtkaif-off-pins         T      pins-bus            
  e   f   g   h   i   j                             cros-ec-int-pins            T   O   pins-ec-ap-int-odl          
                      disp-pwm0-pins          T   Q   pins-disp-pwm0          
           <         disp-pwm1-pins          T   R   pins-disp-pwm1          
           <         dp-tx-hpd-pins          T      pins-dp-tx-hpd          
  .         gsc-int-pins            T   r   pins-gsc-ap-int-odl         
                       i2c0-pins           T   c   pins-bus            
  8  7         i2c1-pins           T   q   pins-bus            
  :  9         i2c2-pins           T   f   pins-bus            
  <  ;         H        -            i2c3-pins           T   g   pins-bus            
  >  =         i2c4-pins           T   s   pins-bus            
  @  ?         i2c5-pins           T   u   pins-bus            
  B  A         i2c6-pins           T   v   pins-bus            
  D  C         mipi-disp-avdd-en-pins          T      pins-en-ppvar-mipi-disp         
            U         mipi-disp-avee-en-pins          T      pins-en-ppvar-mipi-disp-150ma           
            U         mipi-dsi-pins           T      pins-bus            
               U         mmc0-default-pins           T   ^   pins-bus          $  
                                    -           `   e      pins-clk            
          -              f      pins-rst            
          -           `   e         mmc0-uhs-pins           T   _   pins-bus          $  
                                    -           `   e      pins-clk            
          -              f      pins-ds         
          -              f      pins-rst            
          -           `   e         nor-default-pins            T   o   pins-clk            
    }                 pins-cs         
  ~         `         pcie-default-pins           T   n   pins-bus            
  /  0  1         scp-pins            T   B   pins-scp-vreq           
  b         H         spi0-pins           T   N   pins-bus            
  E  F  G  H         H         spi1-default-pins           T   S   pins-bus            
  K  L  M  N         H         spi1-sleep-pins         T   T   pins-bus            
  K   L   M   N                             spi2-pins           T   U   pins-bus            
  O  P  Q  R         H         uart0-pins          T   M   pins-bus            
              `         wlan-en-pins            T      pins-en-pp3300-wlan         
            U         audio-codec-pins            T   e   pins-hp-int-odl         
  l                    speaker-en-pins         T   d   pins-en-spkr            
  o             syscon@10006000       )    mediatek,mt8188-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8188-power-controller                         +            m           T   E   power-domain@0                                   +            m              ,   power-domain@1                        -      .           mfg alt            /                     +            m              0   power-domain@2                     m          power-domain@3                     m          power-domain@4                     m                power-domain@15                       .      .      .      .   
   .   3   .   4   .   =   .      .      1      1      1      1      1      1      1      1      1      1      1      1      1      1      1      1      1      1      1            top cam ccu img venc vdec wpe cfgck cfgxo ss-sram-cmn ss-sram-v0l0 ss-sram-v0l1 ss-sram-ve0 ss-sram-ve1 ss-sram-ifa ss-sram-cam ss-sram-v1l5 ss-sram-v1l6 ss-sram-rdr ss-iommu ss-imgcam ss-emi ss-subcmn-rdr ss-rsi ss-cmn-l4 ss-vdec1 ss-wpe ss-cvdo-ve1             /                     +            m      power-domain@16                  H     .      .      2      2      2      2      2      2      2         A  cfgck cfgxo ss-gals ss-cmn ss-emi ss-iommu ss-larb ss-rsi ss-bus               /                     +            m      power-domain@20                  0     .      .      3      3      3      3         8  cfgck cfgxo ss-vpp1-g5 ss-vpp1-g6 ss-vpp1-l5 ss-vpp1-l6            /        m          power-domain@22                       4            ss-vdec1-soc-l1            /                     +            m      power-domain@23                       5            ss-vdec2-l1            /        m             power-domain@29                        .      .      .   	   .           cam ccu bus cfgck              /                     +            m              6   power-domain@30                  (     7       7      7      7      7         6  ss-cam-l13 ss-cam-l14 ss-cam-mm0 ss-cam-mm1 ss-camsys              /                     +            m      power-domain@32                        7      8       9          $  ss-camb-sub ss-camb-raw ss-camb-yuv         m          power-domain@31                       7      :       ;          $  ss-cama-sub ss-cama-raw ss-cama-yuv         m                power-domain@17                  (     .      .      <       <      <         &  cfgck cfgxo ss-larb2 ss-larb3 ss-gals              /                     +            m      power-domain@9             	           .   @   .   ?      	  bus hdcp               /        m          power-domain@18                       /        m          power-domain@19                       /        m             power-domain@24                        =       =      =      =         0  ss-ve1-larb ss-ve1-core ss-ve1-gals ss-ve1-sram            /        m          power-domain@21                       >      >           ss-wpe-l7 ss-wpe-l7pce             /        m                power-domain@5                        /           ?           ss-pextp-fmem           m          power-domain@7                        .   0   .   1        seninf0 seninf1         m          power-domain@6                     m          power-domain@10            
           .   E   .   D      	  bus main               /                     +            m      power-domain@11                       /                     +            m      power-domain@14                       .   F        asm            /        m          power-domain@13                       .   S   .      @            a1sys intbus adspck            /        m          power-domain@12                       /        m                power-domain@8                        ?         	  ethermac               /        m                watchdog@10007000             mediatek,mt8188-wdt              p                                    T   F      syscon@1000c000       "    mediatek,mt8188-apmixedsys syscon                                           T   -      timer@10017000        ,    mediatek,mt8188-timer mediatek,mt6765-timer             p                2      	                  A      pwrap@10024000        3    mediatek,mt8188-pwrap mediatek,mt8195-pwrap syscon              @                pwrap           2                         /      /          	  spi wrap       pmic              mediatek,mt6359                  u                         +         adc           mediatek,mt6359-auxadc                   audio-codec           mediatek,mt6359-codec                                 *         regulators            mediatek,mt6359-regulator      buck_vs1            >vs1         M 5         e !        }                   buck_vgpu11         >vgpu11          M         e 7                  }                                    buck_vmodem         >vmodem          M X        e X          *        }         buck_vpu            >vpu         M         e 7                  }                                    buck_vcore          >vcore           M         e                    }                                    buck_vs2            >vs2         M 5         e j         }                   buck_vpa            >vpa         M          e /M`        }  ,      buck_vproc2         >ppvar_dvdd_vgpu         M dp        e 5           L        }                                0          j        T   ,      buck_vproc1         >vproc1          M         e 7          L        }                             T   6      buck_vcore_sshub            >vcore_sshub         M         e 7      buck_vgpu11_sshub           >vgpu11_sshub            M dp        e dp               ldo_vaud18          >vaud18          M w@        e w@        }         ldo_vsim1           >vsim1           M         e /M`      ldo_vibr            >vibr            M O        e 2Z      ldo_vrf12           >vrf12           M         e                 ldo_vusb            >vusb            M -        e -        }                 ldo_vsram_proc2         >vsram_proc2         M          e           L        }                  ldo_vio18           >vio18           M         e         }                 ldo_vcamio          >vcamio          M         e       ldo_vcn18           >vcn18           M w@        e w@        }         ldo_vfe28           >vfe28           M *        e *        }   x      ldo_vcn13           >vcn13           M         e        ldo_vcn33_1_bt          >vcn33_1_bt          M *        e 5g      ldo_vcn33_1_wifi            >vcn33_1_wifi            M *        e 5g      ldo_vaux18          >vaux18          M w@        e w@        }                  ldo_vsram_others            >pp0850_dvdd_sram_gpu            M q        e 5                   }              ,          j        T   0      ldo_vefuse          >vefuse          M         e       ldo_vxo22           >vxo22           M w@        e !               ldo_vrfck           >vrfck           M `        e       ldo_vrfck_1         >vrfck           M         e j       ldo_vbif28          >vbif28          M *        e *        }         ldo_vio28           >vio28           M *        e 2Z      ldo_vemc            >vemc            M ,@         e 2Z      ldo_vemc_1          >vemc            M &%        e 2Z        T   `      ldo_vcn33_2_bt          >vcn33_2_bt          M *        e 5g      ldo_vcn33_2_wifi            >vcn33_2_wifi            M *        e 5g      ldo_va12            >va12            M O        e                 ldo_va09            >va09            M 5         e O      ldo_vrf18           >vrf18           M         e P      ldo_vsram_md          	  >vsram_md            M 5         e 5           *        }         ldo_vufs            >vufs            M         e                  T   a      ldo_vm18            >vm18            M w@        e                  T         ldo_vbbck           >vbbck           M         e O      ldo_vsram_proc1         >vsram_proc1         M          e           L        }                  ldo_vsim2           >vsim2           M         e /M`      ldo_vsram_others_sshub          >vsram_others_sshub          M          e          rtc           mediatek,mt6358-rtc             spmi@10027000         *    mediatek,mt8188-spmi mediatek,mt8195-spmi                p                            pmif spmimst            )   .   8        9   .              /      /       .   8      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux       iommu@10315000            mediatek,mt8188-iommu-infra             1P                2                     P           T   l      mailbox@10320000              mediatek,mt8188-gce             2        @         2                      ]              /           T   z      mailbox@10330000              mediatek,mt8188-gce             3        @         2                      ]              /           T   |      scp@10720000              mediatek,mt8188-scp-dual                r                 cfg                      +           T        P             Ookay       scp@0             mediatek,scp-core                          sram            2                     Ookay            Vdefault         d   B        i   C        T   }      scp@d0000             mediatek,scp-core                        sram            2                   	  Odisabled             audio-controller@10b10000             mediatek,mt8188-afe                              )   .   S        9   .              D   -   	   -   
   .      .      .      .      .      .   S   .      .       .   E   .   Q   .   M   .   N   .   O   .   P   @       .      .      .      .   T   .   R        clk26m apll1 apll2 apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 top_a1sys_hp top_aud_intbus top_audio_h top_audio_local_bus top_dptx top_i2so1 top_i2so2 top_i2si1 top_i2si2 adsp_audio_26m apll1_d4 apll2_d4 apll12_div4 top_a2sys top_aud_iec          2      6               w   E              F         	  audiosys               /           .        Ookay            i   G                               T         adsp@10b80000             mediatek,mt8188-dsp       @                                                             cfg sram sec bus            )   .   D           .   D   .   E        audiodsp adsp_bus              H   I        rx tx           w   E           Ookay            i   J   K        Vdefault         d   L        T         mailbox@10b86100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox             a                2                     ]            T   H      mailbox@10b87100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox             q                2                     ]            T   I      clock-controller@10b91100             mediatek,mt8188-adsp-audio26m                                          T   @      serial@11001100       *    mediatek,mt8188-uart mediatek,mt6577-uart                                2                         D   /         	  baud bus            Ookay            Vdefault         d   M      serial@11001200       *    mediatek,mt8188-uart mediatek,mt6577-uart                                2                         D   /         	  baud bus          	  Odisabled          serial@11001300       *    mediatek,mt8188-uart mediatek,mt6577-uart                                2                         D   /         	  baud bus          	  Odisabled          serial@11001400       *    mediatek,mt8188-uart mediatek,mt6577-uart                                2                        D   /         	  baud bus          	  Odisabled          adc@11002000          .    mediatek,mt8188-auxadc mediatek,mt8173-auxadc                                    /           main                       Ookay          syscon@11003000       "    mediatek,mt8188-pericfg-ao syscon                0                           T   ?      spi@1100a000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 2                         .   y   .      /           parent-clk sel-clk spi-clk          Ookay            Vdefault         d   N   ec@0              google,cros-ec-spi                         +              Vdefault         d   O         -   i2c-tunnel            google,cros-ec-i2c-tunnel                                   +       sbs-battery@f             sbs,sbs-battery                    !           5            cbas              google,cros-cbas          keyboard-controller           google,cros-ec-keyb         J           Z            m     D     t x   	 q	 r  s  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	  + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      (                 	  	                 thermal-sensor@1100b000           mediatek,mt8188-lvts-ap                              2                         /              /              P        lvts-calib-data-1                      T   '      pwm@1100e000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm                                   .   '   /   /        main mm         2                                 Ookay            Vdefault         d   Q        T         pwm@1100f000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm                                   .   (   /   F        main mm         2                              	  Odisabled            Vdefault         d   R      spi@11010000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 2                         .   y   .      /   2        parent-clk sel-clk spi-clk          Ookay            Vdefault sleep           d   S        n   T      spi@11012000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 2                         .   y   .      /   3        parent-clk sel-clk spi-clk          Ookay            Vdefault         d   U      spi@11013000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                0                2                         .   y   .      /   4        parent-clk sel-clk spi-clk        	  Odisabled          spi@11018000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                2                         .   y   .      /   8        parent-clk sel-clk spi-clk        	  Odisabled          spi@11019000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                2                         .   y   .      /   9        parent-clk sel-clk spi-clk        	  Odisabled          usb@11201000          #    mediatek,mt8188-mtu3 mediatek,mtu3                       -     >              	  mac ippc            T                     ?                      +           2                      )   .   )        9   .   v           ?   	   .      ?   
        sys_ck ref_ck mcu_ck               V      W                       X  h           Ookay            	host            	   Y   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 mac         2                      )   .   *        9   .   v           ?   
        sys_ck          Ookay            	   Y        	'   Z         ethernet@11021000         ;    mediatek,mt8188-gmac mediatek,mt8195-gmac snps,dwmac-5.10a                     @         2                     	3macirq        0     ?       ?      .   A   .   B   .   C   ?         .  axi apb mac_main ptp_ref rmii_internal mac_cg           )   .   A   .   B   .   C        9   .      .      .           w   E           	C   /        	T   [        	d   \        	w   ]        	           	           	          	  Odisabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config           	                                 	           	           T   [      rx-queues-config            	            	        T   \   queue0           	        
          queue1           	        
          queue2           	        
          queue3           	        
             tx-queues-config            
)            
?        T   ]   queue0           	        
Q            
_         queue1           	        
Q           
_         queue2           	        
Q           
_         queue3           	        
Q           
_               mmc@11230000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              #                                                           .      /      /      /   M      !  source hclk source_cg crypto_clk            Ookay            
k            
u         
        
 H                  
         
         
         
         
         
        Vdefault state_uhs           d   ^        n   _         
           `           a      mmc@11240000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              $                                                          .      /      /   $        source hclk source_cg           )   .           9   .         	  Odisabled          mmc@11250000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              %                                                          .      /      /   A        source hclk source_cg           )   .           9   .         	  Odisabled          thermal-sensor@11278000           mediatek,mt8188-lvts-mcu                '                2                         /              /               P        lvts-calib-data-1                      T          i2c@11280000              mediatek,mt8188-i2c              (             "                2                      !              b       /   7      	  main dma                         +            Ookay            Vdefault         d   c            amplifier@38              maxim,max98390             8        +Front Right         =   +   v           Vdefault         d   d                    T         amplifier@39              maxim,max98390             9        +Front Left                      T         audio-codec@19            everest,es8326                        +   l           Vdefault         d   e                    I           Z            T            i2c@11281000              mediatek,mt8188-i2c              (            "               2                      !              b      /   7      	  main dma                         +            Ookay            Vdefault         d   f               i2c@11282000              mediatek,mt8188-i2c              (             "               2                      !              b      /   7      	  main dma                         +            Ookay            Vdefault         d   g               clock-controller@11283000             mediatek,mt8188-imp-iic-wrap-c              (0                           T   b      usb@112a1000          #    mediatek,mt8188-mtu3 mediatek,mtu3               *       -    *>              	  mac ippc            T            *        ?                      +           2                     )   .   -        9   .   v           ?      .      ?           sys_ck ref_ck mcu_ck               h                       X  p           Ookay            	host            	   Y   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 mac         2                     )   .   .        9   .   v           ?           sys_ck          Ookay             p         usb@112b1000          #    mediatek,mt8188-mtu3 mediatek,mtu3               +       -    +>              	  mac ippc            T            +        ?                      +           2                     )   .   ,        9   .   v           ?      .      ?           sys_ck ref_ck mcu_ck               i                       X  `           Ookay            	host            	   Y   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 mac         2                     )   .   +        9   .   v           ?           sys_ck          Ookay            	'   j         pcie@112f0000         *    mediatek,mt8188-pcie mediatek,mt8192-pcie               /                	  pcie-mac            T                                                 wpci                                  +         0     /   L   /   #   /   &   /   +   /   C   ?         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          u           2                   `                    k                      k                     k                     k                                         l                             m         	  pcie-phy            w   E              F           mac         Ookay            Vdefault         d   n   interrupt-controller                         u                    T   k         spi@1132c000          (    mediatek,mt8188-nor mediatek,mt8186-nor             2                   .   X   ?      ?           spi sf axi          )   .   X        2      9                            +            Ookay            Vdefault         d   o   flash@0           jedec,spi-nor                       u          t-phy@11c20700        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3           T                                 +           w   E           Ookay       pcie-phy@0                            .           ref                    T   m         hdmi-phy@11d5f000         2    mediatek,mt8188-hdmi-phy mediatek,mt8195-hdmi-phy                                  /           pll_ref         hdmi_txpll                                     
                 	  Odisabled            T         dsi-phy@11c80000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx                                 D        mipi_tx0_pll                                    Ookay              P        T         dsi-phy@11c90000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx                                 D        mipi_tx0_pll                                  	  Odisabled            T         i2c@11e00000              mediatek,mt8188-i2c                           "                2                      !              p       /   7      	  main dma                         +            Ookay            Vdefault         d   q            tpm@50            google,cr50            P           +               Vdefault         d   r         i2c@11e01000              mediatek,mt8188-i2c                          "               2                      !              p      /   7      	  main dma                         +            Ookay            Vdefault         d   s               clock-controller@11e02000             mediatek,mt8188-imp-iic-wrap-w                                          T   p      t-phy@11e30000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           T                     Ookay       usb-phy@0                             .      -           ref da_ref                     T   i         t-phy@11e40000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           T                     Ookay       usb-phy@0                             .      -           ref da_ref                     T   V      usb-phy@700                          -      D        ref da_ref                     T   W         t-phy@11e80000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           T                     Ookay       usb-phy@0                             .      -           ref da_ref                     T   h         i2c@11ec0000              mediatek,mt8188-i2c                           "               2                      !              t       /   7      	  main dma                         +            Ookay            Vdefault         d   u               i2c@11ec1000              mediatek,mt8188-i2c                          "                2                      !              t      /   7      	  main dma                         +            Ookay            Vdefault         d   v               clock-controller@11ec2000              mediatek,mt8188-imp-iic-wrap-en                                         T   t      efuse@11f20000        ,    mediatek,mt8188-efuse mediatek,mt8186-efuse                                           +      dp-calib@1a0                         T         lvts1-calib@1ac              @        T   P      gpu-speedbin@581                         $               T   x      socinfo-data1@7a0                      socinfo-data2@7e0                         gpu@13000000          )    mediatek,mt8188-mali arm,mali-valhall-jm                         @            w          0  2                   ~             }               	3job mmu gpu            x      
  speed-bin           )   y        w   E      E      E           =core0 core1 core2           E           Ookay            P   ,        T   )      clock-controller@13fbf000             mediatek,mt8188-mfgcfg                                         T   w      syscon@14000000           mediatek,mt8188-vppsys0 syscon                                           T   1      dma-controller@14001000           mediatek,mt8188-mdp3-rdma                                \              1         <     z         z         z         z         z              g   {           w   E           n   |                                   }      display@14002000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                                  1            n   |                 display@14004000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                @                   1   "        n   |      @          display@14005000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal                P                2      F                  1   
        w   E           n   |      P          display@14006000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                   1           n   |      `                %      display@14007000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                p                   1   #        n   |      p          display@14008000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                                2      I                  1   $        w   E           n   |                display@14009000          2    mediatek,mt8188-mdp3-ovl mediatek,mt8195-mdp3-ovl                                2      J                  1   %        w   E           n   |                  g   {         display@1400a000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                                   1           w   E           n   |                display@1400b000          2    mediatek,mt8188-mdp3-tcc mediatek,mt8195-mdp3-tcc                                   1           n   |                display@1400c000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot                              \              1           g   {           w   E           n   |                      +      mutex@1400f000            mediatek,mt8188-vpp-mutex                                2      P                  1           w   E           n   |                smi@14012000              mediatek,mt8188-smi-common-vpp                                  1      1           apb smi         w   E           T   ~      smi@14013000              mediatek,mt8188-smi-larb                0                   1      1           apb smi         w   E                         ~        T         iommu@14018000            mediatek,mt8188-iommu-vpp                      P            1           bclk            2      R               w   E           P                                     T   {      dma-controller@14f09000           mediatek,mt8188-mdp3-rdma                               \              3   
        g              w   E           n   |   	                        dma-controller@14f0a000           mediatek,mt8188-mdp3-rdma                               \              3           g   {           w   E           n   |   	                        display@14f0c000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                                3           n   |   	            display@14f0d000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                                3           n   |   	            display@14f0f000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                                  3   "        n   |   	            display@14f10000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                                   3   $        n   |   
             display@14f12000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal                                2      j                  3   #        w   E           n   |   
             display@14f13000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal               0                2      k                  3   %        w   E           n   |   
  0          display@14f15000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz               P                   3           n   |   
  P                      display@14f16000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz               `                   3           n   |   
  `                      display@14f18000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                                  3           n   |   
            display@14f19000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                                  3           n   |   
            display@14f1a000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge                                  3           w   E           n   |   
            display@14f1b000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge                                  3           w   E           n   |   
            display@14f1d000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                               2      u                  3           w   E           n   |   
            display@14f1e000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                               2      v                  3           w   E           n   |   
            display@14f21000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                                  3           w   E           n   |               display@14f22000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                                   3           w   E           n   |                display@14f24000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot             @                \              3           g              w   E           n   |     @                      display@14f25000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot             P                \              3           g   {           w   E           n   |     P                      clock-controller@14e00000             mediatek,mt8188-wpesys                                          T   >      clock-controller@14e02000             mediatek,mt8188-wpesys-vpp0                                       smi@14e04000              mediatek,mt8188-smi-larb                @                   >      >           apb smi         w   E                         ~        T         syscon@14f00000           mediatek,mt8188-vppsys1 syscon                                          T   3      mutex@14f01000            mediatek,mt8188-vpp-mutex                               2      {                  3   &        w   E           n   |   	            smi@14f02000              mediatek,mt8188-smi-larb                                    3      3           apb smi         w   E                                 T         smi@14f03000              mediatek,mt8188-smi-larb                0                   3      3           apb smi         w   E                         ~        T         clock-controller@15000000             mediatek,mt8188-imgsys                                         clock-controller@15110000              mediatek,mt8188-imgsys1-dip-top                                                  clock-controller@15130000             mediatek,mt8188-imgsys1-dip-nr                                                   clock-controller@15220000             mediatek,mt8188-imgsys-wpe1             "                                     clock-controller@15330000             mediatek,mt8188-ipesys              3                                     clock-controller@15520000             mediatek,mt8188-imgsys-wpe2             R                                     clock-controller@15620000             mediatek,mt8188-imgsys-wpe3             b                                     clock-controller@16000000             mediatek,mt8188-camsys                                           T   7      clock-controller@1604f000             mediatek,mt8188-camsys-rawa                                                   T   :      clock-controller@1606f000             mediatek,mt8188-camsys-yuva                                                   T   ;      clock-controller@1608f000             mediatek,mt8188-camsys-rawb                                                   T   8      clock-controller@160af000             mediatek,mt8188-camsys-yuvb             
                                      T   9      clock-controller@17200000             mediatek,mt8188-ccusys                                         video-decoder@18000000            mediatek,mt8188-vcodec-dec                              @                T                    `         g   {                       +              }   video-codec@10000             mediatek,mtk-vcodec-lat                               )   .   4        9   .   x            .   4   4      4      .   x        sel vdec lat top            2                   H  g   {     {     {     {     {     {     {     {     {          w   E         video-codec@25000             mediatek,mtk-vcodec-core                 P                )   .   4        9   .   x            .   4   5      5      .   x        sel vdec lat top            2                   X  g                                                               w   E            smi@1800d000              mediatek,mt8188-smi-larb                                    4       4            apb smi         w   E                         ~        T         clock-controller@1800f000             mediatek,mt8188-vdecsys-soc                                         T   4      smi@1802e000              mediatek,mt8188-smi-larb                                   5       5            apb smi         w   E                                 T         clock-controller@1802f000             mediatek,mt8188-vdecsys                                        T   5      clock-controller@1a000000             mediatek,mt8188-vencsys                                          T   =      smi@1a010000              mediatek,mt8188-smi-larb                                    =      =           apb smi         w   E                                 T         video-encoder@1a020000            mediatek,mt8188-vcodec-enc                                            +           )   .   3        9   .   p           =         	  venc_sel            2      a             X  g                                                               w   E              }      jpeg-encoder@1a030000         +    mediatek,mt8188-jpgenc mediatek,mtk-jpgenc                                  =           jpgenc          2      b                g                            w   E         jpeg-decoder@1a040000         .    mediatek,mt8188-jpgdec mediatek,mt2701-jpgdec                                   =       =           jpgdec-smi jpgdec           2      c             0  g                                      w   E         ovl@1c000000          2    mediatek,mt8188-disp-ovl mediatek,mt8195-disp-ovl                                    2            2      |               g              w   E           n   z             ports                        +       port@0                 endpoint                       T            port@1                endpoint                       T                  rdma@1c002000         4    mediatek,mt8188-disp-rdma mediatek,mt8195-disp-rdma                                  2           2      ~               g   {            w   E           n   z             ports                        +       port@0                 endpoint                       T            port@1                endpoint                       T                  color@1c003000        6    mediatek,mt8188-disp-color mediatek,mt8173-disp-color                0                   2           2                     w   E           n   z     0       ports                        +       port@0                 endpoint                       T            port@1                endpoint                       T                  ccorr@1c004000        6    mediatek,mt8188-disp-ccorr mediatek,mt8192-disp-ccorr                @                   2           2                     w   E           n   z     @       ports                        +       port@0                 endpoint                       T            port@1                endpoint                       T                  aal@1c005000          2    mediatek,mt8188-disp-aal mediatek,mt8183-disp-aal                P                   2           2                     w   E           n   z     P       ports                        +       port@0                 endpoint                       T            port@1                endpoint                       T                  gamma@1c006000        6    mediatek,mt8188-disp-gamma mediatek,mt8195-disp-gamma                `                   2           2                     w   E           n   z     `       ports                        +       port@0                 endpoint                       T            port@1                endpoint                       T                  dither@1c007000       8    mediatek,mt8188-disp-dither mediatek,mt8183-disp-dither              p                   2           2                     w   E           n   z     p       ports                        +       port@0                 endpoint                       T            port@1                endpoint                       T                  dsi@1c008000              mediatek,mt8188-dsi                                 2      2              engine digital hs           2                                dphy            w   E              2           Ookay                         +       panel@0                        +               Vdefault         d                                                       !          Ookay              ivo,t109nw41 himax,hx83102     port       endpoint                       T               ports                        +       port@0                 endpoint                       T            port@1                endpoint                       T                  dsc@1c009000          2    mediatek,mt8188-disp-dsc mediatek,mt8195-disp-dsc                                   2   
        2                     w   E           n   z               dsi@1c012000              mediatek,mt8188-dsi                                 2   	   2              engine digital hs           2                                dphy            w   E              2   	      	  Odisabled          merge0@1c014000       6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge               @                   2      <           merge merge_async           2                     w   E           n   z     @          dp-intf@1c015000              mediatek,mt8188-dp-intf             P                   2       2      -           pixel engine pll            2                     w   E         	  Odisabled          mutex@1c016000            mediatek,mt8188-disp-mutex              `                   2           2                     w   E           n   z     `              >      postmask@1c01a000         <    mediatek,mt8188-disp-postmask mediatek,mt8192-disp-postmask                                2           2                     w   E           n   z            ports                        +       port@0                 endpoint                       T            port@1                endpoint                       T                  syscon@1c01d000           mediatek,mt8188-vdosys0 syscon                                                       z               n   z                 T   2   port                         +       endpoint@0                                 T               smi@1c022000              mediatek,mt8188-smi-larb                                    2      2           apb smi         w   E                                  T         smi@1c023000              mediatek,mt8188-smi-larb                0                   2      2           apb smi         w   E                         ~        T         smi@1c024000              mediatek,mt8188-smi-common-vdo              @                   2      2           apb smi         w   E           T         iommu@1c028000            mediatek,mt8188-iommu-vdo                      P            2           bclk            2                     w   E           P                                  T         syscon@1c100000           mediatek,mt8188-vdosys1 syscon                                                        z              n   z                  T   <   port                         +       endpoint@1                                T               mutex@1c101000            mediatek,mt8188-disp-mutex                                 <           2                     w   E           n   z                         smi@1c102000              mediatek,mt8188-smi-larb                                    <       <            apb smi         w   E                                 T         smi@1c103000              mediatek,mt8188-smi-larb                0                   <      <           apb smi         w   E                         ~        T         rdma@1c104000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             @                   <           2                     g      @        w   E           \           n   z     @          rdma@1c105000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             P                   <           2                     g   {   `        w   E           \           n   z     P          rdma@1c106000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             `                   <           2                     g      A        w   E           \           n   z     `          rdma@1c107000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             p                   <           2                     g   {   a        w   E           \           n   z     p          rdma@1c108000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                                <           2                     g      B        w   E           \           n   z               rdma@1c109000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                                <           2                     g   {   b        w   E           \           n   z               rdma@1c10a000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                                <           2                     g      C        w   E           \           n   z               rdma@1c10b000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                                <           2                     g   {   c        w   E           \           n   z               merge@1c10c000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                                  <   	   <           merge merge_async           2                     w   E              <           n   z                  *      merge@1c10d000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                                  <   
   <           merge merge_async           2                     w   E              <           n   z                  *      merge@1c10e000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                                  <      <           merge merge_async           2                     w   E              <           n   z                  *      merge@1c10f000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                                  <      <           merge merge_async           2                     w   E              <           n   z                  *      merge@1c110000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                                   <      <           merge merge_async           2                     w   E              <           n   z                   >   ports                        +       port@0                       +                   endpoint@1                                T            port@1                       +                  endpoint@1                                T                  dpi@1c112000          (    mediatek,mt8188-dpi mediatek,mt8195-dpi                                 <   8   <      <   =        pixel engine pll            2                     w   E              <         	  Odisabled       ports                        +       port@0                 endpoint             port@1                endpoint                   dp-intf@1c113000              mediatek,mt8188-dp-intf             0                   <   :   <      -           pixel engine pll            2                     w   E           Ookay       ports                        +       port@0                       +                   endpoint@1                                T            port@1                       +                  endpoint@1                                T                  ethdr@1c114000        6    mediatek,mt8188-disp-ethdr mediatek,mt8195-disp-ethdr         p      @            P            p                                                              4  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       h     <   0   <   +   <   .   <   ,   <   /   <   -   <   <   <   1   <   2   <   3   <   4   <   5   .           mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          2      6               g   {   d   {   e        w   E         (     <   1   <   2   <   3   <   4   <   5      p  n   z     @       z     P       z     p       z            z            z            z            ports                        +       port@0                       +                   endpoint@1                                T            port@1                       +                  endpoint@1                                T                  padding@1c11d000              mediatek,mt8188-disp-padding                                   <           w   E           n   z               padding@1c11e000              mediatek,mt8188-disp-padding                                   <            w   E           n   z               padding@1c11f000              mediatek,mt8188-disp-padding                                   <   !        w   E           n   z               padding@1c120000              mediatek,mt8188-disp-padding                                    <   "        w   E           n   z                padding@1c121000              mediatek,mt8188-disp-padding                                   <   #        w   E           n   z               padding@1c122000              mediatek,mt8188-disp-padding                                    <   $        w   E           n   z                padding@1c123000              mediatek,mt8188-disp-padding                0                   <   %        w   E           n   z     0          padding@1c124000              mediatek,mt8188-disp-padding                @                   <   &        w   E           n   z     @          hdmi@1c300000             mediatek,mt8188-hdmi-tx                        0                     .   @   .   >   .   ?   3   .        bus hdcp hdcp24m hdmi-split         )   .   >        9   .   s        2                     w   E   	                   hdmi          	  Odisabled       i2c       2    mediatek,mt8188-hdmi-ddc mediatek,mt8195-hdmi-ddc              D      ports                        +       port@0                 endpoint             port@1                endpoint                   edp-tx@1c500000           mediatek,mt8188-edp-tx              P                 2                                dp_calibration_data         w   E           U        	  Odisabled          dp-tx@1c600000            mediatek,mt8188-dp-tx               `                 2                                dp_calibration_data         w   E           U          Ookay            Vdefault         d                       T      ports                        +       port@0                 endpoint                       T            port@1                endpoint            f                               backlight-lcd0            pwm-backlight           q                @           +                                                     T         chosen          serial0:115200n8          dmic-codec            dmic-codec                        d      memory@40000000         wmemory              @                 regulator-pp1800-ldo-z1           regulator-fixed         >pp1800_ldo_z1                             M w@        e w@            j      regulator-pp3300-s3           regulator-fixed       
  >pp3300_s3                             M 2Z        e 2Z            j        T   Y      regulator-pp3300-z1           regulator-fixed       
  >pp3300_z1                             M 2Z        e 2Z                    T   j      regulator-pp3300-wlan             regulator-fixed         >pp3300_wlan                  M 2Z        e 2Z                    +               d           Vdefault             j      regulator-pp4200-s5           regulator-fixed       
  >pp4200_s5                             M @@        e @@                  regulator-pp5000-z1           regulator-fixed       
  >pp5000_z1                             M LK@        e LK@                    T         regulator-pp5000-usb-vbus             regulator-fixed         >pp5000_usb_vbus         M LK@        e LK@                    +                           T   Z      regulator-ppvar-sys           regulator-fixed       
  >ppvar_sys                             T         regulator-ppvar-mipi-disp-avdd            regulator-fixed         >ppvar_mipi_disp_avdd                        +               Vdefault         d                       T         regulator-ppvar-mipi-disp-avee            regulator-fixed         >ppvar_mipi_disp_avee            }  '                    +               Vdefault         d                       T         reserved-memory                      +            T   memory@50000000           shared-dma-pool             P                   #        T   C      memory@55000000           shared-dma-pool             U       @        memory@60000000           shared-dma-pool             `                   #        T   K      memory@60f00000           shared-dma-pool             `                  #        T   G      memory@61000000           shared-dma-pool             a                   #        T   J            	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dpi1 dsc0 ethdr0 gce0 gce1 merge0 merge1 merge2 merge3 merge4 merge5 mutex0 mutex1 padding0 padding1 padding2 padding3 padding4 padding5 padding6 padding7 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 dsi0 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 mmc0 serial0 device_type reg enable-method clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-output-names opp-shared opp-hz opp-microvolt opp-supported-hw interrupts mediatek,platform status pinctrl-names pinctrl-0 pinctrl-1 pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 mediatek,adsp audio-routing link-name dai-format mediatek,clk-provider sound-dai polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux bias-pull-down input-enable drive-strength output-high bias-disable output-low bias-pull-up #power-domain-cells domain-supply clocks clock-names mediatek,infracfg mediatek,disable-extrst #sound-dai-cells interrupts-extended #io-channel-cells mediatek,dmic-mode mediatek,mic-type-0 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread regulator-microvolt-offset assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells memory-region power-domains resets reset-names mediatek,topckgen mediatek,etdm-out1-cowork-source mediatek,etdm-in2-cowork-source mboxes mbox-names spi-max-frequency google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells phys wakeup-source mediatek,syscon-wakeup dr_mode vusb33-supply vbus-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,blen snps,rd_osr_lmt snps,wr_osr_lmt snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,priority snps,weight bus-width cap-mmc-highspeed cap-mmc-hw-reset hs400-ds-delay mmc-hs200-1_8v mmc-hs400-1_8v mmc-hs400-enhanced-strobe no-sd no-sdio non-removable supports-cqe vmmc-supply vqmmc-supply clock-div sound-name-prefix reset-gpios everest,jack-pol everest,interrupt-clk usb2-lpm-disable bus-range linux,pci-domain interrupt-map interrupt-map-mask iommu-map iommu-map-mask phy-names #phy-cells mediatek,ibias mediatek,ibias_up drive-strength-microamp bits operating-points-v2 power-domain-names mali-supply #dma-cells iommus mediatek,gce-client-reg mediatek,gce-events mediatek,scp mediatek,larb-id mediatek,smi mediatek,larbs remote-endpoint enable-gpios backlight avdd-supply avee-supply pp1800-supply rotation mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz data-lanes brightness-levels default-brightness-level num-interpolated-steps power-supply pwms stdout-path num-channels wakeup-delay-ms regulator-boot-on vin-supply enable-active-high gpio no-map 