     8    (            
s p                             $    mediatek,mt8188-evb mediatek,mt8188                                  +         !   7MediaTek MT8188 evaluation board       aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dpi@1c112000            T/soc/dsc@1c009000            Y/soc/ethdr@1c114000          `/soc/mailbox@10320000            e/soc/mailbox@10330000            j/soc/merge0@1c014000             q/soc/merge@1c10c000          x/soc/merge@1c10d000          /soc/merge@1c10e000          /soc/merge@1c10f000          /soc/merge@1c110000          /soc/mutex@1c016000          /soc/mutex@1c101000          /soc/padding@1c11d000            /soc/padding@1c11e000            /soc/padding@1c11f000            /soc/padding@1c120000            /soc/padding@1c121000            /soc/padding@1c122000            /soc/padding@1c123000            /soc/padding@1c124000            /soc/rdma@1c104000           /soc/rdma@1c105000           /soc/rdma@1c106000          /soc/rdma@1c107000          /soc/rdma@1c108000          !/soc/rdma@1c109000          ,/soc/rdma@1c10a000          7/soc/rdma@1c10b000          B/soc/serial@11001100            J/soc/i2c@11280000           O/soc/i2c@11e00000           T/soc/i2c@11281000           Y/soc/i2c@11282000           ^/soc/i2c@11e01000           c/soc/i2c@11ec0000           h/soc/i2c@11ec1000           m/soc/mmc@11230000         cpus                         +       cpu@0           rcpu           arm,cortex-a55          ~            psci            w5                                               @                                 @                              ,               @           O   	      cpu@100         rcpu           arm,cortex-a55          ~           psci            w5                                               @                                 @                              ,               @           O   
      cpu@200         rcpu           arm,cortex-a55          ~           psci            w5                                               @                                 @                              ,               @           O         cpu@300         rcpu           arm,cortex-a55          ~           psci            w5                                               @                                 @                              ,               @           O         cpu@400         rcpu           arm,cortex-a55          ~           psci            w5                                               @                                 @                              ,               @           O         cpu@500         rcpu           arm,cortex-a55          ~           psci            w5                                               @                                 @                              ,               @           O         cpu@600         rcpu           arm,cortex-a78          ~           psci                                                            @                                 @                              ,              @           O         cpu@700         rcpu           arm,cortex-a78          ~           psci                                                            @                                 @                              ,              @           O         cpu-map    cluster0       core0           W   	      core1           W   
      core2           W         core3           W         core4           W         core5           W         core6           W         core7           W               idle-states         [psci       cpu-off-l             arm,idle-state          h                       2           _          D        O         cpu-off-b             arm,idle-state          h                       -                             O         cluster-off-l             arm,idle-state          h                     7                     H        O         cluster-off-b             arm,idle-state          h                     2                             O            l2-cache0             cache                                    @                                       O         l2-cache1             cache                                    @                                       O         l3-cache              cache                                     @                            O            oscillator-13m            fixed-clock                      ]@        clk13m          O   3      oscillator-26m            fixed-clock                             clk26m          O   5      oscillator-32k            fixed-clock                                clk32k        opp-table-gpu             operating-points-v2                  O   [   opp-390000000               >                          opp-431000000                                         opp-473000000               1h@         	'                 opp-515000000               F         	X                 opp-556000000               !#          	h                 opp-598000000               #         	<                 opp-640000000               &%          	                 opp-670000000               'c         
                 opp-700000000               )'          
L                 opp-730000000               +         
}                 opp-760000000               -L          
`                 opp-790000000               /q         
4                 opp-835000000               1         (r                 opp-880000000               4s          q                 opp-915000000               6         X                 opp-915000000-5             6                    0      opp-915000000-6             6         q           p      opp-950000000               8ـ         5                  opp-950000000-5             8ـ         X           0      opp-950000000-6             8ـ         q           p         pmu-a55           arm,cortex-a55-pmu                      -                  pmu-a78           arm,cortex-a78-pmu                      -                  psci              arm,psci-1.0            smc       sound           8         	  Jdisabled          thermal-zones      cpu-little0-thermal         Q          _           u          trips      trip-alert0          L                  ypassive         O         trip-alert1          s                  yhot       trip-crit                              	  ycritical             cooling-maps       map0                     H     	   
                        cpu-little1-thermal         Q          _           u         trips      trip-alert0          L                  ypassive         O         trip-alert1          s                  yhot       trip-crit                              	  ycritical             cooling-maps       map0                     H     	   
                        cpu-little2-thermal         Q          _           u         trips      trip-alert0          L                  ypassive         O         trip-alert1          s                  yhot       trip-crit                              	  ycritical             cooling-maps       map0                     H     	   
                        cpu-little3-thermal         Q          _           u         trips      trip-alert0          L                  ypassive         O         trip-alert1          s                  yhot       trip-crit                              	  ycritical             cooling-maps       map0                     H     	   
                        cpu-big0-thermal            Q          _   d        u         trips      trip-alert0          L                  ypassive         O         trip-alert1          s                  yhot       trip-crit                              	  ycritical             cooling-maps       map0                                         cpu-big1-thermal            Q          _   d        u         trips      trip-alert0          L                  ypassive         O         trip-alert1          s                  yhot       trip-crit                              	  ycritical             cooling-maps       map0                                         apu-thermal         Q          _           u          trips      trip-alert0          L                  ypassive       trip-alert1          s                  yhot       trip-crit                              	  ycritical                gpu-thermal         Q          _           u         trips      trip-alert0          L                  ypassive         O         trip-alert1          s                  yhot       trip-crit                              	  ycritical             cooling-maps       map0                                      gpu1-thermal            Q          _           u         trips      trip-alert0          L                  ypassive         O         trip-alert1          s                  yhot       trip-crit                              	  ycritical             cooling-maps       map0                                      adsp-thermal            Q          _           u         trips      trip-alert0          L                  ypassive       trip-alert1          s                  yhot       trip-crit                              	  ycritical                vdo-thermal         Q          _           u         trips      trip-alert0          L                  ypassive       trip-alert1          s                  yhot       trip-crit                              	  ycritical                infra-thermal           Q          _           u         trips      trip-alert0          L                  ypassive       trip-alert1          s                  yhot       trip-crit                              	  ycritical                cam1-thermal            Q          _           u         trips      trip-alert0          L                  ypassive       trip-alert1          s                  yhot       trip-crit                              	  ycritical                cam2-thermal            Q          _           u         trips      trip-alert0          L                  ypassive       trip-alert1          s                  yhot       trip-crit                              	  ycritical                   timer             arm,armv8-timer                   @  -                                             
                ]@      soc                      +             simple-bus                                             performance-controller@11bc10             mediatek,cpufreq-hw          ~                 0                          O         interrupt-controller@c000000              arm,gic-v3                                                      ~                                    -      	               O      ppi-partitions     interrupt-partition-0              	   
                    O         interrupt-partition-1                         O               syscon@10000000            mediatek,mt8188-topckgen syscon         ~                                 O   "      syscon@10001000       #    mediatek,mt8188-infracfg-ao syscon          ~                                           O   #      syscon@10003000           mediatek,mt8188-pericfg syscon          ~     0                           O   A      pinctrl@10005000              mediatek,mt8188-pinctrl       `  ~     P                                                                               0  (iocfg0 iocfg_rm iocfg_lt iocfg_lm iocfg_rt eint          2        B           N                                -                                 O       adsp-uart-pins     pins-tx-rx          Z  #  $         i2c0-pins           O   J   pins-bus            Z  8  7        a            i2c1-pins           O   T   pins-bus            Z  :  9        a            i2c2-pins           O   K   pins-bus            Z  <  ;        a            i2c3-pins           O   L   pins-bus            Z  >  =        a            i2c4-pins           O   U   pins-bus            Z  @  ?        a            i2c5-pins           O   W   pins-bus            Z  B  A        a            i2c6-pins           O   X   pins-bus            Z  D  C        a            mmc0-default-pins           O   G   pins-cmd-dat          $  Z                           n        {           a   e      pins-clk            Z          {              f      pins-rst            Z          {           a   e         mmc0-uhs-pins           O   H   pins-cmd-dat          $  Z                           n        {           a   e      pins-clk-ds         Z            {              f      pins-rst            Z          {           a   e         nor-pins            O   R   pins-io-ck          Z    }                 pins-io-cs          Z  ~             a         spi0-pins           O   ;   pins-spi            Z  E  F  G  H                  spi1-pins           O   =   pins-spi            Z  K  L  M  N                  spi2-pins           O   >   pins-spi            Z  O  P  Q  R                  uart0-pins          O   :   pins-rx-tx          Z              a            syscon@10006000       )    mediatek,mt8188-scpsys syscon simple-mfd            ~     `           power-controller          !    mediatek,mt8188-power-controller                         +                       O   6   power-domain@0          ~                         +                  power-domain@1          ~              !      "           mfg alt            #                     +                  power-domain@2          ~                     power-domain@3          ~                     power-domain@4          ~                           power-domain@15         ~              "      "      "      "   
   "   3   "   4   "   =   "      "      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $            top cam ccu img venc vdec wpe cfgck cfgxo ss-sram-cmn ss-sram-v0l0 ss-sram-v0l1 ss-sram-ve0 ss-sram-ve1 ss-sram-ifa ss-sram-cam ss-sram-v1l5 ss-sram-v1l6 ss-sram-rdr ss-iommu ss-imgcam ss-emi ss-subcmn-rdr ss-rsi ss-cmn-l4 ss-vdec1 ss-wpe ss-cvdo-ve1             #                     +                  power-domain@16         ~         H     "      "      %      %      %      %      %      %      %         A  cfgck cfgxo ss-gals ss-cmn ss-emi ss-iommu ss-larb ss-rsi ss-bus               #                     +                  power-domain@20         ~         0     "      "      &      &      &      &         8  cfgck cfgxo ss-vpp1-g5 ss-vpp1-g6 ss-vpp1-l5 ss-vpp1-l6            #                  power-domain@22         ~              '            ss-vdec1-soc-l1            #                     +                  power-domain@23         ~              (            ss-vdec2-l1            #                     power-domain@29         ~               "      "      "   	   "           cam ccu bus cfgck              #                     +                  power-domain@30         ~         (     )       )      )      )      )         6  ss-cam-l13 ss-cam-l14 ss-cam-mm0 ss-cam-mm1 ss-camsys              #                     +                  power-domain@32         ~               )      *       +          $  ss-camb-sub ss-camb-raw ss-camb-yuv                   power-domain@31         ~              )      ,       -          $  ss-cama-sub ss-cama-raw ss-cama-yuv                         power-domain@17         ~         (     "      "      .       .      .         &  cfgck cfgxo ss-larb2 ss-larb3 ss-gals              #                     +                  power-domain@9          ~   	           "   @   "   ?      	  bus hdcp               #                  power-domain@18         ~              #                  power-domain@19         ~              #                     power-domain@24         ~               /       /      /      /         0  ss-ve1-larb ss-ve1-core ss-ve1-gals ss-ve1-sram            #                  power-domain@21         ~              0      0           ss-wpe-l7 ss-wpe-l7pce             #                        power-domain@5          ~              #           1           ss-pextp-fmem                     power-domain@7          ~              "   0   "   1        seninf0 seninf1                   power-domain@6          ~                     power-domain@10         ~   
           "   E   "   D      	  bus main               #                     +                  power-domain@11         ~              #                     +                  power-domain@14         ~              "   F        asm            #                  power-domain@13         ~              "   S   "      2            a1sys intbus adspck            #                  power-domain@12         ~              #                        power-domain@8          ~              1         	  ethermac               #                        watchdog@10007000             mediatek,mt8188-wdt         ~     p                                    O   7      syscon@1000c000       "    mediatek,mt8188-apmixedsys syscon           ~                                O   !      timer@10017000        ,    mediatek,mt8188-timer mediatek,mt6765-timer         ~    p                -      	                  3      pwrap@10024000        3    mediatek,mt8188-pwrap mediatek,mt8195-pwrap syscon          ~    @                (pwrap           -                         #      #          	  spi wrap       pmic              mediatek,mt6359                                                     adc           mediatek,mt6359-auxadc                   audio-codec           mediatek,mt6359-codec         regulators            mediatek,mt6359-regulator      buck_vs1            .vs1         = 5         U !        m                   buck_vgpu11         .vgpu11          =         U 7                  m                                    buck_vmodem         .vmodem          =         U           *        m         buck_vpu            .vpu         =         U 7                  m                                    buck_vcore          .vcore           =         U                    m                                    buck_vs2            .vs2         = 5         U j         m                   buck_vpa            .vpa         =          U 7        m  ,      buck_vproc2         .vproc2          =         U 7          L        m                           buck_vproc1         .vproc1          =         U 7          L        m                           buck_vcore_sshub            .vcore_sshub         =         U 7      buck_vgpu11_sshub           .vgpu11_sshub            =         U 7      ldo_vaud18          .vaud18          = w@        U w@        m         ldo_vsim1           .vsim1           =         U /M`      ldo_vibr            .vibr            = O        U 2Z      ldo_vrf12           .vrf12           =         U                 ldo_vusb            .vusb            = -        U -        m                 ldo_vsram_proc2         .vsram_proc2         =          U           L        m                  ldo_vio18           .vio18           =         U         m                 ldo_vcamio          .vcamio          =         U       ldo_vcn18           .vcn18           = w@        U w@        m         ldo_vfe28           .vfe28           = *        U *        m   x      ldo_vcn13           .vcn13           =         U        ldo_vcn33_1_bt          .vcn33_1_bt          = *        U 5g      ldo_vcn33_1_wifi            .vcn33_1_wifi            = *        U 5g      ldo_vaux18          .vaux18          = w@        U w@        m                  ldo_vsram_others            .vsram_others            =          U                   m         ldo_vefuse          .vefuse          =         U       ldo_vxo22           .vxo22           = w@        U !               ldo_vrfck           .vrfck           = `        U       ldo_vrfck_1         .vrfck           =         U j       ldo_vbif28          .vbif28          = *        U *        m         ldo_vio28           .vio28           = *        U 2Z               ldo_vemc            .vemc            = ,@         U 2Z      ldo_vemc_1          .vemc            = &%        U 2Z        O   E      ldo_vcn33_2_bt          .vcn33_2_bt          = *        U 5g      ldo_vcn33_2_wifi            .vcn33_2_wifi            = *        U 5g      ldo_va12            .va12            = O        U                 ldo_va09            .va09            = 5         U O      ldo_vrf18           .vrf18           =         U P      ldo_vsram_md          	  .vsram_md            =          U           *        m         ldo_vufs            .vufs            =         U         O   F      ldo_vm18            .vm18            =         U                ldo_vbbck           .vbbck           =         U O      ldo_vsram_proc1         .vsram_proc1         =          U           L        m                  ldo_vsim2           .vsim2           =         U /M`      ldo_vsram_others_sshub          .vsram_others_sshub          =          U          rtc           mediatek,mt6358-rtc             spmi@10027000         *    mediatek,mt8188-spmi mediatek,mt8195-spmi            ~    p                            (pmif spmimst               "   8           "              #      #       "   8      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux       iommu@10315000            mediatek,mt8188-iommu-infra         ~    1P                -                                O   P      mailbox@10320000              mediatek,mt8188-gce         ~    2        @         -                                    #           O   \      mailbox@10330000              mediatek,mt8188-gce         ~    3        @         -                                    #           O   ^      scp@10720000              mediatek,mt8188-scp-dual            ~    r                 (cfg                      +                   P             Jokay       scp@0             mediatek,scp-core           ~               (sram            -                     Jokay            
   4        O   _      scp@d0000             mediatek,scp-core           ~             (sram            -                   	  Jdisabled             audio-controller@10b10000             mediatek,mt8188-afe         ~                        "   S           "              5   !   	   !   
   "      "      "      "      "      "   S   "      "       "   E   "   Q   "   M   "   N   "   O   "   P   2       "      "      "      "   T   "   R        clk26m apll1 apll2 apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 top_a1sys_hp top_aud_intbus top_audio_h top_audio_local_bus top_dptx top_i2so1 top_i2so2 top_i2si1 top_i2si2 adsp_audio_26m apll1_d4 apll2_d4 apll12_div4 top_a2sys top_aud_iec          -      6                  6           &   7         	  -audiosys               #        9   "      	  Jdisabled            O         adsp@10b80000             mediatek,mt8188-dsp       @  ~                                                           (cfg sram sec bus               "   D           "   D   "   E        audiodsp adsp_bus           K   8   9        Rrx tx              6         	  Jdisabled          mailbox@10b86100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox         ~    a                -                                 O   8      mailbox@10b87100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox         ~    q                -                                 O   9      clock-controller@10b91100             mediatek,mt8188-adsp-audio26m           ~                               O   2      serial@11001100       *    mediatek,mt8188-uart mediatek,mt6577-uart           ~                     -                         5   #         	  baud bus            Jokay            ]default         k   :      serial@11001200       *    mediatek,mt8188-uart mediatek,mt6577-uart           ~                     -                         5   #         	  baud bus          	  Jdisabled          serial@11001300       *    mediatek,mt8188-uart mediatek,mt6577-uart           ~                     -                         5   #         	  baud bus          	  Jdisabled          serial@11001400       *    mediatek,mt8188-uart mediatek,mt6577-uart           ~                     -                        5   #         	  baud bus          	  Jdisabled          adc@11002000          .    mediatek,mt8188-auxadc mediatek,mt8173-auxadc           ~                         #           main                       Jokay          syscon@11003000       "    mediatek,mt8188-pericfg-ao syscon           ~     0                           O   1      spi@1100a000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~                     -                         "   y   "      #           parent-clk sel-clk spi-clk          Jokay            ]default         k   ;      thermal-sensor@1100b000           mediatek,mt8188-lvts-ap         ~                     -                         #           &   #           u   <        lvts-calib-data-1                      O         pwm@1100e000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm           ~                        "   '   #   /        main mm         -                               	  Jdisabled          pwm@1100f000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm           ~                        "   (   #   F        main mm         -                              	  Jdisabled          spi@11010000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~                     -                         "   y   "      #   2        parent-clk sel-clk spi-clk          Jokay            ]default         k   =      spi@11012000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~                     -                         "   y   "      #   3        parent-clk sel-clk spi-clk          Jokay            ]default         k   >      spi@11013000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~    0                -                         "   y   "      #   4        parent-clk sel-clk spi-clk        	  Jdisabled          spi@11018000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~                    -                         "   y   "      #   8        parent-clk sel-clk spi-clk        	  Jdisabled          spi@11019000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~                    -                         "   y   "      #   9        parent-clk sel-clk spi-clk        	  Jdisabled          usb@11201000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ~            -     >              	  (mac ippc                                 ?                      +           -                         "   )           "   v           1   	   "      1   
        sys_ck ref_ck mcu_ck               ?      @                       A  h         	  Jdisabled       usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ~                       (mac         -                         "   *           "   v           1   
        sys_ck          Jokay             ethernet@11021000         ;    mediatek,mt8188-gmac mediatek,mt8195-gmac snps,dwmac-5.10a          ~           @         -                     macirq        0     1       1      "   A   "   B   "   C   1         .  axi apb mac_main ptp_ref rmii_internal mac_cg              "   A   "   B   "   C           "      "      "              6              #           B           C        !   D        4           ?           J          	  Jdisabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config           W                                 a           q           O   B      rx-queues-config                                O   C   queue0                             queue1                             queue2                             queue3                                tx-queues-config                                O   D   queue0                               	         queue1                              	         queue2                              	         queue3                              	               mmc@11230000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ~    #                                                           "      #      #      #   M      !  source hclk source_cg crypto_clk            Jokay                        H        .          <         N         ]         l         y                                      E           F        ]default state_uhs           k   G           H      mmc@11240000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ~    $                                                          "      #      #   $        source hclk source_cg              "              "         	  Jdisabled          mmc@11250000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ~    %                                                          "      #      #   A        source hclk source_cg              "              "         	  Jdisabled          thermal-sensor@11278000           mediatek,mt8188-lvts-mcu            ~    '                -                         #           &   #            u   <        lvts-calib-data-1                      O         i2c@11280000              mediatek,mt8188-i2c          ~    (             "                -                                    I       #   7      	  main dma                         +            Jokay            ]default         k   J               i2c@11281000              mediatek,mt8188-i2c          ~    (            "               -                                    I      #   7      	  main dma                         +            Jokay            ]default         k   K               i2c@11282000              mediatek,mt8188-i2c          ~    (             "               -                                    I      #   7      	  main dma                         +            Jokay            ]default         k   L               clock-controller@11283000             mediatek,mt8188-imp-iic-wrap-c          ~    (0                           O   I      usb@112a1000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ~    *       -    *>              	  (mac ippc                        *        ?                      +           -                        "   -           "   v           1      "      1           sys_ck ref_ck mcu_ck               M                       A  p         	  Jdisabled       usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ~                       (mac         -                        "   .           "   v           1           sys_ck          Jokay             usb@112b1000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ~    +       -    +>              	  (mac ippc                        +        ?                      +           -                        "   ,           "   v           1      "      1           sys_ck ref_ck mcu_ck               N                       A  `         	  Jdisabled       usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ~                       (mac         -                        "   +           "   v           1           sys_ck          Jokay             pcie@112f0000         *    mediatek,mt8188-pcie mediatek,mt8192-pcie           ~    /                	  (pcie-mac                                                             rpci                                  +         0     #   L   #   #   #   &   #   +   #   C   1         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                     -                   `                    O                      O                     O                     O                                  	       P              	               Q         	  	(pcie-phy               6           &   7           -mac       	  Jdisabled       interrupt-controller                                             O   O         spi@1132c000          (    mediatek,mt8188-nor mediatek,mt8186-nor         ~    2                   "   X   1      1           spi sf axi             "   X        -      9                            +            Jokay            ]default         k   R   flash@0           jedec,spi-nor           ~            	2u          t-phy@11c20700        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                                            +              6         	  Jdisabled       pcie-phy@0          ~                  "           ref         	D           O   Q         hdmi-phy@11d5f000         2    mediatek,mt8188-hdmi-phy mediatek,mt8195-hdmi-phy           ~                       #           pll_ref         hdmi_txpll                      	D            	O   
        	^         	  Jdisabled            O   z      dsi-phy@11c80000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx         ~                        5        mipi_tx0_pll                        	D          	  Jdisabled            O   s      dsi-phy@11c90000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx         ~                        5        mipi_tx0_pll                        	D          	  Jdisabled            O   t      i2c@11e00000              mediatek,mt8188-i2c          ~                 "                -                                    S       #   7      	  main dma                         +            Jokay            ]default         k   T               i2c@11e01000              mediatek,mt8188-i2c          ~                "               -                                    S      #   7      	  main dma                         +            Jokay            ]default         k   U               clock-controller@11e02000             mediatek,mt8188-imp-iic-wrap-w          ~                                O   S      t-phy@11e30000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                Jokay       usb-phy@0           ~                  "      !           ref da_ref          	D           O   N         t-phy@11e40000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                Jokay       usb-phy@0           ~                  "      !           ref da_ref          	D           O   ?      usb-phy@700         ~                 !      5        ref da_ref          	D           O   @         t-phy@11e80000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                Jokay       usb-phy@0           ~                  "      !           ref da_ref          	D           O   M         i2c@11ec0000              mediatek,mt8188-i2c          ~                 "               -                                    V       #   7      	  main dma                         +            Jokay            ]default         k   W               i2c@11ec1000              mediatek,mt8188-i2c          ~                "                -                                    V      #   7      	  main dma                         +            Jokay            ]default         k   X               clock-controller@11ec2000              mediatek,mt8188-imp-iic-wrap-en         ~                                O   V      efuse@11f20000        ,    mediatek,mt8188-efuse mediatek,mt8186-efuse         ~                                  +      dp-calib@1a0            ~             O   {      lvts1-calib@1ac         ~     @        O   <      gpu-speedbin@581            ~             	p               O   Z      socinfo-data1@7a0           ~           socinfo-data2@7e0           ~              gpu@13000000          )    mediatek,mt8188-mali arm,mali-valhall-jm            ~             @            Y          0  -                   ~             }               job mmu gpu         u   Z      
  speed-bin           	u   [           6      6      6           	core0 core1 core2           @         	  Jdisabled            O         clock-controller@13fbf000             mediatek,mt8188-mfgcfg          ~                               O   Y      syscon@14000000           mediatek,mt8188-vppsys0 syscon          ~                                 O   $      dma-controller@14001000           mediatek,mt8188-mdp3-rdma           ~                     	              $         <  K   \         \         \         \         \              	   ]              6           	   ^                  	              	   _      display@14002000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ~                         $            	   ^                 display@14004000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ~     @                   $   "        	   ^      @          display@14005000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ~     P                -      F                  $   
           6           	   ^      P          display@14006000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ~     `                   $           	   ^      `            	    %      display@14007000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ~     p                   $   #        	   ^      p          display@14008000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ~                     -      I                  $   $           6           	   ^                display@14009000          2    mediatek,mt8188-mdp3-ovl mediatek,mt8195-mdp3-ovl           ~                     -      J                  $   %           6           	   ^                  	   ]         display@1400a000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ~                        $              6           	   ^                display@1400b000          2    mediatek,mt8188-mdp3-tcc mediatek,mt8195-mdp3-tcc           ~                        $           	   ^                display@1400c000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ~                     	              $           	   ]              6           	   ^                  	    +      mutex@1400f000            mediatek,mt8188-vpp-mutex           ~                     -      P                  $              6           	   ^                smi@14012000              mediatek,mt8188-smi-common-vpp          ~                        $      $           apb smi            6           O   `      smi@14013000              mediatek,mt8188-smi-larb            ~    0                   $      $           apb smi            6           	           	   `        O   c      iommu@14018000            mediatek,mt8188-iommu-vpp           ~           P            $           bclk            -      R                  6                      
   a   b   c   d   e   f        O   ]      dma-controller@14f09000           mediatek,mt8188-mdp3-rdma           ~                    	              &   
        	   g              6           	   ^   	              	          dma-controller@14f0a000           mediatek,mt8188-mdp3-rdma           ~                    	              &           	   ]              6           	   ^   	              	          display@14f0c000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ~                       &           	   ^   	            display@14f0d000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ~                       &           	   ^   	            display@14f0f000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ~                       &   "        	   ^   	            display@14f10000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ~                        &   $        	   ^   
             display@14f12000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ~                     -      j                  &   #           6           	   ^   
             display@14f13000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ~    0                -      k                  &   %           6           	   ^   
  0          display@14f15000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ~    P                   &           	   ^   
  P            	          display@14f16000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ~    `                   &           	   ^   
  `            	          display@14f18000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ~                       &           	   ^   
            display@14f19000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ~                       &           	   ^   
            display@14f1a000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge           ~                       &              6           	   ^   
            display@14f1b000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge           ~                       &              6           	   ^   
            display@14f1d000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ~                    -      u                  &              6           	   ^   
            display@14f1e000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ~                    -      v                  &              6           	   ^   
            display@14f21000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ~                       &              6           	   ^               display@14f22000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ~                        &              6           	   ^                display@14f24000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ~    @                	              &           	   g              6           	   ^     @            	          display@14f25000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ~    P                	              &           	   ]              6           	   ^     P            	          clock-controller@14e00000             mediatek,mt8188-wpesys          ~                                O   0      clock-controller@14e02000             mediatek,mt8188-wpesys-vpp0         ~                              smi@14e04000              mediatek,mt8188-smi-larb            ~    @                   0      0           apb smi            6           	           	   `        O   e      syscon@14f00000           mediatek,mt8188-vppsys1 syscon          ~                                O   &      mutex@14f01000            mediatek,mt8188-vpp-mutex           ~                    -      {                  &   &           6           	   ^   	            smi@14f02000              mediatek,mt8188-smi-larb            ~                        &      &           apb smi            6           	           	   h        O   w      smi@14f03000              mediatek,mt8188-smi-larb            ~    0                   &      &           apb smi            6           	           	   `        O   d      clock-controller@15000000             mediatek,mt8188-imgsys          ~                               clock-controller@15110000              mediatek,mt8188-imgsys1-dip-top         ~                                         clock-controller@15130000             mediatek,mt8188-imgsys1-dip-nr          ~                                         clock-controller@15220000             mediatek,mt8188-imgsys-wpe1         ~    "                                     clock-controller@15330000             mediatek,mt8188-ipesys          ~    3                                     clock-controller@15520000             mediatek,mt8188-imgsys-wpe2         ~    R                                     clock-controller@15620000             mediatek,mt8188-imgsys-wpe3         ~    b                                     clock-controller@16000000             mediatek,mt8188-camsys          ~                                 O   )      clock-controller@1604f000             mediatek,mt8188-camsys-rawa         ~                                          O   ,      clock-controller@1606f000             mediatek,mt8188-camsys-yuva         ~                                          O   -      clock-controller@1608f000             mediatek,mt8188-camsys-rawb         ~                                          O   *      clock-controller@160af000             mediatek,mt8188-camsys-yuvb         ~    
                                      O   +      clock-controller@17200000             mediatek,mt8188-ccusys          ~                               video-decoder@18000000            mediatek,mt8188-vcodec-dec           ~                   @                                    `         	   ]                       +           	   _   video-codec@10000             mediatek,mtk-vcodec-lat         ~                         "   4           "   x            "   4   '      '      "   x        sel vdec lat top            -                   H  	   ]     ]     ]     ]     ]     ]     ]     ]     ]             6         video-codec@25000             mediatek,mtk-vcodec-core            ~     P                   "   4           "   x            "   4   (      (      "   x        sel vdec lat top            -                   X  	   g     g     g     g     g     g     g     g     g     g     g             6            smi@1800d000              mediatek,mt8188-smi-larb            ~                        '       '            apb smi            6           	           	   `        O   f      clock-controller@1800f000             mediatek,mt8188-vdecsys-soc         ~                                O   '      smi@1802e000              mediatek,mt8188-smi-larb            ~                       (       (            apb smi            6           	           	   h        O   y      clock-controller@1802f000             mediatek,mt8188-vdecsys         ~                               O   (      clock-controller@1a000000             mediatek,mt8188-vencsys         ~                                 O   /      smi@1a010000              mediatek,mt8188-smi-larb            ~                        /      /           apb smi            6           	           	   h        O   x      video-encoder@1a020000            mediatek,mt8188-vcodec-enc          ~                                  +              "   3           "   p           /         	  venc_sel            -      a             X  	   g     g     g     g     g     g     g     g     g     g     g             6           	   _      jpeg-encoder@1a030000         +    mediatek,mt8188-jpgenc mediatek,mtk-jpgenc          ~                        /           jpgenc          -      b                	   g     g     g     g             6         jpeg-decoder@1a040000         .    mediatek,mt8188-jpgdec mediatek,mt2701-jpgdec           ~                        /       /           jpgdec-smi jpgdec           -      c             0  	   g     g     g     g     g     g             6         ovl@1c000000          2    mediatek,mt8188-disp-ovl mediatek,mt8195-disp-ovl           ~                         %            -      |               	   g              6           	   \             ports                        +       port@0          ~       endpoint             port@1          ~      endpoint            
   i        O   j               rdma@1c002000         4    mediatek,mt8188-disp-rdma mediatek,mt8195-disp-rdma         ~                         %           -      ~               	   ]               6           	   \             ports                        +       port@0          ~       endpoint            
   j        O   i         port@1          ~      endpoint            
   k        O   l               color@1c003000        6    mediatek,mt8188-disp-color mediatek,mt8173-disp-color           ~     0                   %           -                        6           	   \     0       ports                        +       port@0          ~       endpoint            
   l        O   k         port@1          ~      endpoint            
   m        O   n               ccorr@1c004000        6    mediatek,mt8188-disp-ccorr mediatek,mt8192-disp-ccorr           ~     @                   %           -                        6           	   \     @       ports                        +       port@0          ~       endpoint            
   n        O   m         port@1          ~      endpoint            
   o        O   p               aal@1c005000          2    mediatek,mt8188-disp-aal mediatek,mt8183-disp-aal           ~     P                   %           -                        6           	   \     P       ports                        +       port@0          ~       endpoint            
   p        O   o         port@1          ~      endpoint            
   q        O   r               gamma@1c006000        6    mediatek,mt8188-disp-gamma mediatek,mt8195-disp-gamma           ~     `                   %           -                        6           	   \     `       ports                        +       port@0          ~       endpoint            
   r        O   q         port@1          ~      endpoint                   dither@1c007000       8    mediatek,mt8188-disp-dither mediatek,mt8183-disp-dither         ~     p                   %           -                        6           	   \     p       ports                        +       port@0          ~       endpoint             port@1          ~      endpoint                   dsi@1c008000              mediatek,mt8188-dsi         ~                        %      %      s        engine digital hs           -                        s        	(dphy               6           &   %         	  Jdisabled          dsc@1c009000          2    mediatek,mt8188-disp-dsc mediatek,mt8195-disp-dsc           ~                        %   
        -                        6           	   \               dsi@1c012000              mediatek,mt8188-dsi         ~                        %   	   %      t        engine digital hs           -                        t        	(dphy               6           &   %   	      	  Jdisabled          merge0@1c014000       6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~    @                   %      .           merge merge_async           -                        6           	   \     @          dp-intf@1c015000              mediatek,mt8188-dp-intf         ~    P                   %       %      !           pixel engine pll            -                        6         	  Jdisabled          mutex@1c016000            mediatek,mt8188-disp-mutex          ~    `                   %           -                        6           	   \     `            	  >      postmask@1c01a000         <    mediatek,mt8188-disp-postmask mediatek,mt8192-disp-postmask         ~                       %           -                        6           	   \            ports                        +       port@0          ~       endpoint             port@1          ~      endpoint                   syscon@1c01d000           mediatek,mt8188-vdosys0 syscon          ~                                          K   \               	   \                 O   %      smi@1c022000              mediatek,mt8188-smi-larb            ~                        %      %           apb smi            6           	            	   h        O   u      smi@1c023000              mediatek,mt8188-smi-larb            ~    0                   %      %           apb smi            6           	           	   `        O   a      smi@1c024000              mediatek,mt8188-smi-common-vdo          ~    @                   %      %           apb smi            6           O   h      iommu@1c028000            mediatek,mt8188-iommu-vdo           ~           P            %           bclk            -                        6                      
   u   v   w   x   y        O   g      syscon@1c100000           mediatek,mt8188-vdosys1 syscon          ~                                           K   \              	   \                  O   .      mutex@1c101000            mediatek,mt8188-disp-mutex          ~                       .           -                        6           	   \                 	        smi@1c102000              mediatek,mt8188-smi-larb            ~                        .       .            apb smi            6           	           	   h        O   v      smi@1c103000              mediatek,mt8188-smi-larb            ~    0                   .      .           apb smi            6           	           	   `        O   b      rdma@1c104000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    @                   .           -                     	   g   @           6           	           	   \     @          rdma@1c105000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    P                   .           -                     	   ]   `           6           	           	   \     P          rdma@1c106000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    `                   .           -                     	   g   A           6           	           	   \     `          rdma@1c107000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    p                   .           -                     	   ]   a           6           	           	   \     p          rdma@1c108000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~                       .           -                     	   g   B           6           	           	   \               rdma@1c109000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~                       .           -                     	   ]   b           6           	           	   \               rdma@1c10a000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~                       .           -                     	   g   C           6           	           	   \               rdma@1c10b000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~                       .           -                     	   ]   c           6           	           	   \               merge@1c10c000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~                       .   	   .           merge merge_async           -                        6           &   .           	   \                  
$      merge@1c10d000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~                       .   
   .           merge merge_async           -                        6           &   .           	   \                  
$      merge@1c10e000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~                       .      .           merge merge_async           -                        6           &   .           	   \                  
$      merge@1c10f000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~                       .      .           merge merge_async           -                        6           &   .           	   \                  
$      merge@1c110000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~                        .      .           merge merge_async           -                        6           &   .           	   \                   
8      dpi@1c112000          (    mediatek,mt8188-dpi mediatek,mt8195-dpi         ~                        .   8   .      .   =        pixel engine pll            -                        6           &   .         	  Jdisabled       ports                        +       port@0          ~       endpoint             port@1          ~      endpoint                   dp-intf@1c113000              mediatek,mt8188-dp-intf         ~    0                   .   :   .      !           pixel engine pll            -                        6         	  Jdisabled          ethdr@1c114000        6    mediatek,mt8188-disp-ethdr mediatek,mt8195-disp-ethdr         p  ~    @            P            p                                                              4  (mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       h     .   0   .   +   .   .   .   ,   .   /   .   -   .   <   .   1   .   2   .   3   .   4   .   5   "           mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          -      6               	   ]   d   ]   e           6         (  &   .   1   .   2   .   3   .   4   .   5      p  	   \     @       \     P       \     p       \            \            \            \               padding@1c11d000              mediatek,mt8188-disp-padding            ~                       .              6           	   \               padding@1c11e000              mediatek,mt8188-disp-padding            ~                       .               6           	   \               padding@1c11f000              mediatek,mt8188-disp-padding            ~                       .   !           6           	   \               padding@1c120000              mediatek,mt8188-disp-padding            ~                        .   "           6           	   \                padding@1c121000              mediatek,mt8188-disp-padding            ~                       .   #           6           	   \               padding@1c122000              mediatek,mt8188-disp-padding            ~                        .   $           6           	   \                padding@1c123000              mediatek,mt8188-disp-padding            ~    0                   .   %           6           	   \     0          padding@1c124000              mediatek,mt8188-disp-padding            ~    @                   .   &           6           	   \     @          hdmi@1c300000             mediatek,mt8188-hdmi-tx                    ~    0                     "   @   "   >   "   ?   &   .        bus hdcp hdcp24m hdmi-split            "   >           "   s        -                        6   	           z        	(hdmi          	  Jdisabled       i2c       2    mediatek,mt8188-hdmi-ddc mediatek,mt8195-hdmi-ddc              5      ports                        +       port@0          ~       endpoint             port@1          ~      endpoint                   edp-tx@1c500000           mediatek,mt8188-edp-tx          ~    P                 -                     u   {        dp_calibration_data            6           
O        	  Jdisabled          dp-tx@1c600000            mediatek,mt8188-dp-tx           ~    `                 -                     u   {        dp_calibration_data            6           
O        	  Jdisabled             chosen          
`serial0:115200n8          memory@40000000         rmemory          ~    @                reserved-memory                      +               memory@50000000           shared-dma-pool         ~    P                  
l        O   4            	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dpi1 dsc0 ethdr0 gce0 gce1 merge0 merge1 merge2 merge3 merge4 merge5 mutex0 mutex1 padding0 padding1 padding2 padding3 padding4 padding5 padding6 padding7 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 mmc0 device_type reg enable-method clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-output-names opp-shared opp-hz opp-microvolt opp-supported-hw interrupts mediatek,platform status polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux bias-pull-up input-enable drive-strength bias-pull-down bias-disable #power-domain-cells clocks clock-names mediatek,infracfg mediatek,disable-extrst #sound-dai-cells interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells memory-region power-domains resets reset-names mediatek,topckgen mboxes mbox-names pinctrl-names pinctrl-0 nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells phys wakeup-source mediatek,syscon-wakeup interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,blen snps,rd_osr_lmt snps,wr_osr_lmt snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,priority snps,weight bus-width hs400-ds-delay max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v supports-cqe cap-mmc-hw-reset no-sdio no-sd non-removable vmmc-supply vqmmc-supply pinctrl-1 clock-div bus-range linux,pci-domain interrupt-map interrupt-map-mask iommu-map iommu-map-mask phy-names spi-max-frequency #phy-cells mediatek,ibias mediatek,ibias_up bits operating-points-v2 power-domain-names #dma-cells iommus mediatek,gce-client-reg mediatek,gce-events mediatek,scp mediatek,larb-id mediatek,smi mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz stdout-path no-map 