     8     (              P                             $    mediatek,mt8186-evb mediatek,mt8186                                  +         !   7MediaTek MT8186 evaluation board          	   =embedded       aliases          J/soc/ovl@14005000            O/soc/ovl@14006000            W/soc/rdma@14007000           ]/soc/rdma@1401f000           c/soc/serial@11002000          fhctl@1000ce00            mediatek,mt8186-fhctl            k               r                   	   vdisabled          cci           mediatek,mt8186-cci          k                     }cci intermediate                                        "      opp-table-cci             operating-points-v2                          opp-500000000                e           	'                  opp-560000000                !`           
L                  opp-612000000                $za           
                  opp-682000000                (~          
            	      opp-752000000                ,Ҝ           YF            
      opp-822000000                0                            opp-875000000                4'p                            opp-927000000                7@          5                   opp-980000000                :i           ~>                  opp-1050000000               >                            opp-1120000000               B           )$                  opp-1155000000               D                            opp-1190000000               F          
                  opp-1260000000               K           ~                  opp-1330000000               OF0          )                  opp-1400000000               SrN           R                     opp-table-cluster0            operating-points-v2                          opp-500000000                e           	'                  opp-774000000                ."M          
L                  opp-875000000                4'p          
`                  opp-975000000                :Q                      	      opp-1075000000               @2          q            
      opp-1175000000               F	          X                  opp-1275000000               K          5                   opp-1375000000               Q                            opp-1500000000               Yh/                             opp-1618000000               `p          Y                  opp-1666000000               cM$                            opp-1733000000               gK{@          H                  opp-1800000000               kI           ~                  opp-1866000000               o8                            opp-1933000000               s7=@          Z                  opp-2000000000               w5           R                     opp-table-cluster1            operating-points-v2                       #   opp-774000000                ."M          
L                  opp-835000000                1          
                  opp-919000000                6          
                  opp-1002000000               ;N          YF            	      opp-1085000000               @@          X            
      opp-1169000000               E@          5                   opp-1308000000               M                             opp-1419000000               T8          Y                  opp-1530000000               [1          t                  opp-1670000000               c-          Z                  opp-1733000000               gK{@                            opp-1796000000               k           s                  opp-1860000000               nY           Լ                  opp-1923000000               r          6d                  opp-1986000000               v_          v                  opp-2050000000               z0                               cpus                         +       cpu-map    cluster0       core0                     core1                     core2                     core3                     core4                     core5                     core6                     core7                           cpu@0            cpu           arm,cortex-a55           r             psci             w5          k                      }cpu intermediate                           T        '  ~        :               J           W   @        i           v              @                      !                      "                  cpu@100          cpu           arm,cortex-a55           r            psci             w5          k                      }cpu intermediate                           T        '  ~        :               J           W   @        i           v              @                      !                      "                  cpu@200          cpu           arm,cortex-a55           r            psci             w5          k                      }cpu intermediate                           T        '  ~        :               J           W   @        i           v              @                      !                      "                  cpu@300          cpu           arm,cortex-a55           r            psci             w5          k                      }cpu intermediate                           T        '  ~        :               J           W   @        i           v              @                      !                      "                  cpu@400          cpu           arm,cortex-a55           r            psci             w5          k                      }cpu intermediate                           T        '  ~        :               J           W   @        i           v              @                      !                      "                  cpu@500          cpu           arm,cortex-a55           r            psci             w5          k                      }cpu intermediate                           T        '  ~        :               J           W   @        i           v              @                      !                      "                  cpu@600          cpu           arm,cortex-a76           r            psci             z0         k                     }cpu intermediate                #          O        '           :   $   %        J           W   @        i           v              @                      &                      "                  cpu@700          cpu           arm,cortex-a76           r            psci             z0         k                     }cpu intermediate                #          O        '           :   $   %        J           W   @        i           v              @                      &                      "                  idle-states         psci       cpu-retention-l           arm,idle-state                                2           d        %  @                  cpu-retention-b           arm,idle-state                                2           d        %  x            $      cpu-off-l             arm,idle-state                               d                   %  4                   cpu-off-b             arm,idle-state                               d                   %  l            %         l2-cache0             cache           6           L           Y   @        k              '         B            !      l2-cache1             cache           6           L           Y   @        k              '         B            &      l3-cache              cache           6           L           Y   @        k            B            '         fixed-factor-clock-13m            fixed-factor-clock          P             k   (        ]           g           rclk13m              5      oscillator-26m            fixed-clock         P                     rclk26m              (      oscillator-32k            fixed-clock         P                        rclk32k        opp-table-gpu             operating-points-v2             N   opp-299000000                `          	X                 opp-332000000                           	h                 opp-366000000                з          	<                 opp-400000000                ׄ           	Ҧ                 opp-434000000                P          
z                 opp-484000000                A           
4N                 opp-535000000                s          
}                 opp-586000000                "          
`                 opp-637000000                %@          
4                 opp-690000000                )           @                 opp-743000000                ,IG                           opp-796000000                /q                            opp-850000000                2          5                  opp-900000000-3              5           P                 opp-900000000-4              5           |                 opp-900000000-5              5                             opp-950000000-3              8ـ                           opp-950000000-4              8ـ          Y                 opp-950000000-5              8ـ          P                  opp-1000000000-3                 ;           ~                 opp-1000000000-4                 ;           t                 opp-1000000000-5                 ;           Y                     pmu-a55           arm,cortex-a55-pmu                                  )      pmu-a76           arm,cortex-a76-pmu                                  *      psci              arm,psci-1.0             smc       timer             arm,armv8-timer                   @                                               
             soc                      +             simple-bus                                             interrupt-controller@c000000              arm,gic-v3                                                       r                                          	                      ppi-partitions     interrupt-partition-0                                         )      interrupt-partition-1                             *            syscon@c53a000            mediatek,mt8186-mcusys syscon            r    S                P                     syscon@10000000            mediatek,mt8186-topckgen syscon          r                      P               ,      syscon@10001000       #    mediatek,mt8186-infracfg_ao syscon           r                     P                          -      syscon@10003000           mediatek,mt8186-pericfg syscon           r     0                    I      pinctrl@10005000              mediatek,mt8186-pinctrl          r     P                           "             $             &             *             ,                           B  iocfg0 iocfg_lt iocfg_lm iocfg_lb iocfg_bl iocfg_rb iocfg_rt eint            	                   %   +                                                                 +   i2c0-default-pins               :   pins-bus            1             8        E           ]         i2c1-default-pins               ;   pins-bus            1             8        E           ]         i2c2-default-pins               <   pins-bus            1             8        E           ]         i2c3-default-pins               =   pins-bus            1             8        E           ]         i2c4-default-pins               >   pins-bus            1             8        E           ]         i2c5-default-pins               ?   pins-bus            1             8        E           ]         i2c6-default-pins               @   pins-bus            1            j           E           ]         i2c7-default-pins               A   pins-bus            1             8        E           ]         i2c8-default-pins               B   pins-bus            1             8        E           ]         i2c9-default-pins               F   pins-bus            1            j           E           ]            syscon@10006000       )    mediatek,mt8186-scpsys syscon simple-mfd             r     `           power-controller          !    mediatek,mt8186-power-controller                         +            w               8   power-domain@0           r             k   ,            }mfg00                        +            w      power-domain@1           r              -                     +            w      power-domain@2           r           w          power-domain@3           r           w                power-domain@17          r            k   ,      ,         $   }subsys-csirx-top0 subsys-csirx-top1         w          power-domain@4           r            k   ,      -   =         }sys_ck ref_ck           w          power-domain@5           r            k   -   B   -   ?         }sys_ck ref_ck           w          power-domain@18          r            k   ,   /   ,   >         }audioadsp subsys-adsp-bus                        +            w      power-domain@19          r                        +            w      power-domain@20          r              -        w                power-domain@16          r              -        w          power-domain@6           r         0   k   ,   *   ,   +   .   
   .      .      .         M   }disp mdp subsys-smi-infra subsys-smi-common subsys-smi-gals subsys-smi-iommu               -                     +            w      power-domain@14          r            k   ,   )   /             }vdec0 larb             -        w          power-domain@10          r   
      8   k   ,      ,      ,      ,       0      ,   #   ,   %      6   }cam0 cam1 cam2 cam3 gals subsys-cam-tm subsys-cam-top              -                     +            w      power-domain@12          r           w          power-domain@11          r           w             power-domain@7           r            k   1      ,   &         }gals subsys-img-top            -                     +            w      power-domain@8           r           w             power-domain@9           r   	      (   k   ,   '   2       2      2      2         P   }subsys-ipe-top subsys-ipe-larb0 subsys-ipe-larb1 subsys-ipe-smi subsys-ipe-gals            -        w          power-domain@13          r            k   ,   $   3            }venc0 subsys-larb              -        w          power-domain@15          r            k   ,   :   4      4         %   }wpe0 subsys-larb-ck subsys-larb-pclk               -        w                   watchdog@10007000             mediatek,mt8186-wdt                   r     p                               G      syscon@1000c000       "    mediatek,mt8186-apmixedsys syscon            r                     P                     pwrap@1000d000            mediatek,mt8186-pwrap syscon             r                     pwrap                                  k   -      -          	   }spi wrap          spmi@10015000         *    mediatek,mt8186-spmi mediatek,mt8195-spmi             r    P                            pmif spmimst             k   -      -       ,   2      (   }pmif_sys_ck pmif_tmr_ck spmimst_clk_mux            ,   2           ,   t                                           	   vdisabled          timer@10017000        ,    mediatek,mt8186-timer mediatek,mt6765-timer          r    p                                       k   5      mailbox@1022c000              mediatek,mt8186-gce          r    "       @          k   -            }gce                                              O      scp@10500000              mediatek,mt8186-scp           r    P             \             	  sram cfg                                      b      adsp@10680000             mediatek,mt8186-dsp       @   r    h                           h            h                cfg sram sec bus             k   ,   /   ,   >         }audiodsp adsp_bus              ,   /   ,   >           (   ,   E        rx tx              6   7           8         	   vdisabled          mailbox@10686100              mediatek,mt8186-adsp-mbox                        r    ha                      i                   6      mailbox@10687100              mediatek,mt8186-adsp-mbox                        r    hq                      j                   7      spi@11000000              mediatek,mt8186-nor          r                        k   ,   3   -   O   -   c   -   d         }spi sf axi axi_s               ,   3           ,   X              %             	   vdisabled          adc@11001000          .    mediatek,mt8186-auxadc mediatek,mt8173-auxadc            r                                 k   -   "         }main          serial@11002000       *    mediatek,mt8186-uart mediatek,mt6577-uart            r                             p                k   (   -         	   }baud bus             vokay          serial@11003000       *    mediatek,mt8186-uart mediatek,mt6577-uart            r     0                       q                k   (   -         	   }baud bus          	   vdisabled          i2c@11007000              mediatek,mt8186-i2c           r     p                                    i                k   9       -   '      	   }main dma            ]                        +             vokay                      default         (   :      i2c@11008000              mediatek,mt8186-i2c           r                                         j                k   9      -   '      	   }main dma            ]                        +             vokay                      2  @        default         (   ;      i2c@11009000              mediatek,mt8186-i2c           r                                        k                k   9      -   '      	   }main dma            ]                        +             vokay                      2  '        default         (   <      i2c@1100f000              mediatek,mt8186-i2c           r                                        l                k   9      -   '      	   }main dma            ]                        +             vokay                      default         (   =      i2c@11011000              mediatek,mt8186-i2c           r                                      m                k   9      -   '      	   }main dma            ]                        +             vokay                      default         (   >      i2c@11016000              mediatek,mt8186-i2c           r    `                                   b                k   9      -   '      	   }main dma            ]                        +             vokay                      default         (   ?      i2c@1100d000              mediatek,mt8186-i2c           r                                        c                k   9      -   '      	   }main dma            ]                        +             vokay                      default         (   @      i2c@11004000              mediatek,mt8186-i2c           r     @             	                      n                k   9      -   '      	   }main dma            ]                        +             vokay                      default         (   A      i2c@11005000              mediatek,mt8186-i2c           r     P             
                     o                k   9      -   '      	   }main dma            ]                        +             vokay                      default         (   B      spi@1100a000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +             r                                            k   ,   K   ,      -            }parent-clk sel-clk spi-clk        	   vdisabled          thermal-sensor@1100b000           mediatek,mt8186-lvts             r                            c                k   -   	        L   -            S   C   D      $  _lvts-calib-data-1 lvts-calib-data-2         p               f      svs@1100bc00              mediatek,mt8186-svs          r                                            k   -   	         }main            S   E   C      (  _svs-calibration-data t-calibration-data         L   -           svs_rst       pwm@1100e000          2    mediatek,mt8186-disp-pwm mediatek,mt8183-disp-pwm            r                                                       k   ,      -   4         }main mm       	   vdisabled          spi@11010000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +             r                                            k   ,   K   ,      -   8         }parent-clk sel-clk spi-clk        	   vdisabled          spi@11012000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +             r                                            k   ,   K   ,      -   ;         }parent-clk sel-clk spi-clk        	   vdisabled          spi@11013000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +             r    0                                       k   ,   K   ,      -   <         }parent-clk sel-clk spi-clk        	   vdisabled          spi@11014000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +             r    @                       t                k   ,   K   ,      -   J         }parent-clk sel-clk spi-clk        	   vdisabled          spi@11015000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +             r    P                       u                k   ,   K   ,      -   K         }parent-clk sel-clk spi-clk        	   vdisabled          clock-controller@11017000             mediatek,mt8186-imp_iic_wrap             r    p                P               9      serial@11018000       *    mediatek,mt8186-uart mediatek,mt6577-uart            r                                           k   (   -         	   }baud bus          	   vdisabled          i2c@11019000              mediatek,mt8186-i2c           r                                      d                k   9   	   -   '      	   }main dma            ]                        +             vokay                      default         (   F      audio-controller@11210000             mediatek,mt8186-sound            r    !                   k   -   ,   -   6   ,      ,      ,   F   ,            ,            ,      ,   e   ,      ,   h   ,   ?   ,   @   ,   A   ,   B   ,   C   ,      ,      ,      ,      ,      ,   ,   (     }   }aud_infra_clk mtkaif_26m_clk top_mux_audio top_mux_audio_int top_mainpll_d2_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d8 top_mux_aud_eng2 top_apll2_d8 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s4_m_sel top_tdm_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div4 top_apll12_div_tdm top_mux_audio_h top_clk26m_clk                                                -           ,        L   G         	  audiosys          	   vdisabled          usb@11201000          #    mediatek,mt8186-mtu3 mediatek,mtu3            r            -     >              	  mac ippc          (   k   ,      -   =   -   3   -      -   >      $   }sys_ck ref_ck mcu_ck dma_ck xhci_ck               /                  H              8                        +                                I            	   vdisabled       usb@11200000          '    mediatek,mt8186-xhci mediatek,mtk-xhci           r                      mac       (   k   ,      -   =   -   3   -      -   >      $   }sys_ck ref_ck mcu_ck dma_ck xhci_ck               &             	   vdisabled             mmc@11230000          (    mediatek,mt8186-mmc mediatek,mt8183-mmc           r    #                                k   ,      -      -   U   -            }source hclk source_cg crypto                   d                  ,                       	   vdisabled          mmc@11240000          (    mediatek,mt8186-mmc mediatek,mt8183-mmc           r    $                               k   ,      -      -   V         }source hclk source_cg                  e                  ,              ,   o      	   vdisabled          usb@11281000          #    mediatek,mt8186-mtu3 mediatek,mtu3            r    (       -    (>              	  mac ippc          $   k   -   B   -   ?   -   7   (   -   @      $   }sys_ck ref_ck mcu_ck dma_ck xhci_ck               K                  J      K              8                        +                                I  $         	   vdisabled       usb@11280000          '    mediatek,mt8186-xhci mediatek,mtk-xhci           r    (                 mac       $   k   -   B   -   ?   -   7   (   -   @      $   }sys_ck ref_ck mcu_ck dma_ck xhci_ck               D             	   vdisabled             t-phy@11c80000        .    mediatek,mt8186-tphy mediatek,generic-tphy-v2                        +                                 vokay       usb-phy@0            r                k   (         }ref                        J      usb-phy@700          r     	          k   (         }ref                        K         t-phy@11ca0000        .    mediatek,mt8186-tphy mediatek,generic-tphy-v2                        +                                 vokay       usb-phy@0            r                k   (         }ref                                   H         efuse@11cb0000        %    mediatek,mt8186-efuse mediatek,efuse             r                                  +      lvts1-calib@1cc          r                 C      lvts2-calib@2f8          r                 D      calib@550            r  P   P            E      gpu-speedbin@59c             r                                M      socinfo-data1@7a0            r              dsi-phy@11cc0000              mediatek,mt8183-mipi-tx          r                      k   (        P                        rmipi_tx0_pll          	   vdisabled                R      clock-controller@13000000             mediatek,mt8186-mfgsys           r                      P               L      gpu@13040000          &    mediatek,mt8186-mali arm,mali-bifrost            r            @          k   L          0                                                 job mmu gpu            8      8           core0 core1                    S   M      
  _speed-bin               N          O      	   vdisabled                k      syscon@14000000           mediatek,mt8186-mmsys syscon             r                      P                         O          O              0   O                      .      mutex@14001000            mediatek,mt8186-disp-mutex           r                      k   .                  '               0   O                 H               8         smi@14002000              mediatek,mt8186-smi-common           r                        k   .      .      .      .            }apb smi gals0 gals1            8               P      smi@14003000              mediatek,mt8186-smi-larb             r     0                 k   .      .            }apb smi         \            m   P           8               S      smi@14004000              mediatek,mt8186-smi-larb             r     @                 k   .      .            }apb smi         \           m   P           8               T      ovl@14005000          2    mediatek,mt8186-disp-ovl mediatek,mt8192-disp-ovl            r     P                 k   .                 )               z   Q           0   O     P               8         ovl@14006000          8    mediatek,mt8186-disp-ovl-2l mediatek,mt8192-disp-ovl-2l          r     `                 k   .                 *               z   Q   !        0   O     `               8         rdma@14007000         4    mediatek,mt8186-disp-rdma mediatek,mt8183-disp-rdma          r     p                 k   .                 +               z   Q   "        0   O     p               8         color@14009000        6    mediatek,mt8186-disp-color mediatek,mt8173-disp-color            r                      k   .   	              -               0   O                    8         dpi@1400a000              mediatek,mt8186-dpi          r                      k   ,   ;   .                  }pixel engine pll               ,   ;           ,   j              5                  8         	   vdisabled       port       endpoint                ccorr@1400b000        6    mediatek,mt8186-disp-ccorr mediatek,mt8192-disp-ccorr            r                      k   .                 .               0   O                    8         aal@1400c000          2    mediatek,mt8186-disp-aal mediatek,mt8183-disp-aal            r                      k   .                 0               0   O                    8         gamma@1400d000        6    mediatek,mt8186-disp-gamma mediatek,mt8183-disp-gamma            r                      k   .                 1               0   O                    8         postmask@1400e000         <    mediatek,mt8186-disp-postmask mediatek,mt8192-disp-postmask          r                      k   .                 2               0   O                    8         dither@1400f000       8    mediatek,mt8186-disp-dither mediatek,mt8183-disp-dither          r                      k   .                 3               0   O                    8         dsi@14013000              mediatek,mt8186-dsi          r    0                 k   .      .      R         }engine digital hs                 7                  8           L   .              R        dphy          	   vdisabled       port       endpoint                iommu@14016000            mediatek,mt8186-iommu-mm             r    `                 k   .            }bclk                  9             8     S   T   U   V   W   X   Y   Z   [   \   ]   ^   _   `           8                          Q      rdma@1401f000         4    mediatek,mt8186-disp-rdma mediatek,mt8183-disp-rdma          r                     k   .                 4               z   Q            0   O                    8         clock-controller@14020000             mediatek,mt8186-wpesys           r                     P               4      smi@14023000              mediatek,mt8186-smi-larb             r    0                 k   4      4            }apb smi         \           m   P           8               X      clock-controller@15020000             mediatek,mt8186-imgsys1          r                     P               1      smi@1502e000              mediatek,mt8186-smi-larb             r                     k   1      1             }apb smi         \   	        m   P           8               Y      clock-controller@15820000             mediatek,mt8186-imgsys2          r                     P               a      smi@1582e000              mediatek,mt8186-smi-larb             r                     k   1       a             }apb smi         \           m   P           8               Z      video-decoder@16000000            mediatek,mt8186-vcodec-dec           r                                            +                      @                 z   Q              b   video-codec@16025000              mediatek,mtk-vcodec-core             r    P                      W             `  z   Q      Q      Q      Q      Q      Q      Q      Q      Q      Q      Q      Q             k   ,   )   /      /       ,   U      %   }vdec-sel vdec-soc-vdec vdec vdec-top               ,   )           ,   U           8            smi@1602e000              mediatek,mt8186-smi-larb             r                     k   /       /             }apb smi         \           m   P           8               V      clock-controller@1602f000             mediatek,mt8186-vdecsys          r                    P               /      clock-controller@17000000             mediatek,mt8186-vencsys          r                      P               3      smi@17010000              mediatek,mt8186-smi-larb             r                      k   3      3            }apb smi         \           m   P           8               W      video-encoder@17020000        6    mediatek,mt8186-vcodec-enc mediatek,mt8183-vcodec-enc            r                                          H  z   Q      Q      Q      Q      Q      Q      Q      Q      Q            k   3         	   }venc_sel               ,   $           ,   U           8              b      jpeg-encoder@17030000         +    mediatek,mt8186-jpgenc mediatek,mtk-jpgenc           r                                            k   3            }jpgenc           z   Q      Q      Q      Q              8         clock-controller@1a000000             mediatek,mt8186-camsys           r                      P               0      smi@1a001000              mediatek,mt8186-smi-larb             r                      k   0      0             }apb smi         \           m   P           8   
            [      smi@1a002000              mediatek,mt8186-smi-larb             r                       k   0      0            }apb smi         \           m   P           8   
            \      smi@1a00f000              mediatek,mt8186-smi-larb             r                      k   0      c             }apb smi         \           m   P           8               ]      smi@1a010000              mediatek,mt8186-smi-larb             r                      k   0       d             }apb smi         \           m   P           8               ^      clock-controller@1a04f000             mediatek,mt8186-camsys_rawa          r                    P               c      clock-controller@1a06f000             mediatek,mt8186-camsys_rawb          r                    P               d      clock-controller@1b000000             mediatek,mt8186-mdpsys           r                      P               e      smi@1b002000              mediatek,mt8186-smi-larb             r                       k   e      e            }apb smi         \           m   P           8               U      clock-controller@1c000000             mediatek,mt8186-ipesys           r                      P               2      smi@1c00f000              mediatek,mt8186-smi-larb             r                      k   2      2            }apb smi         \           m   P           8   	            `      smi@1c10f000              mediatek,mt8186-smi-larb             r                     k   2       2             }apb smi         \           m   P           8   	            _         thermal-zones      cpu-little0-thermal                                 f       trips      trip-alert0          L                   Epassive             g      trip-alert1          s                   Ehot       trip-crit                              	   Ecritical             cooling-maps       map0               g      H                                cpu-little1-thermal                                 f      trips      trip-alert0          L                   Epassive             h      trip-alert1          s                   Ehot       trip-crit                              	   Ecritical             cooling-maps       map0               h      H                                cpu-little2-thermal                                 f      trips      trip-alert0          L                   Epassive             i      trip-alert1          s                   Ehot       trip-crit                              	   Ecritical             cooling-maps       map0               i      H                                cam-thermal                                 f      trips      trip-alert0          L                   Epassive       trip-alert1          s                   Ehot       trip-crit                              	   Ecritical                nna-thermal                                 f      trips      trip-alert0          L                   Epassive       trip-alert1          s                   Ehot       trip-crit                              	   Ecritical                adsp-thermal                                    f      trips      trip-alert0          L                   Epassive       trip-alert1          s                   Ehot       trip-crit                              	   Ecritical                gpu-thermal                                 f      trips      trip-alert0          L                   Epassive             j      trip-alert1          s                   Ehot       trip-crit                              	   Ecritical             cooling-maps       map0               j           k            cpu-big0-thermal                         d           f      trips      trip-alert0          L                   Epassive             l      trip-alert1          s                   Ehot       trip-crit                              	   Ecritical             cooling-maps       map0               l                          cpu-big1-thermal                         d           f      trips      trip-alert0          L                   Epassive             m      trip-alert1          s                   Ehot       trip-crit                              	   Ecritical             cooling-maps       map0               m                             chosen          serial0:921600n8          memory@40000000          memory           r    @                regulator-vproc12             regulator-fixed         vproc12          .         B        T O        l O                     	compatible interrupt-parent #address-cells #size-cells model chassis-type ovl0 ovl-2l0 rdma0 rdma1 serial0 clocks reg status clock-names operating-points-v2 proc-supply phandle opp-shared opp-hz opp-microvolt required-opps cpu device_type enable-method clock-frequency dynamic-power-coefficient capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells mediatek,cci entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-div clock-mult clock-output-names opp-supported-hw interrupts dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux bias-disable drive-strength-microamp input-enable bias-pull-up #power-domain-cells mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #mbox-cells mbox-names mboxes power-domains #io-channel-cells pinctrl-names pinctrl-0 i2c-scl-internal-delay-ns resets nvmem-cells nvmem-cell-names #thermal-sensor-cells reset-names #pwm-cells mediatek,apmixedsys mediatek,topckgen phys wakeup-source mediatek,syscon-wakeup #phy-cells mediatek,discth bits interrupt-names power-domain-names mediatek,gce-client-reg mediatek,gce-events mediatek,larb-id mediatek,smi iommus phy-names mediatek,larbs #iommu-cells mediatek,scp polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path regulator-name regulator-always-on regulator-boot-on regulator-min-microvolt regulator-max-microvolt 