  'G   8  $H   (              $                                  xiaomi,ax3000t mediatek,mt7981b                                  +            7Xiaomi AX3000T     cpus                         +       cpu@0             arm,cortex-a53           =             Acpu          Mpsci          cpu@1             arm,cortex-a53           =            Acpu          Mpsci             oscillator-40m            fixed-clock          [bZ          kclkxtal          ~          psci              arm,psci-1.0             Tsmc       reserved-memory                      +                wo-boot@15194000             =    @                                    wo-ilm@151e0000          =                                         wo-dlm@151e8000          =                                         secmon@43000000          =    C                          wmcpu-reserved@47c80000          =    G                                     wo-emi@47d80000          =    G                                     wo-data@47dc0000             =    G       $                                 soc           simple-bus                                 +      interrupt-controller@c000000              arm,gic-v3            =                                                       	                                           clock-controller@10001000              mediatek,mt7981-infracfg syscon          =                      ~                     clock-controller@1001b000              mediatek,mt7981-topckgen syscon          =                     ~                     watchdog@1001c000             mediatek,mt7986-wdt          =                            n                                 clock-controller@1001e000             mediatek,mt7981-apmixedsys           =                     ~                     pwm@10048000              mediatek,mt7981-pwm          =                  (                                          top main pwm1 pwm2 pwm3                   syscon@10060000       "    mediatek,mt7981-sgmiisys_0 syscon            =                      ~                     syscon@10070000       "    mediatek,mt7981-sgmiisys_1 syscon            =                      ~                     serial@11002000       *    mediatek,mt7981-uart mediatek,mt6577-uart            =                              {            uart wakeup                            	   baud bus            default                  	  %disabled          serial@11003000       *    mediatek,mt7981-uart mediatek,mt6577-uart            =     0                        |            uart wakeup                             	   baud bus          	  %disabled          serial@11004000       *    mediatek,mt7981-uart mediatek,mt6577-uart            =     @                        }            uart wakeup                      !      	   baud bus          	  %disabled          i2c@11007000              mediatek,mt7981-i2c           =     p            !p                                                      3      4         main dma arb pmic                        +          	  %disabled          spi@11009000          )    mediatek,mt7981-spi-ipm mediatek,spi-ipm             =                                                      N      "      #          parent-clk sel-clk spi-clk hclk                      +          	  %disabled          spi@1100a000          )    mediatek,mt7981-spi-ipm mediatek,spi-ipm             =                                                      N      '      )          parent-clk sel-clk spi-clk hclk                      +          	  %disabled          spi@1100b000          )    mediatek,mt7981-spi-ipm mediatek,spi-ipm             =                                                      N      (      *          parent-clk sel-clk spi-clk hclk                      +          	  %disabled          thermal@1100c800          0    mediatek,mt7981-thermal mediatek,mt7986-thermal          =                                                     0         therm auxadc            ,           8calibration-data            I           _           o         adc@1100d000          .    mediatek,mt7981-auxadc mediatek,mt7986-auxadc            =                            0         main                     	  %disabled                      usb@11200000          '    mediatek,mt7986-xhci mediatek,mtk-xhci            =             .      >              	  mac ippc          (         7      8      5      6      k      $   sys_ck ref_ck mcu_ck dma_ck xhci_ck                                     	         	  %disabled          pcie@11280000         *    mediatek,mt7981-pcie mediatek,mt8192-pcie            =    (        @       	  pcie-mac                                                                      9      :      ;      <      !   pl_250m tl_26m peri_26m top_133m             Apci            	         	  pcie-phy                                                    `                    
                      
                     
                     
                                    +         	  %disabled       interrupt-controller                                                   
         pinctrl@11d00000              mediatek,mt7981-pinctrl          =                                                                                                                           I  gpio iocfg_rt iocfg_rm iocfg_rb iocfg_lb iocfg_bl iocfg_tm iocfg_tl eint                                                                   9                                               uart0-pins                 mux         uart            
uart0               topmisc@11d10000              mediatek,mt7981-topmisc syscon           =                      ~                     t-phy@11e10000        .    mediatek,mt7981-tphy mediatek,generic-tphy-v2                                              +         	  %disabled       usb-phy@0            =                      l         ref                              usb-phy@700          =     	                d         ref                                         	         efuse@11f20000        %    mediatek,mt7981-efuse mediatek,efuse             =                                  +      soc-uuid@140             =  @         thermal-calib@274            =  t                     phy-calib@8dc            =                          clock-controller@15000000             mediatek,mt7981-ethsys syscon            =                       ~                                 wed@15010000              mediatek,mt7981-wed syscon           =                                        1                     %  ?wo-emi wo-ilm wo-dlm wo-data wo-boot            S                     ethernet@15100000             mediatek,mt7981-eth          =                     d      `      a        t            "      x                                  @                                                        ]      ^         fe gp2 gp1 wocpu0 sgmii_ck sgmii_tx250m sgmii_rx250m sgmii_cdr_ref sgmii_cdr_fb sgmii2_tx250m sgmii2_rx250m sgmii2_cdr_ref sgmii2_cdr_fb netsys0 netsys1          `                                                                                         (   fe0 fe1 fe2 fe3 pdma0 pdma1 pdma2 pdma3                                                                 	  %disabled       mdio-bus                         +       ethernet-phy@0            ethernet-phy-ieee802.3-c22           =            gmii                     ,           8phy-cal-data                sram@15140000         
    mmio-sram            =                                                        +                     syscon@151a5000           mediatek,mt7986-wo-ccif syscon           =    P                                             wifi@18000000             mediatek,mt7981-wmac          0   =                   0                           0                                                          _      \         mcu ap2conn         1                         consys        	  %disabled             timer             arm,armv8-timer                   0                                    
         memory@40000000          =    @                   Amemory           	compatible interrupt-parent #address-cells #size-cells model reg device_type enable-method clock-frequency clock-output-names #clock-cells ranges no-map phandle interrupts interrupt-controller #interrupt-cells #reset-cells clocks clock-names #pwm-cells interrupt-names pinctrl-names pinctrl-0 status nvmem-cells nvmem-cell-names #thermal-sensor-cells mediatek,auxadc mediatek,apmixedsys #io-channel-cells reg-names phys bus-range phy-names interrupt-map-mask interrupt-map gpio-ranges gpio-controller #gpio-cells function groups #phy-cells mediatek,syscon-type memory-region memory-region-names mediatek,wo-ccif assigned-clocks assigned-clock-parents sram mediatek,ethsys mediatek,sgmiisys mediatek,infracfg mediatek,wed phy-mode phy-is-integrated resets reset-names 