Ðþí  F   8  h   (            Þ  0                                                                   #   ,Arm Morello Fixed Virtual Platform           2arm,morello-fvp arm,morello    clock-50000000           2fixed-clock          =             Júð€      	   Zapb_pclk             m         clock-85000000           2fixed-clock          =             Jÿ@         Ziofpga:aclk       cpus                                 cpu@0            2arm,rainier          u                 ycpu          …psci             “                @         ²            ¿            Ì   @         Þ            ë            ü          l2-cache             2cache                       •            ¢   @         ´                     ë            m            cpu@100          2arm,rainier          u                ycpu          …psci             “                @         ²            ¿            Ì   @         Þ            ë            ü          l2-cache             2cache                       •            ¢   @         ´                     ë            m            cpu@10000            2arm,rainier          u                ycpu          …psci             “                @         ²            ¿            Ì   @         Þ            ë            ü         l2-cache             2cache                       •            ¢   @         ´                     ë            m            cpu@10100            2arm,rainier          u               ycpu          …psci             “                @         ²            ¿            Ì   @         Þ            ë            ü         l2-cache             2cache                       •            ¢   @         ´                     ë            m            l3-cache             2cache                       •                     m            firmware                    scmi          	   2arm,scmi            tx rx           (                           /   	   
                             protocol@13          u            =            m         protocol@14          u            =               memory@80000000          ymemory           u    €                memory@8080000000            ymemory           u   €€      x         pmu          2arm,rainier-pmu         5               psci             2arm,psci-0.2             Œsmc       reserved-memory                                   @   secure-firmware@ff000000             u    ÿ                   G         spe-pmu       '   2arm,statistical-profiling-extension-v1          5               soc          2simple-bus                                                 @   serial@2a400000          2arm,pl011 arm,primecell          u    *@                 5       ?            ü              Nuartclk apb_pclk            Zokay          interrupt-controller@30000000            2arm,gic-v3            u    0              0                 5      	           a            r                                  @         m      msi-controller@30040000          2arm,gic-v3-its           u    0                  ‡        –         msi-controller@30060000          2arm,gic-v3-its           u    0                  ‡        –         msi-controller@30080000          2arm,gic-v3-its           u    0                  ‡        –         msi-controller@300a0000          2arm,gic-v3-its           u    0
                  ‡        –            iommu@2ce00000           2arm,smmu-v3          u    ,à               $  5       L          P          N           ¡eventq gerror cmdq-sync         ±         mhu@45000000             2arm,mhu-doorbell arm,primecell           u    E                  5      >         <           ¾            ü         	  Napb_pclk             m         sram@6000000          
   2mmio-sram            u             €         @             €                             scp-sram@0           2arm,scmi-shmem           u       €         m   	      scp-sram@80          2arm,scmi-shmem           u   €   €         m   
            timer            2arm,armv8-timer       0  5                                 
         aliases         Ê/soc/serial@2a400000          chosen          Òserial0:115200n8          clock-24000000           2fixed-clock          =             Jn6          Zbp:clock24mhz            m         virtio-block@1c170000            2virtio,mmio          u                     5       `         virtio-net@1c180000          2virtio,mmio          u                     5       f         virtio-rng@1c190000          2virtio,mmio          u                     5       e         virtio-p9@1c1a0000           2virtio,mmio          u                     5       g         kmi@1c150000             2arm,pl050 arm,primecell          u                     5       c            ü              NKMIREFCLK apb_pclk        kmi@1c160000             2arm,pl050 arm,primecell          u                     5       d            ü              NKMIREFCLK apb_pclk        ethernet@1d100000            2smsc,lan91c111           u                     5       b            	interrupt-parent #address-cells #size-cells model compatible #clock-cells clock-frequency clock-output-names phandle reg device_type enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache clocks cache-level cache-unified mbox-names mboxes shmem interrupts ranges no-map clock-names status #interrupt-cells interrupt-controller msi-controller #msi-cells interrupt-names #iommu-cells #mbox-cells serial0 stdout-path 