  ,6   8  (   (            n  (                             "    beagle,beaglev-ahead thead,th1520                                    &BeagleV Ahead      cpus                                      , -   cpu@0             thead,c910 riscv             ?cpu          Krv64imafdc           Urv64i         (   di m a f d c zicntr zicsr zifencei zihpm          y             }   @                                    @                                             riscv,sv39     interrupt-controller              riscv,cpu-intc                                           cpu@1             thead,c910 riscv             ?cpu          Krv64imafdc           Urv64i         (   di m a f d c zicntr zicsr zifencei zihpm          y            }   @                                    @                                             riscv,sv39     interrupt-controller              riscv,cpu-intc                                           cpu@2             thead,c910 riscv             ?cpu          Krv64imafdc           Urv64i         (   di m a f d c zicntr zicsr zifencei zihpm          y            }   @                                    @                                             riscv,sv39     interrupt-controller              riscv,cpu-intc                                           cpu@3             thead,c910 riscv             ?cpu          Krv64imafdc           Urv64i         (   di m a f d c zicntr zicsr zifencei zihpm          y            }   @                                    @                                             riscv,sv39     interrupt-controller              riscv,cpu-intc                                           l2-cache              cache               @                                            +                    pmu       
    riscv,pmu           9                                             	   	    
   
                                                   U                                                            	   	       
   
                                                                                     H  n                                                                       	        
                                                                                                                                                                                         !        "        #        $        %        &        '        (        )        *       oscillator            fixed-clock         osc_24m                     n6                  32k-oscillator            fixed-clock         osc_32k                              soc           simple-bus                                                          interrupt-controller@ffd8000000       "    thead,th1520-plic thead,c900-plic            y                   @              	            	            	            	                                                              timer@ffdc000000          $    thead,th1520-clint thead,c900-clint          y                   @                                                        spi@ffe700c000        !    thead,th1520-spi snps,dw-apb-ssi             y                       6                 6                                 okay          serial@ffe7014000             snps,dw-apb-uart             y   @                   $                 U      7        baudclk apb_pclk            *           4           okay          mmc@ffe7080000            thead,th1520-dwcmshc             y                       >                 +        core            okay            A           K=         Y         h         v         ~      mmc@ffe7090000            thead,th1520-dwcmshc             y   	                    @                 +        core            okay            A           K=      mmc@ffe70a0000            thead,th1520-dwcmshc             y   
                    G                 +        core          	  disabled          serial@ffe7f00000             snps,dw-apb-uart             y                       %                 U      8        baudclk apb_pclk            *           4         	  disabled          serial@ffe7f04000             snps,dw-apb-uart             y   @                   '                 U      :        baudclk apb_pclk            *           4         	  disabled          gpio@ffe7f34000           snps,dw-apb-gpio             y   @                                               ?   gpio-controller@0             snps,dw-apb-gpio-port                                            y                                    :            gpio@ffe7f38000           snps,dw-apb-gpio             y                                                  1   gpio-controller@0             snps,dw-apb-gpio-port                                            y                                    ;            gpio@ffec005000           snps,dw-apb-gpio             y    P                                               =   gpio-controller@0             snps,dw-apb-gpio-port                                            y                                    8            gpio@ffec006000           snps,dw-apb-gpio             y    `                                               >   gpio-controller@0             snps,dw-apb-gpio-port                                            y                                    9            serial@ffec010000             snps,dw-apb-uart             y           @            &                 U      9        baudclk apb_pclk            *           4         	  disabled          clock-controller@ffef010000           thead,th1520-clk-ap          y                                                   dma-controller@ffefc00000             snps,axi-dma-1.01a           y                                                      core-clk cfgr-clk                                                                                                           okay          timer@ffefc32000              snps,dw-apb-timer            y                                  timer                       	  disabled          timer@ffefc32014              snps,dw-apb-timer            y                                 timer                       	  disabled          timer@ffefc32028              snps,dw-apb-timer            y    (                             timer                       	  disabled          timer@ffefc3203c              snps,dw-apb-timer            y    <                             timer                       	  disabled          serial@fff7f08000             snps,dw-apb-uart             y          @            (                 U      ;        baudclk apb_pclk            *           4         	  disabled          serial@fff7f0c000             snps,dw-apb-uart             y          @            )                 U      <        baudclk apb_pclk            *           4         	  disabled          timer@ffffc33000              snps,dw-apb-timer            y   0                              timer                       	  disabled          timer@ffffc33014              snps,dw-apb-timer            y   0                             timer                       	  disabled          timer@ffffc33028              snps,dw-apb-timer            y   0(                             timer                       	  disabled          timer@ffffc3303c              snps,dw-apb-timer            y   0<                             timer                       	  disabled          gpio@fffff41000           snps,dw-apb-gpio             y                                       gpio-controller@0             snps,dw-apb-gpio-port                                            y                                    L            gpio@fffff52000           snps,dw-apb-gpio             y                                        gpio-controller@0             snps,dw-apb-gpio-port                                            y                                    7               aliases         /soc/gpio@ffec005000            /soc/gpio@ffec006000            !/soc/gpio@ffe7f34000            '/soc/gpio@ffe7f38000            -/soc/serial@ffe7014000          5/soc/serial@ffe7f00000          =/soc/serial@ffec010000          E/soc/serial@ffe7f04000          M/soc/serial@fff7f08000          U/soc/serial@fff7f0c000          ]/soc/spi@ffe700c000       chosen          bserial0:115200n8          memory@0             ?memory           y                        	compatible #address-cells #size-cells model timebase-frequency device_type riscv,isa riscv,isa-base riscv,isa-extensions reg i-cache-block-size i-cache-size i-cache-sets d-cache-block-size d-cache-size d-cache-sets next-level-cache mmu-type interrupt-controller #interrupt-cells phandle cache-level cache-unified riscv,event-to-mhpmcounters riscv,event-to-mhpmevent riscv,raw-event-to-mhpmcounters clock-output-names #clock-cells clock-frequency interrupt-parent dma-noncoherent ranges interrupts-extended riscv,ndev interrupts clocks status clock-names reg-shift reg-io-width bus-width max-frequency mmc-hs400-1_8v non-removable no-sdio no-sd gpio-controller #gpio-cells ngpios #dma-cells dma-channels snps,block-size snps,priority snps,dma-masters snps,data-width snps,axi-max-burst-len gpio0 gpio1 gpio2 gpio3 serial0 serial1 serial2 serial3 serial4 serial5 spi0 stdout-path 