     8  @   (                                                                                 1   ,Toradex Colibri iMX8QXP on Colibri Iris V2 Board          @   2toradex,colibri-imx8x-iris-v2 toradex,colibri-imx8x fsl,imx8qxp    aliases           =/bus@5b000000/ethernet@5b040000           G/bus@5b000000/ethernet@5b050000          Q/bus@5d000000/gpio@5d080000          W/bus@5d000000/gpio@5d090000          ]/bus@5d000000/gpio@5d0a0000          c/bus@5d000000/gpio@5d0b0000          i/bus@5d000000/gpio@5d0c0000          o/bus@5d000000/gpio@5d0d0000          u/bus@5d000000/gpio@5d0e0000          {/bus@5d000000/gpio@5d0f0000          /bus@5a000000/i2c@5a800000           /bus@5a000000/i2c@5a810000           /bus@5a000000/i2c@5a820000           /bus@5a000000/i2c@5a830000           /bus@5b000000/mmc@5b010000           /bus@5b000000/mmc@5b020000           /bus@5b000000/mmc@5b030000           /bus@5d000000/mailbox@5d1b0000           /bus@5d000000/mailbox@5d1c0000           /bus@5d000000/mailbox@5d1d0000           /bus@5d000000/mailbox@5d1e0000           /bus@5d000000/mailbox@5d1f0000           /bus@5a000000/serial@5a060000            /bus@5a000000/serial@5a070000            /bus@5a000000/serial@5a080000            /bus@5a000000/serial@5a090000             /vpu@2c000000/vpu-core@2d080000           /vpu@2c000000/vpu-core@2d090000       "   /bus@5a000000/i2c@5a810000/rtc@68            /system-controller/rtc        cpus                                 cpu@0            cpu          2arm,cortex-a35                          psci                       !   @        3           @           M   @        _           l           }                                         
      cpu@1            cpu          2arm,cortex-a35                         psci                       !   @        3           @           M   @        _           l           }                                               cpu@2            cpu          2arm,cortex-a35                         psci                       !   @        3           @           M   @        _           l           }                                               cpu@3            cpu          2arm,cortex-a35                         psci                       !   @        3           @           M   @        _           l           }                                               l2-cache0            2cache                                          #   @        5                       opp-table            2operating-points-v2                        opp-900000000               5          B@         I      opp-1200000000              G                   I                  interrupt-controller@51a00000            2arm,gic-v3               Q             Q                                     ,      	                    reserved-memory                                   7   decoder-boot@84000000                                  >      encoder-boot@86000000                                   >      decoder-rpc@92000000                                   >      dsp@92400000                @                  >      	  Edisabled          encoder-rpc@94400000                @       p           >         pmu          2arm,cortex-a35-pmu          ,               psci             2arm,psci-1.0            smc       system-controller            2fsl,imx-scu         Ltx0 rx0 gip3          $  W                                 power-controller             2fsl,imx8qxp-scu-pd fsl,scu-pd           ^                    clock-controller             2fsl,imx8qxp-clk fsl,scu-clk         r                    pinctrl          2fsl,imx8qxp-iomuxc          default                          z   ad7879intgrp                     !           Q      adc0grp       0     d       `   c       `   h       `   g       `      atmeladaptergrp            N      !   M     !      atmelconnectorgrp                   !         !      canintgrp                    @      csictlgrp                                     csimclkgrp                   A      extio0grp              1     @      fec1grp       x     5          4          &       a   %     a   '       a   (       a   -       a   .       a   /       a   0      a           j      fec1slpgrp        x     5     A   4     A   &      A   %      A   '      A   (      A   -      A   .      A   /      A   0      A           k      flexcan0grp            j       !   i       !      flexcan1grp            l       !   k       !      flexcan2grp            n       !   m       !      gpioblongrp                  `      gpiohpdgrp             z             gpiokeysgrp               p A           |      hog0grp                  a             S                 a   ,                a             T                 a             U                 a   R                 a                                                               X                                 hog1grp                         hog2grp                         hogscfwgrp                          i2c0grp                 !        !           O      i2c0mipilvds0grp               t          u             i2c0mipilvds1grp               x          y             i2c1grp            v     !   w     !           T      lcdifgrp         ,     L      `   H      `   K      `   J      @         @   7      `         `   8      `   9      `   :      `   ;      `   <      `   =      `   >      `   ?      `   @      `   A      `   B      `   C      `   E      `   F      `   G      `   I      `   )      `   P      `      lpspi2grp         0     Y      !   Z      @   [      @   \      @           @      lpspi2cs2grp               *      !      lpuart0grp        0     o          p          i         j                 E      lpuart2grp             r          q                  H      lpuart3grp             m         n                 J      lpuart3ctrlgrp        H     {          V          W                                                K      pciebgrp          $          a        a          `      pwmagrp                   a   `      `      pwmbgrp            M      `           t      pwmcgrp            N      `           v      pwmdgrp                   a   O      `           x      sai0grp       0     ^     @   a     @   ]     @   _     @      sgtl5000grp                  A      sgtl5000usbclkgrp              e      !           P      usb3503agrp                  a      usbcdetgrp             3     @      usbh1reggrp                 @      usdhc1grp              	      A   
       !          !          !          !          !          !          !          !          !          A          !           ]      usdhc1-100mhzgrp               	      A   
       !          !          !          !          !          !          !          !          !          A          !           ^      usdhc1-200mhzgrp               	      A   
       !          !          !          !          !          !          !          !          !          A          !           _      usdhc2gpiogrp                   !           c      usdhc2gpioslpgrp                     `           g      usdhc2grp         T           A          !           !   !       !   "       !   #       !          !           b      usdhc2-100mhzgrp          T           A          !           !   !       !   "       !   #       !          !           d      usdhc2-200mhzgrp          T           A          !           !   !       !   "       !   #       !          !           e      usdhc2slpgrp          T           `         `          `   !      `   "      `   #      `          !           f      wifigrp                         gpioirisgrp       T                         R          U          T          ,         S                        uart1forceoffgrp                            uart23forceoffgrp              {             enable-3v3-vmmc-grp            X                  }      lvds-converter-grp        0     l          k                                               ocotp            2fsl,imx8qxp-scu-ocotp                                  keys          "   2fsl,imx8qxp-sc-key fsl,imx-sc-key              t      	  Edisabled          rtc          2fsl,imx8qxp-sc-rtc        watchdog          "   2fsl,imx8qxp-sc-wdt fsl,imx-sc-wdt              <      thermal-sensor        *   2fsl,imx8qxp-sc-thermal fsl,imx-sc-thermal                                  timer            2arm,armv8-timer       0  ,                                 
         clock-dummy          2fixed-clock         r                      
  clk_dummy                    clock-xtal32k            2fixed-clock         r                       xtal_32KHz        clock-xtal24m            2fixed-clock         r            n6         xtal_24MHz        thermal-zones      cpu0-thermal                       
               c   trips      trip0           ( _        4           passive            	      trip1           ( (        4        	   critical             cooling-maps       map0            ?   	      0  D   
                        clock-img-ipg            2fixed-clock         r                     img_ipg_clk                  bus@58000000             2simple-bus                                   7X       X         jpegdec@58400000            X@             ,      5           }                     S                     c          x                               2nxp,imx8qxp-jpgdec          Eokay          jpegenc@58450000            XE             ,      1           }                     S                     c          x                               2nxp,imx8qxp-jpgenc          Eokay          clock-controller@585d0000            2fsl,imx8qxp-lpcg            X]             r           }                           0  img_jpeg_dec_lpcg_clk img_jpeg_dec_lpcg_ipg_clk         x                      clock-controller@585f0000            2fsl,imx8qxp-lpcg            X_             r           }                           0  img_jpeg_enc_lpcg_clk img_jpeg_enc_lpcg_ipg_clk         x                         vpu@2c000000                                     7,       ,                  ,                  x           	  Edisabled       mailbox@2d000000             2fsl,imx6sx-mu           -              ,                            x           	  Edisabled                     mailbox@2d020000             2fsl,imx6sx-mu           -             ,                            x           	  Edisabled                     vpu-core@2d080000           -              2nxp,imx8q-vpu-decoder           x             Ltx0 tx1 rx        $  W                                     	  Edisabled          vpu-core@2d090000           -              2nxp,imx8q-vpu-encoder           x             Ltx0 tx1 rx        $  W                                     	  Edisabled             clock-cm40-ipg           2fixed-clock         r            )         cm40_ipg_clk                     bus@34000000             2simple-bus                                   74       4                      serial@37220000          2fsl,imx8qxp-lpuart          7"             ,              }                   	  ipg baud            S                cn6         x           	  Edisabled          i2c@37230000          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c         7#             ,   	           }                     per ipg         S                 cn6         x            	  Edisabled          intmux@37400000          2fsl,imx-intmux          7@                        `  ,                                                                                                            }           ipg         x     !      	  Edisabled                     clock-controller@37620000            2fsl,imx8qxp-lpcg            7b             r           }                                *  cm40_lpcg_uart_clk cm40_lpcg_uart_ipg_clk           x                      clock-controller@37630000            2fsl,imx8qxp-lpcg            7c             r           }                                 (  cm40_lpcg_i2c_clk cm40_lpcg_i2c_ipg_clk         x                          bus@53000000             2simple-bus                                   7S       S         gpu@53100000             2vivante,gc          S             ,       @           }                          core shader         S                          c)' 2        x               clock-audio-ipg          2fixed-clock         r            '         audio_ipg_clk                     clock-ext-aud-mclk0          2fixed-clock         r                        ext_aud_mclk0              /      clock-ext-aud-mclk1          2fixed-clock         r                        ext_aud_mclk1              0      clock-esai0-rx           2fixed-clock         r                        esai0_rx_clk               1      clock-esai0-rx-hf            2fixed-clock         r                        esai0_rx_hf_clk            2      clock-esai0-tx           2fixed-clock         r                        esai0_tx_clk               3      clock-esai0-tx-hf            2fixed-clock         r                        esai0_tx_hf_clk            4      clock-spdif0-rx          2fixed-clock         r                      
  spdif0_rx              5      clock-sai0-rx-bclk           2fixed-clock         r                        sai0_rx_bclk               6      clock-sai0-tx-bclk           2fixed-clock         r                        sai0_tx_bclk               7      clock-sai1-rx-bclk           2fixed-clock         r                        sai1_rx_bclk               8      clock-sai1-tx-bclk           2fixed-clock         r                        sai1_tx_bclk               9      clock-sai2-rx-bclk           2fixed-clock         r                        sai2_rx_bclk               :      clock-sai3-rx-bclk           2fixed-clock         r                        sai3_rx_bclk               ;      clock-sai4-rx-bclk           2fixed-clock         r                        sai4_rx_bclk               <      bus@59000000             2simple-bus                                   7Y       Y         asrc@59000000            2fsl,imx8qm-asrc         Y              ,      t         d  }                                                                                      mem ipg asrck_0 asrck_1 asrck_2 asrck_3 asrck_4 asrck_5 asrck_6 asrck_7 asrck_8 asrck_9 asrck_a asrck_b asrck_c asrck_d asrck_e asrck_f spba          `                                                                                            rxa rxb rxc txa txb txc           @                               x           	  Edisabled          esai@59010000            2fsl,imx8qm-esai         Y             ,                 }                              core extal fsys spba                                                rx tx           x           	  Edisabled          spdif@59020000           2fsl,imx8qm-spdif            Y             ,                        0  }                                            :  core rxtx0 rxtx1 rxtx2 rxtx3 rxtx4 rxtx5 rxtx6 rxtx7 spba                               	               rx tx           x           	  Edisabled          sai@59040000             2fsl,imx8qm-sai          Y             ,      :           }   !         !                  bus mclk0 mclk1 mclk2 mclk3         rx tx                                               x     >      	  Edisabled          sai@59050000             2fsl,imx8qm-sai          Y             ,      <           }   "         "                  bus mclk0 mclk1 mclk2 mclk3         rx tx                                               x     ?      	  Edisabled          sai@59060000             2fsl,imx8qm-sai          Y             ,      >           }   #         #                  bus mclk0 mclk1 mclk2 mclk3         rx                               x     @      	  Edisabled          sai@59070000             2fsl,imx8qm-sai          Y             ,      C           }   $         $                  bus mclk0 mclk1 mclk2 mclk3         rx                               x           	  Edisabled          dma-controller@591f0000          2fsl,imx8qm-edma         Y                                    \         ,      v         w         x         y         z         {                                                                   ;         ;         =         =         ?         D                                                                         x      @      A      B      C      D      E      F      G      H      I      J      K      L      M      N      O      P      Q      R      S      T      U      V      W                 clock-controller@59400000            2fsl,imx8qxp-lpcg            Y@             r           }                       asrc0_lpcg_ipg_clk          x                      clock-controller@59410000            2fsl,imx8qxp-lpcg            YA             r           }                               (  esai0_lpcg_extal_clk esai0_lpcg_ipg_clk         x                      clock-controller@59420000            2fsl,imx8qxp-lpcg            YB             r           }                               %  spdif0_lpcg_tx_clk spdif0_lpcg_gclkw            x                      clock-controller@59440000            2fsl,imx8qxp-lpcg            YD             r           }                               !  sai0_lpcg_mclk sai0_lpcg_ipg_clk            x     >           !      clock-controller@59450000            2fsl,imx8qxp-lpcg            YE             r           }                               !  sai1_lpcg_mclk sai1_lpcg_ipg_clk            x     ?           "      clock-controller@59460000            2fsl,imx8qxp-lpcg            YF             r           }                               !  sai2_lpcg_mclk sai2_lpcg_ipg_clk            x     @           #      clock-controller@59470000            2fsl,imx8qxp-lpcg            YG             r           }                               !  sai3_lpcg_mclk sai3_lpcg_ipg_clk            x                $      clock-controller@59590000            2fsl,imx8qxp-lpcg            YY             r           }                       dsp_ram_lpcg_ipg_clk            x           asrc@59800000            2fsl,imx8qm-asrc         Y             ,      |         d  }   %      %                                                                             mem ipg asrck_0 asrck_1 asrck_2 asrck_3 asrck_4 asrck_5 asrck_6 asrck_7 asrck_8 asrck_9 asrck_a asrck_b asrck_c asrck_d asrck_e asrck_f spba          `     &               &              &              &             &             &                  rxa rxb rxc txa txb txc           @                              x           	  Edisabled          sai@59820000             2fsl,imx8qm-sai          Y             ,      I           }   '         '                  bus mclk0 mclk1 mclk2 mclk3             &             &   	                rx tx           x           	  Edisabled               *      sai@59830000             2fsl,imx8qm-sai          Y             ,      K           }   (         (                  bus mclk0 mclk1 mclk2 mclk3            &   
                tx          x           	  Edisabled               +      amix@59840000            2fsl,imx8qm-audmix           Y             }   )            ipg         x                *   +      	  Edisabled          mqs@59850000             2fsl,imx8qm-mqs          Y             }   ,      ,          
  mclk core           x           	  Edisabled          dma-controller@599f0000          2fsl,imx8qm-edma         Y                                              ,      ~                                                                            J         J         L         X  x      l      m      n      o      p      q      r      s      t      u      v           &      clock-controller@59d00000            2fsl,imx8qxp-lpcg            Y             r           }     E                       aud_rec_clk0_lpcg_clk           x     E           -      clock-controller@59d10000            2fsl,imx8qxp-lpcg            Y             r           }                            aud_rec_clk1_lpcg_clk           x                .      clock-controller@59d20000            2fsl,imx8qxp-lpcg            Y             r           }     E                        aud_pll_div_clk0_lpcg_clk           x     E                 clock-controller@59d30000            2fsl,imx8qxp-lpcg            Y             r           }                             aud_pll_div_clk1_lpcg_clk           x                      clock-controller@59d50000            2fsl,imx8qxp-lpcg            Y             r           }                          mclkout0_lpcg_clk           x           clock-controller@59d60000            2fsl,imx8qxp-lpcg            Y             r           }                          mclkout1_lpcg_clk           x           acm@59e00000             2fsl,imx8qxp-acm         Y             r           x                         E                         >     ?     @                               X  }   -       .                     /   0   1   2   3   4   5   6   7   8   9   :   ;   <       aud_rec_clk0_lpcg_clk aud_rec_clk1_lpcg_clk aud_pll_div_clk0_lpcg_clk aud_pll_div_clk1_lpcg_clk ext_aud_mclk0 ext_aud_mclk1 esai0_rx_clk esai0_rx_hf_clk esai0_tx_clk esai0_tx_hf_clk spdif0_rx sai0_rx_bclk sai0_tx_bclk sai1_rx_bclk sai1_tx_bclk sai2_rx_bclk sai3_rx_bclk sai4_rx_bclk                   clock-controller@59c00000            2fsl,imx8qxp-lpcg            Y             r           }                       asrc1_lpcg_ipg_clk          x                %      clock-controller@59c20000            2fsl,imx8qxp-lpcg            Y             r           }                               !  sai4_lpcg_mclk sai4_lpcg_ipg_clk            x                '      clock-controller@59c30000            2fsl,imx8qxp-lpcg            Y             r           }                               !  sai5_lpcg_mclk sai5_lpcg_ipg_clk            x                (      clock-controller@59c40000            2fsl,imx8qxp-lpcg            Y             r           }                        amix_lpcg_ipg_clk           x                )      clock-controller@59c50000            2fsl,imx8qxp-lpcg            Y             r           }                               !  mqs0_lpcg_mclk mqs0_lpcg_ipg_clk            x                ,         clock-dma-ipg            2fixed-clock         r            '         dma_ipg_clk            M      bus@5a000000             2simple-bus                                   7Z       Z         spi@5a000000             2fsl,imx7ulp-spi         Z                                        ,      P                        }   =       =           per ipg         S      5           c         x      5      	  Edisabled          spi@5a010000             2fsl,imx7ulp-spi         Z                                       ,      Q                        }   >       >           per ipg         S      6           c         x      6      	  Edisabled          spi@5a020000             2fsl,imx7ulp-spi         Z                                       ,      R                        }   ?       ?           per ipg         S      7           c         x      7        Eokay            default            @           A             spi@5a030000             2fsl,imx7ulp-spi         Z                                       ,      S                        }   B       B           per ipg         S      8           c         x      8      	  Edisabled          serial@5a060000         Z             ,      Y           }   C      C          	  ipg baud            S      9           cĴ         x      9        rx tx               D             D   	                Eokay             2fsl,imx8qxp-lpuart          default            E      serial@5a070000         Z             ,      Z           }   F      F          	  ipg baud            S      :           cĴ         x      :        rx tx               D   
          D                 	  Edisabled             2fsl,imx8qxp-lpuart        serial@5a080000         Z             ,      [           }   G      G          	  ipg baud            S      ;           cĴ         x      ;        rx tx               D             D                   Eokay             2fsl,imx8qxp-lpuart          default            H      serial@5a090000         Z	             ,      \           }   I      I          	  ipg baud            S      <           cĴ         x      <        rx tx               D             D                   Eokay             2fsl,imx8qxp-lpuart          default            J   K      pwm@5a190000             2fsl,imx8qxp-pwm fsl,imx27-pwm           Z             ,                  }   L      L            ipg per         S                 cn6         %           x            dma-controller@5a1f0000          2fsl,imx8qm-edma         Z                                   ,                                                                                                                                                        x                                                                                              D      clock-controller@5a400000            2fsl,imx8qxp-lpcg            Z@             r           }      5      M                        spi0_lpcg_clk spi0_lpcg_ipg_clk         x      5           =      clock-controller@5a410000            2fsl,imx8qxp-lpcg            ZA             r           }      6      M                        spi1_lpcg_clk spi1_lpcg_ipg_clk         x      6           >      clock-controller@5a420000            2fsl,imx8qxp-lpcg            ZB             r           }      7      M                        spi2_lpcg_clk spi2_lpcg_ipg_clk         x      7           ?      clock-controller@5a430000            2fsl,imx8qxp-lpcg            ZC             r           }      8      M                        spi3_lpcg_clk spi3_lpcg_ipg_clk         x      8           B      clock-controller@5a460000            2fsl,imx8qxp-lpcg            ZF             r           }      9      M                     '  uart0_lpcg_baud_clk uart0_lpcg_ipg_clk          x      9           C      clock-controller@5a470000            2fsl,imx8qxp-lpcg            ZG             r           }      :      M                     '  uart1_lpcg_baud_clk uart1_lpcg_ipg_clk          x      :           F      clock-controller@5a480000            2fsl,imx8qxp-lpcg            ZH             r           }      ;      M                     '  uart2_lpcg_baud_clk uart2_lpcg_ipg_clk          x      ;           G      clock-controller@5a490000            2fsl,imx8qxp-lpcg            ZI             r           }      <      M                     '  uart3_lpcg_baud_clk uart3_lpcg_ipg_clk          x      <           I      clock-controller@5a590000            2fsl,imx8qxp-lpcg            ZY             r           }            M                     (  adma_pwm_lpcg_clk adma_pwm_lpcg_ipg_clk         x                 L      i2c@5a800000            Z    @         ,                  }   N       N           per ipg         S      `           cn6         x      `        Eokay          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c                                            default            O   P   touchscreen@2c           2adi,ad7879-1            default            Q           ,             R        ,              0           I   x        `           {                                          	  Edisabled             i2c@5a810000            Z    @         ,                  }   S       S           per ipg         S      a           cn6         x      a        Eokay          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c                                            default            T   rtc@68        	   2st,m41t0               h         i2c@5a820000            Z    @         ,                  }   U       U           per ipg         S      b           cn6         x      b      	  Edisabled          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c       i2c@5a830000            Z    @         ,                  }   V       V           per ipg         S      c           cn6         x      c      	  Edisabled          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c       adc@5a880000             2nxp,imx8qxp-adc                    Z             ,                               }   W       W           per ipg         S      e           cn6         x      e      	  Edisabled          can@5a8d0000             2fsl,imx8qm-flexcan          Z             ,                               }   X      X            ipg per         S      i           cbZ         x      i                              	  Edisabled          can@5a8e0000             2fsl,imx8qm-flexcan          Z             ,                               }   X      X            ipg per         S      i           cbZ         x      j                             	  Edisabled          can@5a8f0000             2fsl,imx8qm-flexcan          Z             ,                               }   X      X            ipg per         S      i           cbZ         x      k                             	  Edisabled          dma-controller@5a9f0000          2fsl,imx8qm-edma         Z   	                              `  ,                                                                              @  x                                              clock-controller@5ac00000            2fsl,imx8qxp-lpcg            Z             r           }      `      M                        i2c0_lpcg_clk i2c0_lpcg_ipg_clk         x      `           N      clock-controller@5ac10000            2fsl,imx8qxp-lpcg            Z             r           }      a      M                        i2c1_lpcg_clk i2c1_lpcg_ipg_clk         x      a           S      clock-controller@5ac20000            2fsl,imx8qxp-lpcg            Z             r           }      b      M                        i2c2_lpcg_clk i2c2_lpcg_ipg_clk         x      b           U      clock-controller@5ac30000            2fsl,imx8qxp-lpcg            Z             r           }      c      M                        i2c3_lpcg_clk i2c3_lpcg_ipg_clk         x      c           V      clock-controller@5ac80000            2fsl,imx8qxp-lpcg            Z             r           }      e      M                        adc0_lpcg_clk adc0_lpcg_ipg_clk         x      e           W      clock-controller@5acd0000            2fsl,imx8qxp-lpcg            Z             r           }      i      M   M                        5  can0_lpcg_pe_clk can0_lpcg_ipg_clk can0_lpcg_chi_clk            x      i           X         clock-conn-axi           2fixed-clock         r            CU        conn_axi_clk               q      clock-conn-ahb           2fixed-clock         r            	!        conn_ahb_clk               r      clock-conn-ipg           2fixed-clock         r                    conn_ipg_clk               p      bus@5b000000             2simple-bus                                   7[       [         usb@5b0d0000          -   2fsl,imx7ulp-usb fsl,imx6ul-usb fsl,imx27-usb            [                          ,                    Y           Z            }   [                       $           8           x           	  Edisabled          usbmisc@5b0d0200            L         8   2fsl,imx7ulp-usbmisc fsl,imx7d-usbmisc fsl,imx6q-usbmisc         [               Z      usbphy@5b100000          2fsl,imx7ulp-usbphy          [             }   [           x           	  Edisabled               Y      mmc@5b010000            ,                  [             }   \      \      \            ipg ahb per         x              Eokay          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc           Y            c         q         w      "  default state_100mhz state_200mhz              ]           ^           _      mmc@5b020000            ,                  [             }   `      `      `            ipg ahb per         x                                    Eokay          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc           Y              R   	              a      (  default state_100mhz state_200mhz sleep            b   c           d   c           e   c           f   g                        mmc@5b030000            ,                  [             }   h      h      h            ipg ahb per         x            	  Edisabled          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc         ethernet@5b040000           [           0  ,                                              }   i      i      i      i            ipg ahb enet_clk_ref ptp            S                          c沀sY@                              x              Eokay          .   2fsl,imx8qxp-fec fsl,imx8qm-fec fsl,imx6sx-fec           default sleep              j           k        rmii            "   l         -   mdio                                 ethernet-phy@2           2ethernet-phy-ieee802.3-c22          >   d                      l            ethernet@5b050000           [           0  ,                                             }   m      m      m      m            ipg ahb enet_clk_ref ptp            S                          c沀sY@                              x            	  Edisabled          .   2fsl,imx8qxp-fec fsl,imx8qm-fec fsl,imx6sx-fec         usb@5b110000             2fsl,imx8qm-usb3         [                                       7      (  }   n      n       n      n      n           lpm bus aclk ipg core           S                c沀        x           	  Edisabled       usb@5b120000          
   2cdns,usb3           [     [     [             Hotg xhci dev                       0  ,                                            Rhost peripheral otg wakeup          b   o        gcdns3,usb3-phy          q         	  Edisabled             usb-phy@5b160000             2nxp,salvo-phy           [             }   n           salvo_phy_clk           x                       	  Edisabled               o      clock-controller@5b200000            2fsl,imx8qxp-lpcg            [              r           }            p   q                        9  sdhc0_lpcg_per_clk sdhc0_lpcg_ipg_clk sdhc0_lpcg_ahb_clk            x                 \      clock-controller@5b210000            2fsl,imx8qxp-lpcg            [!             r           }            p   q                        9  sdhc1_lpcg_per_clk sdhc1_lpcg_ipg_clk sdhc1_lpcg_ahb_clk            x                 `      clock-controller@5b220000            2fsl,imx8qxp-lpcg            ["             r           }            p   q                        9  sdhc2_lpcg_per_clk sdhc2_lpcg_ipg_clk sdhc2_lpcg_ahb_clk            x                 h      clock-controller@5b230000            2fsl,imx8qxp-lpcg            [#             r         0  }                     q            p   p                                   enet0_lpcg_timer_clk enet0_lpcg_txc_sampling_clk enet0_lpcg_ahb_clk enet0_lpcg_rgmii_txc_clk enet0_lpcg_ipg_clk enet0_lpcg_ipg_s_clk            x                 i      clock-controller@5b240000            2fsl,imx8qxp-lpcg            [$             r         0  }                     q            p   p                                   enet1_lpcg_timer_clk enet1_lpcg_txc_sampling_clk enet1_lpcg_ahb_clk enet1_lpcg_rgmii_txc_clk enet1_lpcg_ipg_clk enet1_lpcg_ipg_s_clk            x                 m      clock-controller@5b270000            2fsl,imx8qxp-lpcg            ['             r           }   r   p                    "  usboh3_ahb_clk usboh3_phy_ipg_clk           x                [      clock-controller@5b280000            2fsl,imx8qxp-lpcg            [(             r                                    0  }                   p   p   p              M  usb3_app_clk usb3_lpm_clk usb3_ipg_clk usb3_core_pclk usb3_phy_clk usb3_aclk            x                n         bus@5c000000             2simple-bus                                   7\       \         ddr-pmu@5c020000             2fsl,imx8-ddr-pmu            \             ,                   clock-lsio-bus           2fixed-clock         r                     lsio_bus_clk               {      bus@5d000000             2simple-bus                                    7]       ]                      pwm@5d000000             2fsl,imx27-pwm           ]              ipg per         }   s      s           S                 cn6         %           ,       ^           Eokay               t        default       pwm@5d010000             2fsl,imx27-pwm           ]             ipg per         }   u      u           S                 cn6         %           ,       _           Eokay               v        default       pwm@5d020000             2fsl,imx27-pwm           ]             ipg per         }   w      w           S                 cn6         %           ,       `           Eokay               x        default       pwm@5d030000             2fsl,imx27-pwm           ]             ipg per         }   y      y           S                 cn6         %           ,       a         	  Edisabled          gpio@5d080000           ]             ,                                                          x                2fsl,imx8qxp-gpio fsl,imx35-gpio       P     z      8      z      E      z      K      z      P      z      R           SODIMM_70 SODIMM_60 SODIMM_58 SODIMM_78 SODIMM_72 SODIMM_80 SODIMM_46 SODIMM_62 SODIMM_48 SODIMM_74 SODIMM_50 SODIMM_52 SODIMM_54 SODIMM_66 SODIMM_64 SODIMM_68   SODIMM_82 SODIMM_56 SODIMM_28 SODIMM_30  SODIMM_61 SODIMM_103    SODIMM_25 SODIMM_27 SODIMM_100             ~      gpio@5d090000           ]	             ,                                                          x                2fsl,imx8qxp-gpio fsl,imx35-gpio       0     z       Y   	   z   	   c      z      t          SODIMM_86 SODIMM_92 SODIMM_90 SODIMM_88    SODIMM_59  SODIMM_6 SODIMM_8   SODIMM_2 SODIMM_4 SODIMM_34 SODIMM_32 SODIMM_63 SODIMM_55 SODIMM_33 SODIMM_35 SODIMM_36 SODIMM_38 SODIMM_21 SODIMM_19 SODIMM_140 SODIMM_142 SODIMM_196 SODIMM_194 SODIMM_186 SODIMM_188 SODIMM_138               A      gpio@5d0a0000           ]
             ,                                                          x                2fsl,imx8qxp-gpio fsl,imx35-gpio       0     z       {      z      ~      z                 SODIMM_23   SODIMM_144        gpio@5d0b0000           ]             ,                                                          x                2fsl,imx8qxp-gpio fsl,imx35-gpio       0     z             z            z                 SODIMM_96 SODIMM_75 SODIMM_37 SODIMM_29      SODIMM_43 SODIMM_45 SODIMM_69 SODIMM_71 SODIMM_73 SODIMM_77 SODIMM_89 SODIMM_93 SODIMM_95 SODIMM_99 SODIMM_105 SODIMM_107 SODIMM_98 SODIMM_102 SODIMM_104 SODIMM_106              R   lvds-tx-on-hog                                            gpio@5d0c0000           ]             ,                                                          x                2fsl,imx8qxp-gpio fsl,imx35-gpio            z              z            z      	      z            z            z            z            z      %              SODIMM_129 SODIMM_133 SODIMM_127 SODIMM_131             SODIMM_44  SODIMM_76 SODIMM_31 SODIMM_47 SODIMM_190 SODIMM_192 SODIMM_49 SODIMM_51 SODIMM_53       gpio@5d0d0000           ]             ,                                                          x                2fsl,imx8qxp-gpio fsl,imx35-gpio       0     z       (      z      ,      z   	   3         a   SODIMM_57 SODIMM_65 SODIMM_85     SODIMM_135 SODIMM_137 UNUSABLE_SODIMM_180 UNUSABLE_SODIMM_184          gpio@5d0e0000           ]             ,                                                          x                2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0f0000           ]             ,                                                          x                2fsl,imx8qxp-gpio fsl,imx35-gpio       spi@5d120000                                       2nxp,imx8qxp-fspi            ]                   Hfspi_base fspi_mmap         ,       \           }                          fspi_en fspi            x            	  Edisabled          mailbox@5d1b0000            ]             ,                           	  Edisabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1c0000            ]             ,                           -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu                     mailbox@5d1d0000            ]             ,                           	  Edisabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1e0000            ]             ,                           	  Edisabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1f0000            ]             ,                           	  Edisabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d200000            ]              ,                             x            	  Edisabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d210000            ]!             ,                             x            	  Edisabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d280000            ](             ,                             x               2fsl,imx8qxp-mu fsl,imx6sx-mu          clock-controller@5d400000            2fsl,imx8qxp-lpcg            ]@             r         4  }                              {                                       h  pwm0_lpcg_ipg_clk pwm0_lpcg_ipg_hf_clk pwm0_lpcg_ipg_s_clk pwm0_lpcg_ipg_slv_clk pwm0_lpcg_ipg_mstr_clk         x                 s      clock-controller@5d410000            2fsl,imx8qxp-lpcg            ]A             r         4  }                              {                                       h  pwm1_lpcg_ipg_clk pwm1_lpcg_ipg_hf_clk pwm1_lpcg_ipg_s_clk pwm1_lpcg_ipg_slv_clk pwm1_lpcg_ipg_mstr_clk         x                 u      clock-controller@5d420000            2fsl,imx8qxp-lpcg            ]B             r         4  }                              {                                       h  pwm2_lpcg_ipg_clk pwm2_lpcg_ipg_hf_clk pwm2_lpcg_ipg_s_clk pwm2_lpcg_ipg_slv_clk pwm2_lpcg_ipg_mstr_clk         x                 w      clock-controller@5d430000            2fsl,imx8qxp-lpcg            ]C             r         4  }                              {                                       h  pwm3_lpcg_ipg_clk pwm3_lpcg_ipg_hf_clk pwm3_lpcg_ipg_s_clk pwm3_lpcg_ipg_slv_clk pwm3_lpcg_ipg_mstr_clk         x                 y      clock-controller@5d440000            2fsl,imx8qxp-lpcg            ]D             r         4  }                              {                                       h  pwm4_lpcg_ipg_clk pwm4_lpcg_ipg_hf_clk pwm4_lpcg_ipg_s_clk pwm4_lpcg_ipg_slv_clk pwm4_lpcg_ipg_mstr_clk         x            clock-controller@5d450000            2fsl,imx8qxp-lpcg            ]E             r         4  }                              {                                       h  pwm5_lpcg_ipg_clk pwm5_lpcg_ipg_hf_clk pwm5_lpcg_ipg_s_clk pwm5_lpcg_ipg_slv_clk pwm5_lpcg_ipg_mstr_clk         x            clock-controller@5d460000            2fsl,imx8qxp-lpcg            ]F             r         4  }                              {                                       h  pwm6_lpcg_ipg_clk pwm6_lpcg_ipg_hf_clk pwm6_lpcg_ipg_s_clk pwm6_lpcg_ipg_slv_clk pwm6_lpcg_ipg_mstr_clk         x            clock-controller@5d470000            2fsl,imx8qxp-lpcg            ]G             r         4  }                              {                                       h  pwm7_lpcg_ipg_clk pwm7_lpcg_ipg_hf_clk pwm7_lpcg_ipg_s_clk pwm7_lpcg_ipg_slv_clk pwm7_lpcg_ipg_mstr_clk         x               chosen          /bus@5a000000/serial@5a090000         gpio-keys         
   2gpio-keys           default            |        Eokay       key-wakeup             
           R   
            Wake-Up                              regulator-module-3v3             2regulator-fixed         +V3.3           , 2Z        D 2Z      regulator-3v3            2regulator-fixed         D 2Z        , 2Z        3.3V          regulator-3v3-vmmc           2regulator-fixed         default            }         \        o   ~               D 2Z        , 2Z      	  3v3_vmmc            t   d           a         	interrupt-parent #address-cells #size-cells model compatible ethernet0 ethernet1 gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 i2c0 i2c1 i2c2 i2c3 mmc0 mmc1 mmc2 mu0 mu1 mu2 mu3 mu4 serial0 serial1 serial2 serial3 vpu-core0 vpu-core1 rtc0 rtc1 device_type reg enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache clocks operating-points-v2 #cooling-cells phandle cache-level cache-unified opp-shared opp-hz opp-microvolt clock-latency-ns opp-suspend #interrupt-cells interrupt-controller interrupts ranges no-map status mbox-names mboxes #power-domain-cells #clock-cells pinctrl-names pinctrl-0 fsl,pins linux,keycodes timeout-sec #thermal-sensor-cells clock-frequency clock-output-names polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device assigned-clocks assigned-clock-rates power-domains slot clock-indices #mbox-cells clock-names dmas dma-names fsl,asrc-rate fsl,asrc-width fsl,asrc-clk-map #dma-cells dma-channels dma-channel-mask dais cs-gpios #pwm-cells touchscreen-max-pressure adi,resistance-plate-x adi,first-conversion-delay adi,acquisition-time adi,median-filter-size adi,averaging adi,conversion-interval #io-channel-cells fsl,clk-source fsl,scu-index fsl,usbphy fsl,usbmisc ahb-burst-config tx-burst-size-dword rx-burst-size-dword #index-cells bus-width non-removable no-sd no-sdio pinctrl-1 pinctrl-2 fsl,tuning-start-tap fsl,tuning-step cd-gpios vmmc-supply pinctrl-3 disable-wp cap-power-off-card fsl,num-tx-queues fsl,num-rx-queues phy-mode phy-handle fsl,magic-packet max-speed reg-names interrupt-names phys phy-names cdns,on-chip-buff-size #phy-cells gpio-controller #gpio-cells gpio-ranges gpio-line-names gpio-hog output-high stdout-path debounce-interval label linux,code wakeup-source regulator-name regulator-min-microvolt regulator-max-microvolt enable-active-high gpio startup-delay-us 