  ʁ   8  d   (              ,                                                                   9   ,Toradex Apalis iMX8QM/QP on Apalis Evaluation Board V1.2          =   2toradex,apalis-imx8-eval-v1.2 toradex,apalis-imx8 fsl,imx8qm       aliases          =/bus@5b000000/mmc@5b010000           B/bus@5b000000/mmc@5b020000           G/bus@5b000000/mmc@5b030000           L/bus@5a000000/serial@5a060000            T/bus@5a000000/serial@5a070000            \/bus@5a000000/serial@5a080000            d/bus@5a000000/serial@5a090000             l/vpu@2c000000/vpu-core@2d080000           v/vpu@2c000000/vpu-core@2d090000           /vpu@2c000000/vpu-core@2d0a0000       "   /bus@5a000000/i2c@5a820000/rtc@68            /system-controller/rtc        cpus                                 cpu-map    cluster0       core0                     core1                     core2                     core3                        cluster1       core0                     core1                           cpu@0            cpu          2arm,cortex-a53                                               psci                            @                                    @                      	        &   
        :           I         cpu@1            cpu          2arm,cortex-a53                                              psci                            @                                    @                      	        &   
        :           I         cpu@2            cpu          2arm,cortex-a53                                              psci                            @                                    @                      	        &   
        :           I         cpu@3            cpu          2arm,cortex-a53                                              psci                            @                                    @                      	        &   
        :           I         cpu@100          cpu          2arm,cortex-a72                                             psci                            @                                    @                              &           :           I         cpu@101          cpu          2arm,cortex-a72                                            psci                       &           :           I         l2-cache0            2cache           Q            ]                        @                    I   	      l2-cache1            2cache           Q            ]                        @                    I            opp-table-0          2operating-points-v2          k        I   
   opp-600000000           v    #F         }          I      opp-896000000           v    5g         } B@         I      opp-1104000000          v    Aʹ         }          I      opp-1200000000          v    G         }          I                  opp-table-1          2operating-points-v2          k        I      opp-600000000           v    #F         } B@         I      opp-1056000000          v    >H         } B@         I      opp-1296000000          v    M?d         }          I      opp-1596000000          v    _!         }          I                  interrupt-controller@51a00000            2arm,gic-v3        P       Q             Q             R               R             R                                           	                        I         pmu          2arm,armv8-pmuv3                        psci             2arm,psci-1.0             smc       timer            2arm,armv8-timer       0                                   
         iommu@51400000           2arm,mmu-500                           Q@                                                                                                                                                                                                                                                                                                                                                                                                                         I   c      system-controller            2fsl,imx-scu         tx0 rx0 gip3          $                                   power-controller             2fsl,imx8qm-scu-pd fsl,scu-pd                       I   #      clock-controller             2fsl,imx8qm-clk fsl,scu-clk                     I         pinctrl          2fsl,imx8qm-iomuxc           ,default       H  :                                                              I      adc0grp       0  D         `         `         `         `        I   Q      adc1grp       0  D         `         `         `         `        I   S      cam1gpiosgrp            D   C      !   D      !   l      !   m      !   n      !   o      !   p      !   q      !   r      !   c      !   j      !   k      !        I         dap1gpiosgrp          T  D   d      !         !   X      !   y      !         !   ~      !   ^      !        I         esai0gpiosgrp           D   h      !   i      !        I         fec1grp         D                                                                                                                                                                  9         3     `        I   w      fec1-sleepgrp           D                 @        @        @        @        @        @        @        @        @        @        @        @        @        @        @   9     @   3     @        I   x      fec2gpiosgrp            D                 !         !         !        !        !  	      !  
      !        !        !         !        !        !        !        I         flexcan0grp         D          !          !        I   U      flexcan1grp         D          !          !        I   X      flexcan2grp         D          !          !        I   [      gpio1grp            D   	     !      gpio2grp            D   
     !      gpio3grp            D        !        I         gpio4grp            D        !        I         gpio5grp            D        !        I   L      gpio6grp            D         !        I   M      gpio7grp            D         !        I         gpio8grp            D         !        I         gpiobklongrp            D   2      !        I         gpiokeysgrp         D   e   p !        I         gpiousbhocngrp          D        !        I         hdmictrlgrp         D   N      a        I         lpi2c1grp           D                          I   E      lpi2c2grp           D                          I   J      lpi2c3grp           D                          I   O      lpspi0grp         0  D   u      L   v      L   w      L   x     L        I   1      lpspi2grp         0  D   z      L   {      L   |      L   }     L        I   5      lpuart0grp          D                            I   9      lpuart1grp        0  D                                                I   ;      lpuart1ctrlgrp        0  D         !         !         !         !        I         lpuart2grp          D   6         7              I   =      lpuart3grp        0  D   <         =                              I   ?      lvds0i2c0gpiogrp            D   4      !        I         lvds1i2c0gpiosgrp           D   :      !   ;      !        I         mipidsi0-1engrp         D   5      !        I         mipidsi1gpiosgrp            D   E      !        I         mlbgpiosgrp         D         !        I         mmc1cdgrp           D   Z      !        I   i      mmc1cdsleepgrp          D   Z     !        I   m      pciebgrp          $  D         !         !         !      pciesatarefclkgrp           D         !        I         pciewifirefclkgrp           D   \      !        I         pwm0grp         D                  I         pwm1grp         D                  I         pwm2grp         D                  I         pwm3grp         D                  I         pwmbklgrp           D   8             qspi1agpiosgrp        `  D         !         !         !         !         !         !         !         !        I         resetmocigrp            D   &      !      sai1grp       0  D         l         L         L         L      sata1actgrp         D   Y      !        I         sd1cdgrp            D         !        I   r      sgtl5000grp         D   s      L      sim0gpiosgrp          0  D          !         !         !         !        I         spdif0grp           D   `      @   _      @      touchctrlgpiosgrp         0  D   U      !   V      A   b      !   f      A        I         touchctrlidlegrp          0  D         !         !         !         !        I         usbh1activegrp          D                          usbh1idlegrp            D                          usb3503agrp       $  D   '      A   )      !   *      A        I   F      usbhengrp           D         !        I         usbotg1grp          D         !        !        I   `      usdhc1grp           D         A          !          !          !          !          !          !          !          !          !         A          !        I   d      usdhc1-100mhzgrp            D         @                                                                                                            @                   I   e      usdhc1-200mhzgrp            D         @                                                                                                            @                   I   f      usdhc1gpiosgrp          D         !        I         usdhc2grp4bitgrp          T  D         A          !          !          !          !          !          !        I   h      usdhc2-4bit100mhzgrp          T  D         @                                                                 !        I   j      usdhc2-4bit200mhzgrp          T  D         @                                                                 !        I   k      usdhc2grp8bitgrp          0  D          !          !          !          !      usdhc2-8bit100mhzgrp          0  D                                                  usdhc2-8bit200mhzgrp          0  D                                                  usdhc2-4bitsleepgrp       T  D         a         a         a         a         a         a          !        I   l      usdhc2-8bitsleepgrp       0  D         a         a         a         a      usdhc3grp         T  D         A          !          !          !          !          !          !        I   q      usdhc3-100mhzgrp          T  D         A          !          !          !          !          !          !        I   s      usdhc3-200mhzgrp          T  D         A          !          !          !          !          !          !        I   t      wifigrp         D   +     !   H     !      wifipdngrp          D   L     !        I         lpi2c0grp           D   R     "   S     "        I   C      enable3v3mmcgrp         D         !        I         enable3v3sdgrp          D         !        I         enablecan1powergrp          D         !        I         enablecan2powergrp          D         !        I            rtc          2fsl,imx8qxp-sc-rtc        thermal-sensor        *   2fsl,imx8qxp-sc-thermal fsl,imx-sc-thermal           M           I             thermal-zones      cpu0-thermal            c           y                     trips      trip0                               passive         I   !      trip1                            	   critical             cooling-maps       map0               !      0                          cpu1-thermal            c           y                    trips      trip0                               passive         I   "      trip1                            	   critical             cooling-maps       map0               "                          gpu0-thermal            c           y                    trips      trip0                               passive       trip1                            	   critical                gpu1-thermal            c           y                    trips      trip0                               passive       trip1                            	   critical                drc0-thermal            c           y                    trips      trip0                               passive       trip1                            	   critical                   vpu@2c000000                                     ,       ,                   ,                     #          okay             2nxp,imx8qm-vpu     mailbox@2d000000             2fsl,imx6sx-mu            -                                             #          okay            I   $      mailbox@2d020000             2fsl,imx6sx-mu            -                                            #          okay            I   '      mailbox@2d040000             2fsl,imx6sx-mu            -                                            #          okay            I   *      vpu-core@2d080000            -              2nxp,imx8q-vpu-decoder              #          tx0 tx1 rx        $     $           $          $               okay               %   &      vpu-core@2d090000            -	              2nxp,imx8q-vpu-encoder              #          tx0 tx1 rx        $     '           '          '               okay               (   )      vpu-core@2d0a0000            -
              2nxp,imx8q-vpu-encoder              #          tx0 tx1 rx        $     *           *          *               okay               +   ,         clock-img-ipg            2fixed-clock                              img_ipg_clk         I   /      bus@58000000             2simple-bus                                   X       X         jpegdec@58400000             X@                   5               -       -              -       -           +             #     #          @          %   2nxp,imx8qm-jpgdec nxp,imx8qxp-jpgdec            okay          jpegenc@58450000             XE                   1               .       .              .       .           +             #     #          @          %   2nxp,imx8qm-jpgenc nxp,imx8qxp-jpgenc            okay          clock-controller@585d0000            2fsl,imx8qxp-lpcg             X]                            /   /        E             0  img_jpeg_dec_lpcg_clk img_jpeg_dec_lpcg_ipg_clk            #          I   -      clock-controller@585f0000            2fsl,imx8qxp-lpcg             X_                            /   /        E             0  img_jpeg_enc_lpcg_clk img_jpeg_enc_lpcg_ipg_clk            #          I   .         clock-dma-ipg            2fixed-clock                     '         dma_ipg_clk         I   A      bus@5a000000             2simple-bus                                   Z       Z         spi@5a000000             2fsl,imx7ulp-spi          Z                                              P                            0       0           Sper ipg               5           +            #   5        okay            ,default         :   1        _   2            spi@5a010000             2fsl,imx7ulp-spi          Z                                             Q                            3       3           Sper ipg               6           +            #   6      	  disabled          spi@5a020000             2fsl,imx7ulp-spi          Z                                             R                            4       4           Sper ipg               7           +            #   7        okay            ,default         :   5        _   2   
         spi@5a030000             2fsl,imx7ulp-spi          Z                                             S                            6       6           Sper ipg               8           +            #   8      	  disabled          serial@5a060000          Z                   Y               7      7          	  Sipg baud                  9           +Ĵ            #   9        hrx tx            r   8              8                  okay          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart            ,default         :   9      serial@5a070000          Z                   Z               :      :          	  Sipg baud                  :           +Ĵ            #   :        hrx tx            r   8              8                  okay          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart            ,default         :   ;      serial@5a080000          Z                   [               <      <          	  Sipg baud                  ;           +Ĵ            #   ;        hrx tx            r   8              8                  okay          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart            ,default         :   =      serial@5a090000          Z	                   \               >      >          	  Sipg baud                  <           +Ĵ            #   <        hrx tx            r   8              8                  okay          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart            ,default         :   ?      pwm@5a190000             2fsl,imx8qxp-pwm fsl,imx27-pwm            Z                                   @      @            Sipg per                          +n6         w              #         dma-controller@5a1f0000          2fsl,imx8qm-edma          Z                                                                                                                                                                                                                                                           #   @   #   A   #   B   #   C   #   D   #   E   #   F   #   G   #   H   #   I   #   J   #   K   #   L   #   M   #   N   #   O   #   P   #   Q   #   R   #   S   #   T   #   U                   okay            I   8      clock-controller@5a400000            2fsl,imx8qxp-lpcg             Z@                               5      A        E                spi0_lpcg_clk spi0_lpcg_ipg_clk            #   5        I   0      clock-controller@5a410000            2fsl,imx8qxp-lpcg             ZA                               6      A        E                spi1_lpcg_clk spi1_lpcg_ipg_clk            #   6        I   3      clock-controller@5a420000            2fsl,imx8qxp-lpcg             ZB                               7      A        E                spi2_lpcg_clk spi2_lpcg_ipg_clk            #   7        I   4      clock-controller@5a430000            2fsl,imx8qxp-lpcg             ZC                               8      A        E                spi3_lpcg_clk spi3_lpcg_ipg_clk            #   8        I   6      clock-controller@5a460000            2fsl,imx8qxp-lpcg             ZF                               9      A        E             '  uart0_lpcg_baud_clk uart0_lpcg_ipg_clk             #   9        I   7      clock-controller@5a470000            2fsl,imx8qxp-lpcg             ZG                               :      A        E             '  uart1_lpcg_baud_clk uart1_lpcg_ipg_clk             #   :        I   :      clock-controller@5a480000            2fsl,imx8qxp-lpcg             ZH                               ;      A        E             '  uart2_lpcg_baud_clk uart2_lpcg_ipg_clk             #   ;        I   <      clock-controller@5a490000            2fsl,imx8qxp-lpcg             ZI                               <      A        E             '  uart3_lpcg_baud_clk uart3_lpcg_ipg_clk             #   <        I   >      clock-controller@5a590000            2fsl,imx8qxp-lpcg             ZY                                     A        E             (  adma_pwm_lpcg_clk adma_pwm_lpcg_ipg_clk            #           I   @      i2c@5a800000             Z    @                               B       B           Sper ipg               `           +n6            #   `      	  disabled          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c          ,default         :   C                                         i2c@5a810000             Z    @                               D       D           Sper ipg               a           +n6            #   a        okay          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c          ,default         :   E                                      usb-hub@8            2smsc,usb3503a                       ,default         :   F           G                            H               }x@           H               i2c@5a820000             Z    @                               I       I           Sper ipg               b           +n6            #   b        okay          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c          ,default         :   J                                      touch@4a             2atmel,maxtouch              J             K                      ,default         :   L   M           K            	  disabled          rtc@68        	   2st,m41t0                h        okay          hwmon@40          
   2ti,ina219               @                temperature-sensor@4f         
   2ti,tmp75c               O      eeprom@57            2st,24c02 atmel,24c02                W         i2c@5a830000             Z    @                               N       N           Sper ipg               c           +n6            #   c        okay          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c          ,default         :   O                                         adc@5a880000             2nxp,imx8qxp-adc                     Z                                                P       P           Sper ipg               e           +n6            #   e        okay            ,default         :   Q      adc@5a890000             2nxp,imx8qxp-adc                     Z                                                R       R           Sper ipg               f           +n6            #   f        okay            ,default         :   S        I         can@5a8d0000             2fsl,imx8qm-flexcan           Z                                                T      T            Sipg per               i           +bZ            #   i                               okay            ,default         :   U        ,   V      can@5a8e0000             2fsl,imx8qm-flexcan           Z                                                W      W            Sipg per               j           +bZ            #   j                              okay            ,default         :   X        ,   Y      can@5a8f0000             2fsl,imx8qm-flexcan           Z                                                Z      Z            Sipg per               k           +bZ            #   k                            	  disabled            ,default         :   [      dma-controller@5a9f0000          2fsl,imx8qm-edma          Z   !                        
      x                                                                                                  P     #   l   #   m   #   n   #   o   #   p   #   q   #   r   #   s   #   t   #   u      clock-controller@5ac00000            2fsl,imx8qxp-lpcg             Z                               `      A        E                i2c0_lpcg_clk i2c0_lpcg_ipg_clk            #   `        I   B      clock-controller@5ac10000            2fsl,imx8qxp-lpcg             Z                               a      A        E                i2c1_lpcg_clk i2c1_lpcg_ipg_clk            #   a        I   D      clock-controller@5ac20000            2fsl,imx8qxp-lpcg             Z                               b      A        E                i2c2_lpcg_clk i2c2_lpcg_ipg_clk            #   b        I   I      clock-controller@5ac30000            2fsl,imx8qxp-lpcg             Z                               c      A        E                i2c3_lpcg_clk i2c3_lpcg_ipg_clk            #   c        I   N      clock-controller@5ac80000            2fsl,imx8qxp-lpcg             Z                               e      A        E                adc0_lpcg_clk adc0_lpcg_ipg_clk            #   e        I   P      clock-controller@5ac90000            2fsl,imx8qxp-lpcg             Z                               f      A        E                adc1_lpcg_clk adc1_lpcg_ipg_clk            #   f        I   R      clock-controller@5acd0000            2fsl,imx8qxp-lpcg             Z                               i      A   A        E                5  can0_lpcg_pe_clk can0_lpcg_ipg_clk can0_lpcg_chi_clk               #   i        I   T      clock-controller@5a4a0000            2fsl,imx8qxp-lpcg             ZJ                               =      A        E             '  uart4_lpcg_baud_clk uart4_lpcg_ipg_clk             #   =      i2c@5a840000          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c           Z    @               X                            \       \           Sper ipg               d           +n6            #   d      	  disabled          clock-controller@5ac40000            2fsl,imx8qxp-lpcg             Z                               d      A        E                i2c4_lpcg_clk i2c4_lpcg_ipg_clk            #   d        I   \      clock-controller@5ace0000            2fsl,imx8qxp-lpcg             Z                               j      A   A        E                5  can1_lpcg_pe_clk can1_lpcg_ipg_clk can1_lpcg_chi_clk               #   j        I   W      clock-controller@5acf0000            2fsl,imx8qxp-lpcg             Z                               k      A   A        E                5  can2_lpcg_pe_clk can2_lpcg_ipg_clk can2_lpcg_chi_clk               #   k        I   Z         clock-conn-axi           2fixed-clock                     CU        conn_axi_clk            I   ~      clock-conn-ahb           2fixed-clock                     	!        conn_ahb_clk            I         clock-conn-ipg           2fixed-clock                             conn_ipg_clk            I   }      bus@5b000000             2simple-bus                                   [       [         usb@5b0d0000          -   2fsl,imx7ulp-usb fsl,imx6ul-usb fsl,imx27-usb             [                                           ;   ]        F   ^                _           R            c           w              #          okay            ,default         :   `                                                   usbmisc@5b0d0200                     8   2fsl,imx7ulp-usbmisc fsl,imx7d-usbmisc fsl,imx6q-usbmisc          [            I   ^      usbphy@5b100000          2fsl,imx7ulp-usbphy           [                 _              #          okay               a        I   ]      mmc@5b010000                               [                 b      b      b            Sipg ahb per            #           okay          3   2fsl,imx8qm-usdhc fsl,imx8qxp-usdhc fsl,imx7d-usdhc             c           "  ,default state_100mhz state_200mhz           :   d           e           f                          mmc@5b020000                               [                 g      g      g            Sipg ahb per            #           (           =           okay          3   2fsl,imx8qm-usdhc fsl,imx8qxp-usdhc fsl,imx7d-usdhc             c           (  ,default state_100mhz state_200mhz sleep         :   h   i           j   i           k   i        M   l   m                   W   n   	            `        i   o      mmc@5b030000                               [                 p      p      p            Sipg ahb per            #           okay          3   2fsl,imx8qm-usdhc fsl,imx8qxp-usdhc fsl,imx7d-usdhc             c           "  ,default state_100mhz state_200mhz           :   q   r           s   r           t   r                   W   K               `        i   u      ethernet@5b040000            [           0                                                    v      v      v      v            Sipg ahb enet_clk_ref ptp                                      +沀sY@        u                         #           okay             2fsl,imx8qm-fec fsl,imx6sx-fec              c             ,default sleep           :   w           x                    y        rgmii-rxid     mdio                                 ethernet-phy@7           2ethernet-phy-ieee802.3-c22                           H                                                           H              I   y            ethernet@5b050000            [           0                                                   z      z      z      z            Sipg ahb enet_clk_ref ptp                                      +沀sY@        u                         #         	  disabled             2fsl,imx8qm-fec fsl,imx6sx-fec              c           usb@5b110000             2fsl,imx8qm-usb3          [                                             (      {      {       {      {      {           Slpm bus aclk ipg core                           +沀           #        	  disabled       usb@5b120000          
   2cdns,usb3            [     [     [             otg xhci dev                       0                                              host peripheral otg wakeup          
   |        cdns3,usb3-phy                   	  disabled             usb-phy@5b160000             2nxp,salvo-phy            [                 {           Ssalvo_phy_clk              #          0          	  disabled            I   |      clock-controller@5b200000            2fsl,imx8qxp-lpcg             [                                      }   ~        E                9  sdhc0_lpcg_per_clk sdhc0_lpcg_ipg_clk sdhc0_lpcg_ahb_clk               #           I   b      clock-controller@5b210000            2fsl,imx8qxp-lpcg             [!                                     }   ~        E                9  sdhc1_lpcg_per_clk sdhc1_lpcg_ipg_clk sdhc1_lpcg_ahb_clk               #           I   g      clock-controller@5b220000            2fsl,imx8qxp-lpcg             ["                                     }   ~        E                9  sdhc2_lpcg_per_clk sdhc2_lpcg_ipg_clk sdhc2_lpcg_ahb_clk               #           I   p      clock-controller@5b230000            2fsl,imx8qxp-lpcg             [#                      0                        ~            }   }        E                           enet0_lpcg_timer_clk enet0_lpcg_txc_sampling_clk enet0_lpcg_ahb_clk enet0_lpcg_rgmii_txc_clk enet0_lpcg_ipg_clk enet0_lpcg_ipg_s_clk               #           I   v      clock-controller@5b240000            2fsl,imx8qxp-lpcg             [$                      0                        ~            }   }        E                           enet1_lpcg_timer_clk enet1_lpcg_txc_sampling_clk enet1_lpcg_ahb_clk enet1_lpcg_rgmii_txc_clk enet1_lpcg_ipg_clk enet1_lpcg_ipg_s_clk               #           I   z      clock-controller@5b270000            2fsl,imx8qxp-lpcg             ['                               }        E            "  usboh3_ahb_clk usboh3_phy_ipg_clk              #          I   _      clock-controller@5b280000            2fsl,imx8qxp-lpcg             [(                        E                         0                      }   }   }              M  usb3_app_clk usb3_lpm_clk usb3_ipg_clk usb3_core_pclk usb3_phy_clk usb3_aclk               #          I   {         clock-lsio-bus           2fixed-clock                              lsio_bus_clk            I         bus@5d000000             2simple-bus                                    ]       ]                      pwm@5d000000             2fsl,imx27-pwm            ]              Sipg per                                               +n6         w                  ^           okay            ,default         :         pwm@5d010000             2fsl,imx27-pwm            ]             Sipg per                                               +n6         w                  _           okay            ,default         :         pwm@5d020000             2fsl,imx27-pwm            ]             Sipg per                                               +n6         w                  `           okay            ,default         :         pwm@5d030000             2fsl,imx27-pwm            ]             Sipg per                                               +n6         w                  a           okay            ,default         :         gpio@5d080000            ]                                ;        K                                  #            2fsl,imx8qm-gpio fsl,imx35-gpio        0  W                                   $           cMXM3_279 MXM3_277 MXM3_135 MXM3_203 MXM3_201 MXM3_275 MXM3_110 MXM3_120 MXM3_1/GPIO1 MXM3_3/GPIO2 MXM3_124 MXM3_122 MXM3_5/GPIO3 MXM3_7/GPIO4   MXM3_4 MXM3_211 MXM3_209 MXM3_2 MXM3_136 MXM3_134 MXM3_6 MXM3_8 MXM3_112 MXM3_118 MXM3_114 MXM3_116         I   G      gpio@5d090000            ]	                                ;        K                                  #            2fsl,imx8qm-gpio fsl,imx35-gpio        @  W          (            2            ?            H         }  c    MXM3_286  MXM3_87 MXM3_99 MXM3_138 MXM3_140 MXM3_239  MXM3_281 MXM3_283 MXM3_126 MXM3_132     MXM3_173 MXM3_175 MXM3_123            I   H   hdmi-ctrl-hog           ,default         :            s        b               |CONNECTOR_IS_HDMI                     gpio@5d0a0000            ]
                                ;        K                                  #            2fsl,imx8qm-gpio fsl,imx35-gpio        0  W          P            U            h   
        c       MXM3_198 MXM3_35 MXM3_164     MXM3_217 MXM3_215   MXM3_193 MXM3_194 MXM3_37  MXM3_271 MXM3_273 MXM3_195 MXM3_197 MXM3_177 MXM3_179 MXM3_181 MXM3_183 MXM3_185 MXM3_187           I   n   pcie-wifi-hog           ,default         :            s        b               |PCIE_WIFI_CLK                     gpio@5d0b0000            ]                                ;        K                                  #            2fsl,imx8qm-gpio fsl,imx35-gpio          W          r            u                                                                                                                                   cMXM3_191  MXM3_221 MXM3_225 MXM3_223 MXM3_227 MXM3_200 MXM3_235 MXM3_231 MXM3_229 MXM3_233 MXM3_204 MXM3_196  MXM3_202    MXM3_305 MXM3_307 MXM3_309 MXM3_311 MXM3_315 MXM3_317 MXM3_319 MXM3_321 MXM3_15/GPIO7 MXM3_63 MXM3_17/GPIO8 MXM3_12 MXM3_14 MXM3_16           I   2      gpio@5d0c0000            ]                                ;        K                                  #            2fsl,imx8qm-gpio fsl,imx35-gpio        `  W                                                                                 cMXM3_18 MXM3_11/GPIO5 MXM3_13/GPIO6 MXM3_274 MXM3_84 MXM3_262 MXM3_96      MXM3_190    MXM3_269 MXM3_251 MXM3_253 MXM3_295 MXM3_299 MXM3_301 MXM3_297 MXM3_293 MXM3_291 MXM3_289 MXM3_287           I   K   pcie-sata-hog           ,default         :            s        b               |PCIE_SATA_CLK                     gpio@5d0d0000            ]                                ;        K                                  #            2fsl,imx8qm-gpio fsl,imx35-gpio          W                                                                                                         c              MXM3_150 MXM3_160 MXM3_162 MXM3_144 MXM3_146 MXM3_148 MXM3_152 MXM3_156 MXM3_158 MXM3_159 MXM3_184 MXM3_180 MXM3_186 MXM3_188 MXM3_176 MXM3_178           I         gpio@5d0e0000            ]                                ;        K                                  #            2fsl,imx8qm-gpio fsl,imx35-gpio           W             
      
            v  c          MXM3_261 MXM3_263 MXM3_259 MXM3_257 MXM3_255 MXM3_128 MXM3_130 MXM3_265 MXM3_249 MXM3_247 MXM3_245 MXM3_243         gpio@5d0f0000            ]                                ;        K                                  #            2fsl,imx8qm-gpio fsl,imx35-gpio        spi@5d120000                                       2nxp,imx8qxp-fspi             ]                   fspi_base fspi_mmap                \                                      Sfspi_en fspi               #         	  disabled          mailbox@5d1b0000             ]                                        	  disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d1c0000             ]                                        ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu         I         mailbox@5d1d0000             ]                                        	  disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d1e0000             ]                                        	  disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d1f0000             ]                                        	  disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d200000             ]                                              #         	  disabled             2fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d210000             ]!                                             #         	  disabled             2fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d280000             ](                                             #            2fsl,imx8qm-mu fsl,imx6sx-mu       clock-controller@5d400000            2fsl,imx8qxp-lpcg             ]@                      4                                                  E                      h  pwm0_lpcg_ipg_clk pwm0_lpcg_ipg_hf_clk pwm0_lpcg_ipg_s_clk pwm0_lpcg_ipg_slv_clk pwm0_lpcg_ipg_mstr_clk            #           I         clock-controller@5d410000            2fsl,imx8qxp-lpcg             ]A                      4                                                  E                      h  pwm1_lpcg_ipg_clk pwm1_lpcg_ipg_hf_clk pwm1_lpcg_ipg_s_clk pwm1_lpcg_ipg_slv_clk pwm1_lpcg_ipg_mstr_clk            #           I         clock-controller@5d420000            2fsl,imx8qxp-lpcg             ]B                      4                                                  E                      h  pwm2_lpcg_ipg_clk pwm2_lpcg_ipg_hf_clk pwm2_lpcg_ipg_s_clk pwm2_lpcg_ipg_slv_clk pwm2_lpcg_ipg_mstr_clk            #           I         clock-controller@5d430000            2fsl,imx8qxp-lpcg             ]C                      4                                                  E                      h  pwm3_lpcg_ipg_clk pwm3_lpcg_ipg_hf_clk pwm3_lpcg_ipg_s_clk pwm3_lpcg_ipg_slv_clk pwm3_lpcg_ipg_mstr_clk            #           I         clock-controller@5d440000            2fsl,imx8qxp-lpcg             ]D                      4                                                  E                      h  pwm4_lpcg_ipg_clk pwm4_lpcg_ipg_hf_clk pwm4_lpcg_ipg_s_clk pwm4_lpcg_ipg_slv_clk pwm4_lpcg_ipg_mstr_clk            #         clock-controller@5d450000            2fsl,imx8qxp-lpcg             ]E                      4                                                  E                      h  pwm5_lpcg_ipg_clk pwm5_lpcg_ipg_hf_clk pwm5_lpcg_ipg_s_clk pwm5_lpcg_ipg_slv_clk pwm5_lpcg_ipg_mstr_clk            #         clock-controller@5d460000            2fsl,imx8qxp-lpcg             ]F                      4                                                  E                      h  pwm6_lpcg_ipg_clk pwm6_lpcg_ipg_hf_clk pwm6_lpcg_ipg_s_clk pwm6_lpcg_ipg_slv_clk pwm6_lpcg_ipg_mstr_clk            #         clock-controller@5d470000            2fsl,imx8qxp-lpcg             ]G                      4                                                  E                      h  pwm7_lpcg_ipg_clk pwm7_lpcg_ipg_hf_clk pwm7_lpcg_ipg_s_clk pwm7_lpcg_ipg_slv_clk pwm7_lpcg_ipg_mstr_clk            #            chosen          /bus@5a000000/serial@5a070000         backlight            2pwm-backlight           ,default         :                   -   ?   X   w                               H             	  disabled          gpio-fan          	   2gpio-fan            ,default         :           b   2                                  regulator-ext-rgmii          2regulator-fixed            #           2Z         2Z        VDD_EXT_RGMII (LDO1)       regulator-state-mem          (         regulator-module-3v3             2regulator-fixed          2Z         2Z        +V3.3         regulator-module-3v3-avdd            2regulator-fixed          2Z         2Z        +V3.3_AUDIO       regulator-module-wifi            2regulator-fixed         ,default         :           A   H                F         Y        wifi_pwrdn_fake_regulator           m   d      regulator-pcie-switch            2regulator-fixed         ,default         :           A   2                F         w@         w@        pcie_switch                regulator-usb-host-vbus          2regulator-fixed         ,default         :           A   K                F         Y         LK@         LK@        VCC USBH2(ABCD) / USBH(3|4)       regulator-usb-hsic           2regulator-fixed          -         -        usb-hsic-dummy        regulator-usb-hsic1          2regulator-fixed          -         -        usb-phy-dummy           I   a      reserved-memory                                      decoder-boot@84000000                                           I   %      encoder1-boot@86000000                                           I   (      encoder2-boot@86200000                                           I   +      m4@88000000                                       rpmsg@90200000                                         vdevbuffer@90400000          2shared-dma-pool              @                        decoder-rpc@92000000                                             I   &      dsp@92400000                 @                        encoder1-rpc@94400000                @       p                   I   )      encoder2-rpc@94b00000                       p                   I   ,      linux,cma            2shared-dma-pool                    <                                  <            touchscreen          2toradex,vf50-touchscreen                 2                      ,idle default            :                 S                                                           n                 n                  n                 n             	  disabled          regulator-3v3-mmc            2regulator-fixed         ,default         :            F        A                            2Z         2Z      	  3.3V_MMC              '        I   o      regulator-3v3-sd             2regulator-fixed         ,default         :            F        A                            2Z         2Z        3.3V_SD           '        I   u      regulator-can1           2regulator-fixed         ,default         :            F        A                  5V_SW_CAN1            '        I   V      regulator-can2           2regulator-fixed         ,default         :            F        A                  5V_SW_CAN2            '        I   Y         	interrupt-parent #address-cells #size-cells model compatible mmc0 mmc1 mmc2 serial0 serial1 serial2 serial3 vpu-core0 vpu-core1 vpu-core2 rtc0 rtc1 cpu device_type reg clocks enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache operating-points-v2 #cooling-cells phandle cache-level cache-unified opp-shared opp-hz opp-microvolt clock-latency-ns opp-suspend #interrupt-cells interrupt-controller interrupts #global-interrupts #iommu-cells mbox-names mboxes #power-domain-cells #clock-cells pinctrl-names pinctrl-0 fsl,pins #thermal-sensor-cells polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device ranges power-domains status #mbox-cells memory-region clock-frequency clock-output-names assigned-clocks assigned-clock-rates slot clock-indices clock-names cs-gpios dma-names dmas #pwm-cells #dma-cells dma-channels dma-channel-mask connect-gpios initial-mode intn-gpios refclk-frequency reset-gpios shunt-resistor #io-channel-cells fsl,clk-source fsl,scu-index xceiver-supply fsl,usbphy fsl,usbmisc ahb-burst-config tx-burst-size-dword rx-burst-size-dword adp-disable hnp-disable over-current-active-low power-active-high srp-disable #index-cells phy-3p0-supply iommus pinctrl-1 pinctrl-2 bus-width non-removable fsl,tuning-start-tap fsl,tuning-step pinctrl-3 cd-gpios no-1-8-v vmmc-supply fsl,num-tx-queues fsl,num-rx-queues fsl,magic-packet phy-handle phy-mode micrel,led-mode reset-assert-us reset-deassert-us reg-names interrupt-names phys phy-names cdns,on-chip-buff-size #phy-cells gpio-controller #gpio-cells gpio-ranges gpio-line-names gpio-hog line-name output-high stdout-path brightness-levels default-brightness-level enable-gpios gpio-fan,speed-map regulator-max-microvolt regulator-min-microvolt regulator-name regulator-off-in-suspend gpio enable-active-high regulator-always-on regulator-settling-time-us startup-delay-us no-map alloc-ranges linux,cma-default reusable io-channels vf50-ts-min-pressure xp-gpios xm-gpios yp-gpios ym-gpios off-on-delay-us 