  g   8  c   (              b                                                                      ,Freescale i.MX8QXP MEK           2fsl,imx8qxp-mek fsl,imx8qxp    aliases           =/bus@5b000000/ethernet@5b040000           G/bus@5b000000/ethernet@5b050000          Q/bus@5d000000/gpio@5d080000          W/bus@5d000000/gpio@5d090000          ]/bus@5d000000/gpio@5d0a0000          c/bus@5d000000/gpio@5d0b0000          i/bus@5d000000/gpio@5d0c0000          o/bus@5d000000/gpio@5d0d0000          u/bus@5d000000/gpio@5d0e0000          {/bus@5d000000/gpio@5d0f0000          /bus@5a000000/i2c@5a800000           /bus@5a000000/i2c@5a810000           /bus@5a000000/i2c@5a820000           /bus@5a000000/i2c@5a830000           /bus@5b000000/mmc@5b010000           /bus@5b000000/mmc@5b020000           /bus@5b000000/mmc@5b030000           /bus@5d000000/mailbox@5d1b0000           /bus@5d000000/mailbox@5d1c0000           /bus@5d000000/mailbox@5d1d0000           /bus@5d000000/mailbox@5d1e0000           /bus@5d000000/mailbox@5d1f0000           /bus@5a000000/serial@5a060000            /bus@5a000000/serial@5a070000            /bus@5a000000/serial@5a080000            /bus@5a000000/serial@5a090000             /vpu@2c000000/vpu-core@2d080000           /vpu@2c000000/vpu-core@2d090000           /vpu@2c000000/vpu-core@2d0a0000       cpus                                 cpu@0            cpu          2arm,cortex-a35                          psci                       !   @        3           @           M   @        _           l           }                                         
      cpu@1            cpu          2arm,cortex-a35                         psci                       !   @        3           @           M   @        _           l           }                                               cpu@2            cpu          2arm,cortex-a35                         psci                       !   @        3           @           M   @        _           l           }                                               cpu@3            cpu          2arm,cortex-a35                         psci                       !   @        3           @           M   @        _           l           }                                               l2-cache0            2cache                                 #   @        5                       opp-table            2operating-points-v2                        opp-900000000               5          B@         I      opp-1200000000              G                   I                  interrupt-controller@51a00000            2arm,gic-v3               Q             Q                             	              	                    reserved-memory                                   )   decoder-boot@84000000                                  0                 encoder-boot@86000000                                   0                 decoder-rpc@92000000                                   0                 dsp@92400000                @                  0                 encoder-rpc@94400000                @       p           0                    pmu          2arm,cortex-a35-pmu                         psci             2arm,psci-1.0            smc       scu          2fsl,imx-scu         7tx0 rx0 gip3          $  B                                 imx8qx-pd            2fsl,imx8qxp-scu-pd fsl,scu-pd           I                    clock-controller             2fsl,imx8qxp-clk         ]           }              jxtal_32KHz xtal_24Mhz                    pinctrl          2fsl,imx8qxp-iomuxc     fec1grp         v   5          4          &          %          '          (          )          *          ,          -          .          /          0          1                  5      ioexprstgrp         v   Z     !           (      isl29023grp         v   [      !           *      lpi2c1grp           v         !         !           '      lpuart0grp          v   o          p                         usdhc1grp           v   	      A   
       !          !          !          !          !          !          !          !          !          A           .      usdhc2grp         T  v         A          !           !   !       !   "       !   #       !          !           0         imx8qx-ocotp             2fsl,imx8qxp-scu-ocotp                                  scu-key       "   2fsl,imx8qxp-sc-key fsl,imx-sc-key              t        okay          rtc          2fsl,imx8qxp-sc-rtc        watchdog          "   2fsl,imx8qxp-sc-wdt fsl,imx-sc-wdt              <      thermal-sensor        *   2fsl,imx8qxp-sc-thermal fsl,imx-sc-thermal                                  timer            2arm,armv8-timer       0                                   
         clock-xtal32k            2fixed-clock         ]                       xtal_32KHz                   clock-xtal24m            2fixed-clock         ]            n6         xtal_24MHz                   thermal-zones      cpu-thermal0                                      c   trips      trip0                               passive            	      trip1                            	   critical             cooling-maps       map0            %   	      0  *   
                     pmic-thermal0                                        trips      trip0                               passive                  trip1            H                	   critical             cooling-maps       map0            %         0  *   
                        bus@58000000             2simple-bus                                   )X       X         clock-img-ipg            2fixed-clock         ]                     img_ipg_clk                  jpegdec@58400000            X@           0        5         6         7         8           }                     jper ipg         9                     I        (  ^                                  2nxp,imx8qxp-jpgdec        jpegenc@58450000            XE           0        1         2         3         4           }                     jper ipg         9                     I        (  ^                                  2nxp,imx8qxp-jpgenc        clock-controller@585d0000            2fsl,imx8qxp-lpcg            X]             ]           }              l             0  img_jpeg_dec_lpcg_clk img_jpeg_dec_lpcg_ipg_clk         ^                      clock-controller@585f0000            2fsl,imx8qxp-lpcg            X_             ]           }              l             0  img_jpeg_enc_lpcg_clk img_jpeg_enc_lpcg_ipg_clk         ^                         vpu@2c000000                                     ),       ,                  ,                  ^             okay             2nxp,imx8qxp-vpu    mailbox@2d000000             2fsl,imx6sx-mu           -                               z           ^             okay                     mailbox@2d020000             2fsl,imx6sx-mu           -                              z           ^             okay                     mailbox@2d040000             2fsl,imx6sx-mu           -                              z           ^           	  disabled                     vpu-core@2d080000           -              2nxp,imx8q-vpu-decoder           ^             7tx0 tx1 rx        $  B                                       okay                        vpu-core@2d090000           -              2nxp,imx8q-vpu-encoder           ^             7tx0 tx1 rx        $  B                                       okay                        vpu-core@2d0a0000           -
              2nxp,imx8q-vpu-encoder           ^             7tx0 tx1 rx        $  B                                     	  disabled             bus@59000000             2simple-bus                                   )Y       Y         clock-audio-ipg          2fixed-clock         ]            '         audio_ipg_clk                    clock-controller@59580000            2fsl,imx8qxp-lpcg            YX             ]           }                 l               4  dsp_lpcg_adb_clk dsp_lpcg_ipg_clk dsp_lpcg_core_clk         ^                       clock-controller@59590000            2fsl,imx8qxp-lpcg            YY             ]           }           l           dsp_ram_lpcg_ipg_clk            ^                      dsp@596e8000             2fsl,imx8qxp-dsp         Yn           }                          jipg ocram core           ^                               7txdb0 txdb1 rxdb0 rxdb1       0  B                                                         okay             bus@5a000000             2simple-bus                                   )Z       Z         clock-dma-ipg            2fixed-clock         ]            '         dma_ipg_clk            $      serial@5a060000         Z                               }                   	  jipg baud            ^      9        okay             2fsl,imx8qxp-lpuart          default                   serial@5a070000         Z                               }   !      !          	  jipg baud            ^      :      	  disabled             2fsl,imx8qxp-lpuart        serial@5a080000         Z                               }   "      "          	  jipg baud            ^      ;      	  disabled             2fsl,imx8qxp-lpuart        serial@5a090000         Z	                               }   #      #          	  jipg baud            ^      <      	  disabled             2fsl,imx8qxp-lpuart        clock-controller@5a460000            2fsl,imx8qxp-lpcg            ZF             ]           }      9      $        l             '  uart0_lpcg_baud_clk uart0_lpcg_ipg_clk          ^      9                 clock-controller@5a470000            2fsl,imx8qxp-lpcg            ZG             ]           }      :      $        l             '  uart1_lpcg_baud_clk uart1_lpcg_ipg_clk          ^      :           !      clock-controller@5a480000            2fsl,imx8qxp-lpcg            ZH             ]           }      ;      $        l             '  uart2_lpcg_baud_clk uart2_lpcg_ipg_clk          ^      ;           "      clock-controller@5a490000            2fsl,imx8qxp-lpcg            ZI             ]           }      <      $        l             '  uart3_lpcg_baud_clk uart3_lpcg_ipg_clk          ^      <           #      i2c@5a800000            Z    @                           }   %            jper         9      `           In6         ^      `      	  disabled          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c       i2c@5a810000            Z    @                           }   &            jper         9      a           In6         ^      a        okay          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c                                            default            '   (   i2c-switch@71            2nxp,pca9646 nxp,pca9546                                      q           )         i2c@0                                            gpio@68          2maxim,max7322              h                             i2c@1                                              i2c@2                                           pressure-sensor@60           2fsl,mpl3115            `         i2c@3                                           gpio@1a          2nxp,pca9557                                      gpio@1d          2nxp,pca9557                                      light-sensor@44         default            *         2isil,isl29023              D             )                             i2c@5a820000            Z    @                           }   +            jper         9      b           In6         ^      b      	  disabled          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c       i2c@5a830000            Z    @                           }   ,            jper         9      c           In6         ^      c      	  disabled          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c       clock-controller@5ac00000            2fsl,imx8qxp-lpcg            Z             ]           }      `      $        l                i2c0_lpcg_clk i2c0_lpcg_ipg_clk         ^      `           %      clock-controller@5ac10000            2fsl,imx8qxp-lpcg            Z             ]           }      a      $        l                i2c1_lpcg_clk i2c1_lpcg_ipg_clk         ^      a           &      clock-controller@5ac20000            2fsl,imx8qxp-lpcg            Z             ]           }      b      $        l                i2c2_lpcg_clk i2c2_lpcg_ipg_clk         ^      b           +      clock-controller@5ac30000            2fsl,imx8qxp-lpcg            Z             ]           }      c      $        l                i2c3_lpcg_clk i2c3_lpcg_ipg_clk         ^      c           ,         bus@5b000000             2simple-bus                                   )[       [         clock-conn-axi           2fixed-clock         ]            CU        conn_axi_clk               9      clock-conn-ahb           2fixed-clock         ]            	!        conn_ahb_clk          clock-conn-ipg           2fixed-clock         ]                    conn_ipg_clk               8      mmc@5b010000                              [             }   -      -      -            jipg per ahb         ^              okay          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc           9                 I         default            .                                            mmc@5b020000                              [             }   /      /      /            jipg per ahb         ^                                    okay          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc           9                 I         default            0                      1        +   2              4   2             mmc@5b030000                              [             }   3      3      3            jipg per ahb         ^            	  disabled          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc         ethernet@5b040000           [           0                                                }   4      4      4      4            jipg ahb enet_clk_ref ptp            9                          I沀sY@        =           O           ^              okay          .   2fsl,imx8qxp-fec fsl,imx8qm-fec fsl,imx6sx-fec           default            5      	  argmii-id            j   6         u   mdio                                 ethernet-phy@0           2ethernet-phy-ieee802.3-c22                         6            ethernet@5b050000           [           0                                               }   7      7      7      7            jipg ahb enet_clk_ref ptp            9                          I沀sY@        =           O           ^            	  disabled          .   2fsl,imx8qxp-fec fsl,imx8qm-fec fsl,imx6sx-fec         clock-controller@5b200000            2fsl,imx8qxp-lpcg            [              ]           }            8   9        l                9  sdhc0_lpcg_per_clk sdhc0_lpcg_ipg_clk sdhc0_lpcg_ahb_clk            ^                 -      clock-controller@5b210000            2fsl,imx8qxp-lpcg            [!             ]           }            8   9        l                9  sdhc1_lpcg_per_clk sdhc1_lpcg_ipg_clk sdhc1_lpcg_ahb_clk            ^                 /      clock-controller@5b220000            2fsl,imx8qxp-lpcg            ["             ]           }            8   9        l                9  sdhc2_lpcg_per_clk sdhc2_lpcg_ipg_clk sdhc2_lpcg_ahb_clk            ^                 3      clock-controller@5b230000            2fsl,imx8qxp-lpcg            [#             ]         0  }                     9            8   8        l                           enet0_lpcg_timer_clk enet0_lpcg_txc_sampling_clk enet0_lpcg_ahb_clk enet0_lpcg_rgmii_txc_clk enet0_lpcg_ipg_clk enet0_lpcg_ipg_s_clk            ^                 4      clock-controller@5b240000            2fsl,imx8qxp-lpcg            [$             ]         0  }                     9            8   8        l                           enet1_lpcg_timer_clk enet1_lpcg_txc_sampling_clk enet1_lpcg_ahb_clk enet1_lpcg_rgmii_txc_clk enet1_lpcg_ipg_clk enet1_lpcg_ipg_s_clk            ^                 7         bus@5c000000             2simple-bus                                   )\       \         ddr-pmu@5c020000             2fsl,imx8-ddr-pmu            \                                bus@5d000000             2simple-bus                                   )]       ]         clock-lsio-mem           2fixed-clock         ]                     lsio_mem_clk          clock-lsio-bus           2fixed-clock         ]                     lsio_bus_clk               :      gpio@5d080000           ]                                                    	                   ^                2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d090000           ]	                                                    	                   ^                2fsl,imx8qxp-gpio fsl,imx35-gpio            )      gpio@5d0a0000           ]
                                                    	                   ^                2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0b0000           ]                                                    	                   ^                2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0c0000           ]                                                    	                   ^                2fsl,imx8qxp-gpio fsl,imx35-gpio            2      gpio@5d0d0000           ]                                                    	                   ^                2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0e0000           ]                                                    	                   ^                2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0f0000           ]                                                    	                   ^                2fsl,imx8qxp-gpio fsl,imx35-gpio       mailbox@5d1b0000            ]                               z         	  disabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1c0000            ]                               z         -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu                     mailbox@5d1d0000            ]                               z         	  disabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1e0000            ]                               z         	  disabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1f0000            ]                               z         	  disabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d200000            ]                                z           ^            	  disabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d210000            ]!                               z           ^            	  disabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d280000            ](                               z           ^               2fsl,imx8qxp-mu fsl,imx6sx-mu                     clock-controller@5d400000            2fsl,imx8qxp-lpcg            ]@             ]         4  }                              :                 l                      h  pwm0_lpcg_ipg_clk pwm0_lpcg_ipg_hf_clk pwm0_lpcg_ipg_s_clk pwm0_lpcg_ipg_slv_clk pwm0_lpcg_ipg_mstr_clk         ^            clock-controller@5d410000            2fsl,imx8qxp-lpcg            ]A             ]         4  }                              :                 l                      h  pwm1_lpcg_ipg_clk pwm1_lpcg_ipg_hf_clk pwm1_lpcg_ipg_s_clk pwm1_lpcg_ipg_slv_clk pwm1_lpcg_ipg_mstr_clk         ^            clock-controller@5d420000            2fsl,imx8qxp-lpcg            ]B             ]         4  }                              :                 l                      h  pwm2_lpcg_ipg_clk pwm2_lpcg_ipg_hf_clk pwm2_lpcg_ipg_s_clk pwm2_lpcg_ipg_slv_clk pwm2_lpcg_ipg_mstr_clk         ^            clock-controller@5d430000            2fsl,imx8qxp-lpcg            ]C             ]         4  }                              :                 l                      h  pwm3_lpcg_ipg_clk pwm3_lpcg_ipg_hf_clk pwm3_lpcg_ipg_s_clk pwm3_lpcg_ipg_slv_clk pwm3_lpcg_ipg_mstr_clk         ^            clock-controller@5d440000            2fsl,imx8qxp-lpcg            ]D             ]         4  }                              :                 l                      h  pwm4_lpcg_ipg_clk pwm4_lpcg_ipg_hf_clk pwm4_lpcg_ipg_s_clk pwm4_lpcg_ipg_slv_clk pwm4_lpcg_ipg_mstr_clk         ^            clock-controller@5d450000            2fsl,imx8qxp-lpcg            ]E             ]         4  }                              :                 l                      h  pwm5_lpcg_ipg_clk pwm5_lpcg_ipg_hf_clk pwm5_lpcg_ipg_s_clk pwm5_lpcg_ipg_slv_clk pwm5_lpcg_ipg_mstr_clk         ^            clock-controller@5d460000            2fsl,imx8qxp-lpcg            ]F             ]         4  }                              :                 l                      h  pwm6_lpcg_ipg_clk pwm6_lpcg_ipg_hf_clk pwm6_lpcg_ipg_s_clk pwm6_lpcg_ipg_slv_clk pwm6_lpcg_ipg_mstr_clk         ^            clock-controller@5d470000            2fsl,imx8qxp-lpcg            ]G             ]         4  }                              :                 l                      h  pwm7_lpcg_ipg_clk pwm7_lpcg_ipg_hf_clk pwm7_lpcg_ipg_s_clk pwm7_lpcg_ipg_slv_clk pwm7_lpcg_ipg_mstr_clk         ^               chosen          /bus@5a000000/serial@5a060000         memory@80000000          memory                     @         usdhc2-vmmc          2regulator-fixed       	  SD1_SPWR             -         -           2                           1         	interrupt-parent #address-cells #size-cells model compatible ethernet0 ethernet1 gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 i2c0 i2c1 i2c2 i2c3 mmc0 mmc1 mmc2 mu0 mu1 mu2 mu3 mu4 serial0 serial1 serial2 serial3 vpu_core0 vpu_core1 vpu_core2 device_type reg enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache clocks operating-points-v2 #cooling-cells phandle cache-level opp-shared opp-hz opp-microvolt clock-latency-ns opp-suspend #interrupt-cells interrupt-controller interrupts ranges no-map mbox-names mboxes #power-domain-cells #clock-cells clock-names fsl,pins linux,keycodes status timeout-sec #thermal-sensor-cells clock-frequency clock-output-names polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device assigned-clocks assigned-clock-rates power-domains clock-indices #mbox-cells memory-region pinctrl-names pinctrl-0 reset-gpios gpio-controller #gpio-cells bus-width no-sd no-sdio non-removable fsl,tuning-start-tap fsl,tuning-step vmmc-supply cd-gpios wp-gpios fsl,num-tx-queues fsl,num-rx-queues phy-mode phy-handle fsl,magic-packet stdout-path regulator-name regulator-min-microvolt regulator-max-microvolt gpio enable-active-high 