<87(d7xsolidrun,cuboxmarvell,dove&SolidRun CuBox,aliases9=/mbus/internal-regs/power-management@d0000/gpio-ctrl@4009C/mbus/internal-regs/power-management@d0000/gpio-ctrl@420$I/mbus/internal-regs/gpio-ctrl@e8400cpuscpu@0marvell,pj4amarvell,sheeva-v7Ocpu[ll2-cachemarvell,tauros2-cachepgpu-subsystemmarvell,dove-gpu-subsystemokayi2c-muxi2c-mux-pinctrli2c0i2c1i2c2i2c@0lokayclock-generator@60silabs,si5351a-msopl`xtal clkout@0l3L`clkout@2l3L`i2c@1l disabledi2c@2l disabledmbus*marvell,dove-mbusmarvell,mbussimple-busr } P pciemarvell,dove-pcie disabledOpci  pcie@1Opci disabled l @ intxerror `     interrupt-controller. pcie@2Opci disabled l @ intxerror `     interrupt-controller. internal-regs simple-bus@ spi@10600marvell,orion-spiCl( defaultokayflash@0 st,w25q32N1-li2c@11000marvell,mv64xxx-i2cl   okayserial@12000 ns16550al ` okayserial@12100 ns16550al!` default disabledserial@12200 ns16550al"`   disabledserial@12300 ns16550al#`   disabledspi@14600marvell,orion-spiClF(  disabledmbus-ctrl@20000marvell,mbus-controllerl system-ctrl@20000 marvell,orion-system-controllerlbridge-interrupt-ctrl@20110marvell,orion-bridge-intc.ljinterrupt-controller@20200marvell,orion-intc.ltimer@20300marvell,orion-timerl , watchdog@20300marvell,orion-wdtl(, crypto-engine@30000marvell,dove-cryptol~regs okayusb-host@50000marvell,orion-ehcil okayusb-host@51000marvell,orion-ehcil okaydma-engine@60800marvell,orion-xorl  okaychannel0'channel1(dma-engine@60900marvell,orion-xorl   okaychannel0*channel1+sdio-host@90000marvell,dove-sdhcil $& default disabledethernet-ctrl@72000marvell,orion-ethl @ @okayethernet-port@0marvell,orion-eth-portlmdio-bus@72004marvell,orion-mdiol  okayethernet-phy@1marvell,88e1310lsdio-host@92000marvell,dove-sdhcil #% defaultokaysata-host@a0000marvell,orion-satal $>  port0okaysata-phy@a2000marvell,mvebu-sata-phyl 4 sataokayaudio-controller@b0000marvell,dove-audiol "  internal disabledaudio-controller@b4000marvell,dove-audiol @" internalextclkokaydefaultpower-management@d0000marvell,dove-pmusimple-busl  !.)domainsvpu-domain6J_tgpu-domain6J_tthermal-diode@1cmarvell,dove-thermall \clock-gating-ctrl@38marvell,dove-gating-clockl8  core-clock@64marvell,dove-divider-clockldpin-ctrl@200marvell,dove-pinctrll@ pmx-gpio-0{mpp0gpiopmx-gpio-1{mpp1gpiopmx-gpio-2{mpp2gpiopmx-gpio-3{mpp3gpiopmx-gpio-4{mpp4gpiopmx-gpio-5{mpp5gpiopmx-gpio-6{mpp6gpiopmx-gpio-7{mpp7gpiopmx-gpio-8{mpp8gpiopmx-gpio-9{mpp9gpiopmx-pcie1-clkreq{mpp9pex1pmx-gpio-10{mpp10gpiopmx-gpio-11{mpp11gpiopmx-pcie0-clkreq{mpp11pex0pmx-gpio-12{mpp12gpiopmx-gpio-13{mpp13gpiopmx-audio1-extclk{mpp13audio1pmx-gpio-14{mpp14gpiopmx-gpio-15{mpp15gpiopmx-gpio-16{mpp16gpiopmx-gpio-17{mpp17gpiopmx-gpio-18{mpp18gpiopmx-gpio-19{mpp19gpiopmx-gpio-20{mpp20gpiopmx-gpio-21{mpp21gpiopmx-camera {mpp_cameracamerapmx-camera-gpio {mpp_cameragpiopmx-sdio0 {mpp_sdio0sdio0pmx-sdio0-gpio {mpp_sdio0gpiopmx-sdio1 {mpp_sdio1sdio1pmx-sdio1-gpio {mpp_sdio1gpiopmx-audio1-gpio {mpp_audio1gpiopmx-audio1-i2s1-spdifo {mpp_audio1 i2s1/spdifopmx-spi0 {mpp_spi0spi0pmx-spi0-gpio {mpp_spi0gpiopmx-spi1-4-7{mpp4mpp5mpp6mpp7spi1pmx-spi1-20-23{mpp20mpp21mpp22mpp23spi1pmx-uart1 {mpp_uart1uart1pmx-uart1-gpio {mpp_uart1gpiopmx-nand {mpp_nandnandpmx-nand-gpo {mpp_nandgpopmx-i2c1 {mpp17mpp19twsipmx-i2c2 {mpp_audio1twsipmx-ssp-i2c2 {mpp_audio1 ssp/twsipmx-i2cmux-0{twsi twsi-opt1pmx-i2cmux-1{twsi twsi-opt2pmx-i2cmux-2{twsi twsi-opt3core-clocks@214marvell,dove-core-clockl gpio-ctrl@400marvell,orion-gpiol  ., <gpio-ctrl@420marvell,orion-gpiol  .,=real-time-clock@8500marvell,orion-rtcl global-config@e802c"marvell,dove-global-configsysconl,gpio-ctrl@e8400marvell,orion-gpiol lcd-controller@810000marvell,dove-lcdl. disabledlcd-controller@820000marvell,dove-lcdl/ disabledsram@ffffe000 mmio-sraml gpu@840000core vivante,gc0l@okaymemoryOmemoryl@chosen#console=ttyS0,115200n8 earlyprintkleds gpio-ledsdefaultled-powerPower keepregulator-1regulator-fixed USB PowerLK@LK@&9M _defaultclocksoscillator fixed-clock}x@ir-receivergpio-ir-receiver default #address-cells#size-cellscompatiblemodelinterrupt-parentgpio0gpio1gpio2device_typenext-level-cacheregmarvell,tauros2-cache-featuresphandlecoresstatusi2c-parentpinctrl-namespinctrl-0pinctrl-1pinctrl-2clock-frequency#clock-cellsclocksclock-namessilabs,pll-sourcesilabs,drive-strengthsilabs,multisynth-sourcesilabs,clock-sourcesilabs,pll-mastercontrollerpcie-mem-aperturepcie-io-aperturerangesmsi-parentbus-rangeassigned-addressesmarvell,pcie-port#interrupt-cellsinterrupt-namesinterruptsinterrupt-map-maskinterrupt-mapinterrupt-controllercell-indexspi-max-frequencyreg-shiftmarvell,#interruptsreg-namesmarvell,crypto-sramsmarvell,crypto-sram-sizedmacap,memcpydmacap,xormarvell,tx-checksum-limitlocal-mac-addressphy-handlephysphy-namesnr-ports#phy-cells#reset-cells#power-domain-cellsmarvell,pmu_pwr_maskmarvell,pmu_iso_maskresetsmarvell,pinsmarvell,function#gpio-cellsgpio-controllerngpiospower-domainsbootargslabeldefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highregulator-always-onregulator-boot-ongpio