Ðþí  Kä   8  F¨   (            <  Fp                                                         Altera SOCFPGA Arria 10       =   !altr,socfpga-arria10-socdk altr,socfpga-arria10 altr,socfpga       cpus                                       ,altr,socfpga-a10-smp       cpu@0            !arm,cortex-a9            :cpu          F             J            [         cpu@1            !arm,cortex-a9            :cpu          F            J            [            pmu@ff111000             !arm,cortex-a9-pmu            c            t       |          }                           Fÿ    ÿ0          interrupt-controller@ffffd000            !arm,cortex-a9-gic            ’             £         FÿÿÐ    ÿÿÁ             [         soc                                   !simple-bus           :soc          c             ¸   amba             !simple-bus                                     ¸   pdma@ffda1000            !arm,pl330 arm,primecell          FÿÚ          l   t       S          T          U          V          W          X          Y          Z          [            ¿            Ê         	   Ñapb_pclk             Ý      0      5         ädma dma-ocp          [   "         base_fpga_region                                      !fpga-region          ð         clkmgr@ffd04000          !altr,clk-mgr             FÿÐ@       clocks                               cb_intosc_hs_div2_clk            ù             !fixed-clock          [         cb_intosc_ls_clk             ù             !fixed-clock          [   	      f2s_free_clk             ù             !fixed-clock          [   
      osc1             ù             !fixed-clock         }x@         [         main_pll@40                                    ù             !altr,socfpga-a10-pll-clock           Ê      	   
         F   @         [      main_mpu_base_clk            ù             !altr,socfpga-a10-perip-clk           Ê             @                [         main_noc_base_clk            ù             !altr,socfpga-a10-perip-clk           Ê             D                [         main_emaca_clk@68            ù             !altr,socfpga-a10-perip-clk           Ê            F   h      main_emacb_clk@6c            ù             !altr,socfpga-a10-perip-clk           Ê            F   l      main_emac_ptp_clk@70             ù             !altr,socfpga-a10-perip-clk           Ê            F   p      main_gpio_db_clk@74          ù             !altr,socfpga-a10-perip-clk           Ê            F   t      main_sdmmc_clk@78            ù             !altr,socfpga-a10-perip-clk           Ê            F   x         [         main_s2f_usr0_clk@7c             ù             !altr,socfpga-a10-perip-clk           Ê            F   |      main_s2f_usr1_clk@80             ù             !altr,socfpga-a10-perip-clk           Ê            F   €         [         main_hmc_pll_ref_clk@84          ù             !altr,socfpga-a10-perip-clk           Ê            F   „      main_periph_ref_clk@9c           ù             !altr,socfpga-a10-perip-clk           Ê            F   œ         [            periph_pll@c0                                      ù             !altr,socfpga-a10-pll-clock           Ê      	   
            F   À         [      peri_mpu_base_clk            ù             !altr,socfpga-a10-perip-clk           Ê             @               [         peri_noc_base_clk            ù             !altr,socfpga-a10-perip-clk           Ê             D               [         peri_emaca_clk@e8            ù             !altr,socfpga-a10-perip-clk           Ê            F   è      peri_emacb_clk@ec            ù             !altr,socfpga-a10-perip-clk           Ê            F   ì      peri_emac_ptp_clk@f0             ù             !altr,socfpga-a10-perip-clk           Ê            F   ð         [         peri_gpio_db_clk@f4          ù             !altr,socfpga-a10-perip-clk           Ê            F   ô      peri_sdmmc_clk@f8            ù             !altr,socfpga-a10-perip-clk           Ê            F   ø         [         peri_s2f_usr0_clk@fc             ù             !altr,socfpga-a10-perip-clk           Ê            F   ü      peri_s2f_usr1_clk@100            ù             !altr,socfpga-a10-perip-clk           Ê            F            [         peri_hmc_pll_ref_clk@104             ù             !altr,socfpga-a10-perip-clk           Ê            F           mpu_free_clk@60          ù             !altr,socfpga-a10-perip-clk           Ê               
         F   `         [         noc_free_clk@64          ù             !altr,socfpga-a10-perip-clk           Ê               
         F   d         [         s2f_user1_free_clk@104           ù             !altr,socfpga-a10-perip-clk           Ê               
         F        sdmmc_free_clk@f8            ù             !altr,socfpga-a10-perip-clk           Ê               
                    F   ø         [         l4_sys_free_clk          ù             !altr,socfpga-a10-perip-clk           Ê                       [   -      l4_main_clk          ù             !altr,socfpga-a10-gate-clk            Ê              ¨               ,   H            [         l4_mp_clk            ù             !altr,socfpga-a10-gate-clk            Ê              ¨              ,   H            [         l4_sp_clk            ù             !altr,socfpga-a10-gate-clk            Ê              ¨              ,   H            [         mpu_periph_clk           ù             !altr,socfpga-a10-gate-clk            Ê                      ,   H             [   ,      sdmmc_clk            ù             !altr,socfpga-a10-gate-clk            Ê           ,   È            [   $      qspi_clk             ù             !altr,socfpga-a10-gate-clk            Ê           ,   È            [   +      nand_x_clk           ù             !altr,socfpga-a10-gate-clk            Ê           ,   È   
         [         nand_ecc_clk             ù             !altr,socfpga-a10-gate-clk            Ê           ,   È   
         [   &      nand_clk             ù             !altr,socfpga-a10-gate-clk            Ê                      ,   È   
         [   %      spi_m_clk            ù             !altr,socfpga-a10-gate-clk            Ê           ,   È   	         [   !      usb_clk          ù             !altr,socfpga-a10-gate-clk            Ê           ,   È            [   .      s2f_usr1_clk             ù             !altr,socfpga-a10-gate-clk            Ê           ,   È               stmmac-axi-config           5           E           U                                    [         ethernet@ff800000         8   !altr,socfpga-stmmac-a10-s10 snps,dwmac-3.72a snps,dwmac         _      D             Fÿ€               t       \           rmacirq          ‚                Ž           ©   €        Å           Ó  @          Ê               Ñstmmaceth ptp_ref            Ý             (         ästmmaceth stmmaceth-ocp         á           ñokay            ørgmii           ÿÿÿÿ        
                        $            1            >  ¤        K  ¤        X  ¤        e  ¤        r              D        ‹  ¤        ˜  �        ¤  Ø         [   (      ethernet@ff802000         8   !altr,socfpga-stmmac-a10-s10 snps,dwmac-3.72a snps,dwmac         _      H            Fÿ€               t       ]           rmacirq          ‚                Ž           ©   €        Å           Ó  @          Ê               Ñstmmaceth ptp_ref            Ý      !      )         ästmmaceth stmmaceth-ocp         á         	  ñdisabled          ethernet@ff804000         8   !altr,socfpga-stmmac-a10-s10 snps,dwmac-3.72a snps,dwmac         _      L            Fÿ€@              t       ^           rmacirq          ‚                Ž           ©   €        Å           Ó  @          Ê               Ñstmmaceth ptp_ref            Ý      "      *         ästmmaceth stmmaceth-ocp         á         	  ñdisabled          gpio@ffc02900                                      !snps,dw-apb-gpio             FÿÀ)             Ý      X      	  ñdisabled       gpio-controller@0            !snps,dw-apb-gpio-port            ³        Ã           Ï            F              £         ’            t       p            gpio@ffc02a00                                      !snps,dw-apb-gpio             FÿÀ*             Ý      Y        ñokay       gpio-controller@0            !snps,dw-apb-gpio-port            ³        Ã           Ï            F              £         ’            t       q            [   #         gpio@ffc02b00                                      !snps,dw-apb-gpio             FÿÀ+             Ý      Z      	  ñdisabled       gpio-controller@0            !snps,dw-apb-gpio-port            ³        Ã           Ï            F              £         ’            t       r            fpga-mgr@ffd03000            !altr,socfpga-a10-fpga-mgr            FÿÐ0    ÿÏä              Ê            Ý      ƒ         äfpgamgr          [         i2c@ffc02200                                       !snps,designware-i2c          FÿÀ"             t       i            Ê            Ý      H      	  ñdisabled          i2c@ffc02300                                       !snps,designware-i2c          FÿÀ#             t       j            Ê            Ý      I        ñokay             †         Ý  p        õ  p   adc@14           !lltc,ltc2497             F                     adc@16           !lltc,ltc2497             F                     eeprom@51            !atmel,24c32          F   Q                  rtc@68           !dallas,ds1339            F   h      ltc@5c           !ltc2977          F   \      temp@4c          !maxim,max1619            F   L         i2c@ffc02400                                       !snps,designware-i2c          FÿÀ$             t       k            Ê            Ý      J      	  ñdisabled          i2c@ffc02500                                       !snps,designware-i2c          FÿÀ%             t       l            Ê            Ý      K      	  ñdisabled          i2c@ffc02600                                       !snps,designware-i2c          FÿÀ&             t       m            Ê            Ý      L      	  ñdisabled          spi@ffda4000             !snps,dw-apb-ssi                                    FÿÚ@             t       e           "            Ê   !         Ý      1         äspi       	  ñdisabled          spi@ffda5000             !snps,dw-apb-ssi                                    FÿÚP             t       f           "           )   "           8   "            Ê   !         Ý      2         äspi         ñokay       resource-manager@0           !altr,a10sr           F            G †          c   #         t                £         ’      gpio-controller          !altr,a10sr-gpio          ³        Ã            [   0      reset-controller             !altr,a10sr-reset            Y               sdr@ffcfb100             !altr,sdr-ctl syscon          FÿÏ±    €         [   '      cache-controller@fffff000            !arm,pl310-cache          Fÿÿð             t                   f        t           €           Ž            �         [         mmc@ff808000                                       !altr,socfpga-dw-mshc             Fÿ€€             t       b           È            Ê      $         Ñbiu ciu          Ý      '        _      (         	  ñdisabled             [   )      nand-controller@ffb90000                                       !altr,socfpga-denali-nand             Fÿ¹     ÿ¸             ±nand_data denali_reg             t       c            Ê   %      &         Ñnand nand_x ecc          Ý      %      	  ñdisabled          sram@ffe00000         
   !mmio-sram            Fÿà           eccmgr           !altr,socfpga-a10-ecc-manager            _                                     t                               £         ’             ¸   sdramedac            !altr,sdram-edac-a10         »   '         t         1         l2-ecc@ffd06010          !altr,socfpga-a10-l2-ecc          FÿÐ`            t                    ocram-ecc@ff8c3000           !altr,socfpga-a10-ocram-ecc           FÿŒ0             t         !         emac0-rx-ecc@ff8c0800            !altr,socfpga-eth-mac-ecc             FÿŒ            Ë   (         t         $         emac0-tx-ecc@ff8c0c00            !altr,socfpga-eth-mac-ecc             FÿŒ            Ë   (         t         %         sdmmca-ecc@ff8c2c00          !altr,socfpga-sdmmc-ecc           FÿŒ,            Ë   )          t         /            0         dma-ecc@ff8c8000             !altr,socfpga-dma-ecc             FÿŒ€            Ë   "         t   
      *         usb0-ecc@ff8c8800            !altr,socfpga-usb-ecc             FÿŒˆ            Ë   *         t         "            spi@ff809000          !   !intel,socfpga-qspi cdns,qspi-nor                                       Fÿ€�    ÿ               t       d           Û   €        ë           û             Ê   +         Ý      &      .         äqspi qspi-ocp           ñokay       flash@0                                   !micron,mt25qu02g jedec,spi-nor           F            Gõá                             /   2        =   2        K           Y      partition@qspi-boot         gBoot and fpga data           F    r        partition@qspi-rootfs           gRoot Filesystem - JFFS2          Fr  Ž              rstmgr@ffd05000         Y            !altr,rst-mgr             FÿÐP            m             [         snoop-control-unit@ffffc000          !arm,cortex-a9-scu            FÿÿÀ          sysmgr@ffd06000          !altr,sys-mgr syscon          FÿÐ`            €ÿÐb0         [         timer@ffffc600           !arm,cortex-a9-twd-timer          FÿÿÆ             t                 Ê   ,      timer0@ffc02700          !snps,dw-apb-timer            t       s            FÿÀ'             Ê            Ñtimer            Ý      D         ätimer         timer1@ffc02800          !snps,dw-apb-timer            t       t            FÿÀ(             Ê            Ñtimer            Ý      E         ätimer         timer2@ffd00000          !snps,dw-apb-timer            t       u            FÿÐ              Ê   -         Ñtimer            Ý      B         ätimer         timer3@ffd00100          !snps,dw-apb-timer            t       v            FÿÐ             Ê   -         Ñtimer            Ý      C         ätimer         serial@ffc02000          !snps,dw-apb-uart             FÿÀ              t       n           �           š            Ê            Ý      P      	  ñdisabled          serial@ffc02100          !snps,dw-apb-uart             FÿÀ!             t       o           �           š            Ê            Ý      Q        ñokay          usbphy          §             !usb-nop-xceiv           ñokay             [   /      usb@ffb00000          
   !snps,dwc2            Fÿ°    ÿÿ         t       _            Ê   .         Ñotg          Ý      #         ädwc2            ²   /      	  ·usb2-phy            ñokay             Á         [   *      usb@ffb40000          
   !snps,dwc2            Fÿ´    ÿÿ         t       `            Ê   .         Ñotg          Ý      $         ädwc2            ²   /      	  ·usb2-phy          	  ñdisabled          watchdog@ffd00200            !snps,dw-wdt          FÿÐ             t       w            Ê   -         Ý      @      	  ñdisabled          watchdog@ffd00300            !snps,dw-wdt          FÿÐ             t       x            Ê   -         Ý      A        ñokay             aliases         Ö/soc/ethernet@ff800000          à/soc/serial@ffc02100          chosen          èearlyprintk         ñserial0:115200n8          memory@0             :memory           F    @         a10leds       
   !gpio-leds      a10sr_led0          ga10sr-led0          ×   0             a10sr_led1          ga10sr-led1          ×   0            a10sr_led2          ga10sr-led2          ×   0            a10sr_led3          ga10sr-led3          ×   0               033-v-ref            !regulator-fixed         ý0.33V            	        $ 	         [             	#address-cells #size-cells model compatible enable-method device_type reg next-level-cache phandle interrupt-parent interrupts interrupt-affinity #interrupt-cells interrupt-controller ranges #dma-cells clocks clock-names resets reset-names fpga-mgr #clock-cells clock-frequency div-reg fixed-divider clk-gate snps,wr_osr_lmt snps,rd_osr_lmt snps,blen altr,sysmgr-syscon interrupt-names mac-address snps,multicast-filter-bins snps,perfect-filter-entries tx-fifo-depth rx-fifo-depth snps,axi-config status phy-mode phy-addr txd0-skew-ps txd1-skew-ps txd2-skew-ps txd3-skew-ps rxd0-skew-ps rxd1-skew-ps rxd2-skew-ps rxd3-skew-ps txen-skew-ps txc-skew-ps rxdv-skew-ps rxc-skew-ps max-frame-size gpio-controller #gpio-cells snps,nr-gpios i2c-sda-falling-time-ns i2c-scl-falling-time-ns vref-supply pagesize num-cs tx-dma-channel rx-dma-channel spi-max-frequency #reset-cells cache-unified cache-level prefetch-data prefetch-instr arm,shared-override reg-names altr,sdr-syscon altr,ecc-parent cdns,fifo-depth cdns,fifo-width cdns,trigger-address m25p,fast-read cdns,read-delay cdns,tshsl-ns cdns,tsd2d-ns cdns,tchsh-ns cdns,tslch-ns label altr,modrst-offset cpu1-start-addr reg-shift reg-io-width #phy-cells phys phy-names disable-over-current ethernet0 serial0 bootargs stdout-path regulator-name regulator-min-microvolt regulator-max-microvolt 