Ðþí Tv   8 H|   (            ú HD                             4    mediatek,mt8395-evk mediatek,mt8395 mediatek,mt8195                                  +         "   7MediaTek Genio 1200 EVK-P1V2-EMMC      aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/mailbox@10320000            T/soc/mailbox@10330000            Y/soc/hdr-engine@1c114000             `/soc/mutex@1c016000          g/soc/mutex@1c101000          n/soc/vpp-merge@1c10c000          u/soc/vpp-merge@1c10d000          |/soc/vpp-merge@1c10e000          ƒ/soc/vpp-merge@1c10f000          Š/soc/vpp-merge@1c110000          ‘/soc/dma-controller@1c104000             œ/soc/dma-controller@1c105000             §/soc/dma-controller@1c106000             ²/soc/dma-controller@1c107000             ½/soc/dma-controller@1c108000             È/soc/dma-controller@1c109000             Ó/soc/dma-controller@1c10a000             Þ/soc/dma-controller@1c10b000             é/soc/serial@11001100             ñ/soc/ethernet@11021000        cpus                         +       cpu@0            ûcpu           arm,cortex-a55                      psci                           -ec3@        =  4        P              `  €         m   @           €        Œ  €         ™   @        «   €        ¸           É           Ø   	      cpu@100          ûcpu           arm,cortex-a55                     psci                           -ec3@        =  4        P              `  €         m   @           €        Œ  €         ™   @        «   €        ¸           É           Ø   
      cpu@200          ûcpu           arm,cortex-a55                     psci                           -ec3@        =  4        P              `  €         m   @           €        Œ  €         ™   @        «   €        ¸           É           Ø         cpu@300          ûcpu           arm,cortex-a55                     psci                           -ec3@        =  4        P              `  €         m   @           €        Œ  €         ™   @        «   €        ¸           É           Ø         cpu@400          ûcpu           arm,cortex-a78                     psci                          -�fÔÀ        =           P              `           m   @                   Œ           ™   @        «           ¸           É           Ø         cpu@500          ûcpu           arm,cortex-a78                     psci                          -�fÔÀ        =           P              `           m   @                   Œ           ™   @        «           ¸           É           Ø         cpu@600          ûcpu           arm,cortex-a78                     psci                          -�fÔÀ        =           P              `           m   @                   Œ           ™   @        «           ¸           É           Ø         cpu@700          ûcpu           arm,cortex-a78                     psci                          -�fÔÀ        =           P              `           m   @                   Œ           ™   @        «           ¸           É           Ø         cpu-map    cluster0       core0           à   	      core1           à   
      core2           à         core3           à         core4           à         core5           à         core6           à         core7           à               idle-states         äpsci       cpu-retention-l           arm,idle-state          ñ                      2        *   _        :  D        Ø         cpu-retention-b           arm,idle-state          ñ                      -        *   Œ        :  ä        Ø         cpu-off-l             arm,idle-state          ñ                     7        *   ›        :  H        Ø         cpu-off-b             arm,idle-state          ñ                     2        *   È        :  è        Ø            l2-cache0             cache           K           b           o   @        �           ¸            W        Ø         l2-cache1             cache           K           b           o   @        �           ¸            W        Ø         l3-cache              cache           K           b            o   @        �            W        Ø            dsu-pmu           arm,dsu-pmu         e                       p   	   
                          ufail          dmic-codec            dmic-codec          |           ‰   È      mt8195-sound            ™         	  udisabled          fixed-factor-clock-13m            fixed-factor-clock          «            ¸           ¿           É           Ôclk13m          Ø   )      oscillator-26m            fixed-clock         «            -Œº€        Ôclk26m          Ø         oscillator-32k            fixed-clock         «            -  €         Ôclk32k        performance-controller@11bc10             mediatek,cpufreq-hw               ¼            ½0               ç           Ø         opp-table-gpu             operating-points-v2                  Ø   o   opp-390000000               >í€         	‰h      opp-410000000               p€         	¡Ò      opp-431000000               °‰À         	¡Ò      opp-473000000               1h@         	º<      opp-515000000               ²FÀ         	º<      opp-556000000               !#ã          	Ò¦      opp-598000000               #¤Á€         	ë      opp-640000000               &%           	ë      opp-670000000               'ïc€         
ä      opp-700000000               )¹'          
L¸      opp-730000000               +‚ê€         
}Œ      opp-760000000               -L®          
®`      opp-790000000               /q€         
ß4      opp-820000000               0à5                opp-850000000               2©ø€         @Ü      opp-880000000               4s¼          q°         pmu-a55           arm,cortex-a55-pmu                      e                  pmu-a78           arm,cortex-a78-pmu                      e                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  e                                             
             soc                      +             simple-bus           !        (                          interrupt-controller@c000000              arm,gic-v3          3           D                        [                                             e      	               Ø      ppi-partitions     interrupt-partition-0           p   	   
              Ø         interrupt-partition-1           p                    Ø               syscon@10000000            mediatek,mt8195-topckgen syscon                               «           Ø         syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon                               «           y           Ø         syscon@10003000           mediatek,mt8195-pericfg syscon               0                «           Ø   B      pinctrl@10005000              mediatek,mt8195-pinctrl       €       P            Ñ             Ó             Ô             â             ë             ô              °              B  †iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            �                    ¬              �         [        e       ë               3           Ø      audio-default-pins     pins-cmd-dat          4  ¸  =  >  A  B  C  D  E  F  G  H  I  J  K         disp-pwm1-default-pins     pins1           ¸  h         edp-panel-12v-en-pins           Ø   ±   pins1           ¸  `          ¿         edp-panel-3v3-en-pins           Ø   °   pins1           ¸            ¿         eth-default-pins            Ø   >   pins-cc         ¸  U  V  W  X        Ë         pins-mdio           ¸  Y  Z         Ú      pins-power          ¸  [   \          ¿      pins-rxd            ¸  Q  R  S  T      pins-txd            ¸  M  N  O  P        Ë            eth-sleep-pins          Ø   ?   pins-cc         ¸  U   V   W   X       pins-mdio           ¸  Y   Z          ç         õ      pins-rxd            ¸  Q   R   S   T       pins-txd            ¸  M   N   O   P          gpio-keys-pins     pins            ¸  j                   Ú         i2c0-pins           Ø   \   pins            ¸    	           Ï          è         i2c1-pins           Ø   ]   pins            ¸  
             Ï          è         i2c2-pins           Ø   `   pins            ¸               Ï        Ë            i2c6-pins           Ø   X   pins            ¸                      mmc0-default-pins           Ø   D   pins-clk            ¸  z        Ë           '   f      pins-cmd-dat          $  ¸  ~  }  |  {  w  v  u  t  y         Ú        Ë              e      pins-rst            ¸  x        Ë              e         mmc0-uhs-pins           Ø   E   pins-clk            ¸  z        Ë           '   f      pins-cmd-dat          $  ¸  ~  }  |  {  w  v  u  t  y         Ú        Ë              e      pins-ds         ¸          Ë           '   f      pins-rst            ¸  x        Ë              e         mmc1-default-pins           Ø   H   pins-clk            ¸  o        Ë           '   f      pins-cmd-dat            ¸  n  p  q  r  s         Ú        Ë              e         mmc1-uhs-pins           Ø   I   pins-clk            ¸  o        Ë           '   f      pins-cmd-dat            ¸  n  p  q  r  s         Ú        Ë              e         mt6360-pins         Ø   Y   pins            ¸     €          Ú                  pcie0-default-pins          Ø   S   pins            ¸                        pcie0-idle-pins         Ø   T   pins            ¸            õ         6         pcie1-default-pins          Ø   V   pins            ¸                        pwm0-default-pins           Ø   5   pins-cmd-dat            ¸  a         spi1-pins           Ø   6   pins            ¸  ˆ  ‰  Š  ‹         õ         spi-pins            Ø   9   pins            ¸  Œ  �  Ž  �         õ         touch-pins          Ø   _   pins-irq            ¸  „          Ú         õ      pins-reset          ¸  …          ¿         uart0-pins          Ø   0   pins            ¸  b  c         uart1-pins          Ø   1   pins            ¸  d  e  f  g            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8195-power-controller                         +            A           Ø   ,   power-domain@8                                  +            A           U      power-domain@9             	        ¸                    cmfg alt         o                        +            A      power-domain@10            
        A          power-domain@11                    A          power-domain@12                    A          power-domain@13                    A          power-domain@14                    A                power-domain@15                  Ø  ¸                        	      @      A      K      à                                                                                                                          cvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           o                        +            A      power-domain@16                  8  ¸      â      $      %      &      '      (      )      D  cvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         o                        +            A      power-domain@17                    ¸      á                    cvppsys1 vppsys1-0 vppsys1-1         o           A          power-domain@22                     ¸                              $  cwepsys-0 wepsys-1 wepsys-2 wepsys-3         o           A          power-domain@23                    ¸               cvdec0-0         o                        +            A       power-domain@24                    ¸                cvdec1-0         o           A          power-domain@25                    ¸   !            cvdec2-0         o           A             power-domain@26                    ¸   "            cvenc0-larb          o                        +            A       power-domain@27                    ¸   #            cvenc1-larb          o           A             power-domain@18                     ¸      ã   $       $      $         &  cvdosys1 vdosys1-0 vdosys1-1 vdosys1-2           o                        +            A      power-domain@19                    o           A          power-domain@20                    o           A          power-domain@21                    ¸      Q        chdmi_tx         A             power-domain@28                    ¸   %       %   
        cimg-0 img-1         o                        +            A      power-domain@29                    A          power-domain@30                    ¸         %      &           cipe ipe-0 ipe-1         o           A             power-domain@31                  (  ¸   '       '      '      '      '           ccam-0 cam-1 cam-2 cam-3 cam-4           o                        +            A      power-domain@32                     A          power-domain@33            !        A          power-domain@34            "        A                   power-domain@0                      o           A          power-domain@1                     o           A          power-domain@2                     A          power-domain@3                     A          power-domain@4                     ¸      5      7        ccsi_rx_top csi_rx_top1          A          power-domain@5                     ¸   (           cether           A          power-domain@6                     ¸      X      n        cadsp adsp1                       +            o           A      power-domain@7                      ¸      g      "      n      2        caudio audio1 audio2 audio3          o           A                   watchdog@10007000             mediatek,mt8195-wdt          �             p                y           Ø   /      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon                À                «           Ø         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer             p                e      	               ¸   )      pwrap@10024000            mediatek,mt8195-pwrap syscon                @                †pwrap           e       ó               ¸                   	  cspi wrap            ™      $        ©      Ë   pmic              mediatek,mt6359          [        3           À      Þ      adc           mediatek,mt6359-auxadc          Ô         mt6359codec         æ           ú                    regulators            mediatek,mt6359-regulator      buck_vs1            "vs1         1 5         I !‘À        a             }      buck_vgpu11         "vgpu11          1 €        I 7        ‘  ˆ        a   È        ¦                   }      buck_vmodem         "vmodem          1 €        I Èà        ‘  *        a   È      buck_vpu            "vpu         1 €        I 7        ‘  ˆ        a   È        ¦                   }      buck_vcore          "vcore           1 €        I Ö         ‘  ˆ        a   È        ¦                   }      buck_vs2            "vs2         1 5         I j         a             }      buck_vpa            "vpa         1 ¡         I 7±Ð        a  ,      buck_vproc2         "vproc2          1 €        I 7        ‘  L        a   È        ¦                buck_vproc1         "vproc1          1 €        I 7        ‘  L        a   È        ¦                buck_vcore_sshub            "vcore_sshub         1 €        I 7      buck_vgpu11_sshub           "vgpu11_sshub            1 €        I 7      ldo_vaud18          "vaud18          1 w@        I w@        a   ð         }      ldo_vsim1           "vsim1           1 ð         I /M`      ldo_vibr            "vibr            1 O€        I 2Z       ldo_vrf12           "vrf12           1 Èà        I Ö          }      ldo_vusb            "vusb            1 -ÆÀ        I -ÆÀ        a  À         }        Ø   C      ldo_vsram_proc2         "vsram_proc2         1 ¡         I ½¶        ‘  L        a   ð         }      ldo_vio18           "vio18           1 ð         I ýà        a  À         }      ldo_vcamio          "vcamio          1 ð         I ýà         }      ldo_vcn18           "vcn18           1 w@        I w@        a   ð      ldo_vfe28           "vfe28           1 *¹€        I *¹€        a   x      ldo_vcn13           "vcn13           1 »         I Ö       ldo_vcn33_1_bt          "vcn33_1_bt          1 *¹€        I 5gà      ldo_vcn33_1_wifi            "vcn33_1_wifi            1 *¹€        I 5gà      ldo_vaux18          "vaux18          1 w@        I w@        a   ð         }      ldo_vsram_others            "vsram_others            1 ¡         I ½¶        ‘  ˆ        a   ð      ldo_vefuse          "vefuse          1 ð         I „€      ldo_vxo22           "vxo22           1 w@        I !‘À         }      ldo_vrfck           "vrfck           1 ã`        I ð       ldo_vrfck_1         "vrfck           1 ëÀ        I j       ldo_vbif28          "vbif28          1 *¹€        I *¹€        a   ð      ldo_vio28           "vio28           1 *¹€        I 2Z          }      ldo_vemc            "vemc            1 ,@         I 2Z       ldo_vemc_1          "vemc            1 &%         I 2Z         Ø   F      ldo_vcn33_2_bt          "vcn33_2_bt          1 2Z         I 2Z         Ø   8      ldo_vcn33_2_wifi            "vcn33_2_wifi            1 *¹€        I 5gà      ldo_va12            "va12            1 O€        I Ö          }      ldo_va09            "va09            1 5         I O€      ldo_vrf18           "vrf18           1 ð         I žP      ldo_vsram_md          	  "vsram_md            1 ¡         I ½¶        ‘  *        a   ð      ldo_vufs            "vufs            1 ð         I ýà        Ø   G      ldo_vm18            "vm18            1 ð         I ýà         }      ldo_vbbck           "vbbck           1 Èà        I O€         }      ldo_vsram_proc1         "vsram_proc1         1 ¡         I ½¶        ‘  L        a   ð         }      ldo_vsim2           "vsim2           1 ð         I /M`      ldo_vsram_others_sshub          "vsram_others_sshub          1 ¡         I ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi                 p            �                †pmif spmimst            ¸                   E      (  cpmif_sys_ck pmif_tmr_ck spmimst_clk_mux         ™      $        ©      Ë                     +       pmic@6            mediatek,mt6315-regulator                     regulators     vbuck1          "Vbcpu           1 “à        I 7        a           ¦                   }            pmic@7            mediatek,mt6315-regulator                     regulators     vbuck1          "Vgpu            1 “à        I 7        a           ¦                  Ø                  infra-iommu@10315000              mediatek,mt8195-iommu-infra             1P       P       P  e                                                                         ¾           Ø   P      mailbox@10320000              mediatek,mt8195-gce             2        @         e       â               Ë           ¸              Ø   ’      mailbox@10330000              mediatek,mt8195-gce             3        @         e       ä               Ë           ¸              Ø   p      scp@10500000              mediatek,mt8195-scp       0      P             r             p        €         †sram cfg l1tcm          e      Î               uokay            ×   *        Ø   q      clock-controller@10720000             mediatek,mt8195-scp_adsp                r                 «           Ø   +      dsp@10803000              mediatek,mt8195-dsp              €0            „               	  †cfg sram          ,  ¸      X         n      Š   +          #      K  cadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          å   ,           órx tx           þ   -   .      	  udisabled          mailbox@10816000              mediatek,mt8195-adsp-mbox           Ë                �`                e      ¾               Ø   -      mailbox@10817000              mediatek,mt8195-adsp-mbox           Ë                �p                e      ¿               Ø   .      mt8195-afe-pcm@10890000           mediatek,mt8195-audio               ‰                            å   ,           e      6                  /         	  audiosys          ”  ¸                     Ú      Û      Ü      Ý      ß      g      "      #      n      e      a      b      c      d      2   +          ó  cclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  udisabled            Ø         serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e       �               ¸               	  cbaud bus            uokay            *   0        4default       serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e       Ž               ¸               	  cbaud bus            uokay            *   1        4default       serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e       �               ¸               	  cbaud bus          	  udisabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e      Ó               ¸               	  cbaud bus          	  udisabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e      Ô               ¸               	  cbaud bus          	  udisabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e      Õ               ¸               	  cbaud bus          	  udisabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc                                 ¸              cmain            Ô         	  udisabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon                0                «           Ø   (      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  e       ¿               ¸      ™                    cparent-clk sel-clk spi-clk        	  udisabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap              °                e       ©               ¸                             B   2   3      $  Nlvts-calib-data-1 lvts-calib-data-2         _           Ø   ­      svs@1100bc00              mediatek,mt8195-svs              ¼                e       Ç               ¸              cmain            B   4   2      (  Nsvs-calibration-data t-calibration-data                       svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                à                e       Ë               å   ,           u           ¸      *      0        cmain mm         uokay            4default         *   5        Ø   ®      pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                ð                e                     u           ¸      +      N        cmain mm       	  udisabled            Ø   ¯      spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 e       À               ¸      ™            3        cparent-clk sel-clk spi-clk          uokay            *   6        4default         €            ”      @      can@0             microchip,mcp2518fd                     ¸   7        �1-         À                 ¯   8        º   8         spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 e       Á               ¸      ™            4        cparent-clk sel-clk spi-clk          uokay            *   9        4default         €          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                0                e       Â               ¸      ™            5        cparent-clk sel-clk spi-clk        	  udisabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                €                e       Ã               ¸      ™            <        cparent-clk sel-clk spi-clk        	  udisabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                �                e       Ä               ¸      ™            =        cparent-clk sel-clk spi-clk        	  udisabled          spi@1101d000              mediatek,mt8195-spi-slave               Ð                e       Å               ¸      R        cspi         ™              ©      ˜      	  udisabled          spi@1101e000              mediatek,mt8195-spi-slave               à                e       Æ               ¸      S        cspi         ™              ©      ˜      	  udisabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a                      @         e      Ì               Émacirq        .  caxi apb mac_main ptp_ref rmii_internal mac_cg         0  ¸   (       (         R      S      T   (           ™      R      S      T        ©      Â      Ã      Ä        å   ,           Ù           ê   :        ú   ;           <                    +           6            uokay            Crgmii-rxid          L   =        W      ]            g      '  '        |  î         ‘        4default sleep           *   >        ¢   ?   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916                       Ø   =         stmmac-axi-config           ¬           ¼           Ì                                 Ø   :      rx-queues-config            Ö            ì        Ø   ;   queue0           ý                  queue1           ý                  queue2           ý                  queue3           ý                     tx-queues-config            (            >        Ø   <   queue0          P            ý        \          queue1          P            ý        \         queue2          P            ý        \         queue3          P            ý        \               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3                       -ÿ     >              	  †mac ippc            !                     ?                      +           e       €               ¸      /      í      B        csys_ck ref_ck mcu_ck            j   @      A            o        }   B      g        uokay            ”   C   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 †mac         e       �               ™      ,      -        ©      –      –      $  ¸      /      í               B      $  csys_ck ref_ck mcu_ck dma_ck xhci_ck         uokay             mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              #             õ                 e       ƒ               ¸                          csource hclk source_cg           uokay            4default state_uhs           *   D        ¢   E        ¢           ¡ëÂ          ¬         ¾         Í         Ü         í         õ        û L        	
   F        	   G         	#      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              $             Ç                 e       ‡               ¸                  $        csource hclk source_cg           ™              ©      ¿        uokay            4default state_uhs           *   H        ¢   I        ¢           ¡ëÂ          	1         	B         	O         	]         í        	
   J        	   K         	#      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              %             æ                 e       ˆ               ¸                   I        csource hclk source_cg           ™               ©      ¿      	  udisabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu                '€                e       ª               ¸                            B   2   3      $  Nlvts-calib-data-1 lvts-calib-data-2         _           Ø   ¤      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci               )             )>              	  †mac ippc            e                     j   L      M           ™      .      /        ©      –      –      $  ¸   (         ï            (         $  csys_ck ref_ck mcu_ck dma_ck xhci_ck         }   B      h         o        uokay            ”   C      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               *       -ÿ    *>              	  †mac ippc            !            *        ?                      +           e                     ™      0        ©      –        ¸   (         ñ   (           csys_ck ref_ck mcu_ck            j   N            o        }   B      i        uokay            ”   C   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 †mac         e                     ™      1        ©      –        ¸   (           csys_ck          uokay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               +       -ÿ    +>              	  †mac ippc            !            +        ?                      +           e                     ™      2        ©      –        ¸   (         ó   (   	        csys_ck ref_ck mcu_ck            j   O            o        }   B      j        uokay            ”   C   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 †mac         e                     ™      3        ©      –        ¸   (   	        csys_ck          uokay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            ûpci                      +               /        @       	  †pcie-mac            e                     	d       ÿ      8  !�                           ‚                       à          	n       P              	x          0  ¸      V      #      &      +      K   (         /  cpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ™      G        ©              j   Q      	  	‡pcie-phy            å   ,                          mac         3           	‘                     `  	¤                  R                      R                     R                     R           uokay            4default idle            *   S        ¢   T   interrupt-controller             [                     3           Ø   R         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            ûpci                      +               /€       @       	  †pcie-mac            e                     	d       ÿ      8  !�       $       $           ‚       $       $       à          	n       P              	x          (  ¸      W         X         Q   (         /  cpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ™      H        ©              j   M         	  	‡pcie-phy            å   ,           3           	‘                     `  	¤                  U                      U                     U                     U         	  udisabled            4default         *   V   interrupt-controller             [                     3           Ø   U         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor             2À                e      9               ¸      o   (      (           cspi sf axi                       +          	  udisabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse                Á                              +      usb3-tx-imp@184,1             „           	²               Ø   f      usb3-rx-imp@184,2             „           	²              Ø   e      usb3-intr@185             …           	²              Ø   d      usb3-tx-imp@186,1             †           	²               Ø   c      usb3-rx-imp@186,2             †           	²              Ø   b      usb3-intr@187             ‡           	²              Ø   a      usb2-intr-p0@188,1            ˆ           	²             usb2-intr-p1@188,2            ˆ           	²            usb2-intr-p2@189,1            ‰           	²            usb2-intr-p3@189,2            ‰           	²            pciephy-rx-ln1@190,1              �           	²               Ø   m      pciephy-tx-ln1-nmos@190,2             �           	²              Ø   l      pciephy-tx-ln1-pmos@191,1             ‘           	²               Ø   k      pciephy-rx-ln0@191,2              ‘           	²              Ø   j      pciephy-tx-ln0-nmos@192,1             ’           	²               Ø   i      pciephy-tx-ln0-pmos@192,2             ’           	²              Ø   h      pciephy-glb-intr@193              “           	²               Ø   g      dp-data@1ac           ¬           Ø   £      lvts1-calib@1bc           ¼           Ø   2      lvts2-calib@1d0           Ð   8        Ø   3      svs-calib@580             €   d        Ø   4      socinfo-data1@7a0                          t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           !        Ä             uokay       usb-phy@0                          ¸      ò        cref         	·           Ø   N         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           !        Å             uokay       usb-phy@0                          ¸      ô        cref         	·           Ø   O         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx             È                 ¸           Ômipi_tx0_pll            «            	·          	  udisabled            Ø   “      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx             É                 ¸           Ômipi_tx1_pll            «            	·          	  udisabled            Ø   ”      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð             "€       €        e       š               ¿           ¸   W          ;      	  cmain dma                         +          	  udisabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð            "        €        e       ›               ¿           ¸   W         ;      	  cmain dma                         +            uokay            - €        *   X        4default    pmic@34           mediatek,mt6360            4                    e   €           ÉIRQB             [        3           *   Y   charger           mediatek,mt6360-chg         	Â Ý@    usb-otg-vbus-regulator          "usb-otg-vbus            1 C…(        I Xáè         regulator             mediatek,mt6360-regulator           	Û   Z   buck1         	  "emi_vdd2            1 “à        I Ö         ¦                   }      buck2         	  "emi_vddq            1 “à        I Ö         ¦                   }        Ø   Z      ldo1          	  "tp1_p3v0            1 2Z         I 2Z         ¦                }        Ø   ^      ldo2            "panel1_p1v8         1 w@        I w@        ¦             ldo3            "vmc_pmu         1 O€        I 6î€        ¦               Ø   K      ldo5          	  "vmch_pmu            1 )2à        I 6î€        ¦               Ø   J      ldo6            "mt6360_ldo1         1 ¡         I           ¦             ldo7            "emi_vmddr_en            1 ¡         I           ¦                }               i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð             "€       €        e       œ               ¿           ¸   W         ;      	  cmain dma                         +          	  udisabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s              Ð0                «           Ø   W      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à             " €       €        e       �               ¿           ¸   [          ;      	  cmain dma                         +            uokay            - €        *   \        4default       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à            "        €        e       “               ¿           ¸   [         ;      	  cmain dma                         +            uokay            - €        *   ]        4default    touchscreen@5d            goodix,gt9271              ]        À      „           	ë      „            	õ      …            
   ^        4default         *   _         i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à             "€       €        e       –               ¿           ¸   [         ;      	  cmain dma                         +            uokay            - €        *   `        4default       i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à0            "€       €        e       ˜               ¿           ¸   [         ;      	  cmain dma                         +          	  udisabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à@            "        €        e       ™               ¿           ¸   [         ;      	  cmain dma                         +          	  udisabled          clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w              àP                «           Ø   [      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           !        ã             å   ,           uokay       usb-phy@0                          ¸      ð           cref da_ref          	·           Ø   L      usb-phy@700                       ¸            ð        cref da_ref          B   a   b   c        Nintr rx_imp tx_imp          	·            
        Ø   M         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           !        ä             uokay       usb-phy@0                          ¸      î           cref da_ref          	·           Ø   @      usb-phy@700                       ¸            î        cref da_ref          B   d   e   f        Nintr rx_imp tx_imp          	·           Ø   A         phy@11e80000              mediatek,mt8195-pcie-phy                è                 †sif         B   g   h   i   j   k   l   m      G  Nglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          å   ,           	·            uokay            Ø   Q      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy               ú        À         ¸            
  cunipro mp           	·          	  udisabled          gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm                        @         ¸   n          0  e      �             Œ             ‹               Éjob mmu gpu         
#   o      (  å   ,   
   ,      ,      ,      ,           
7core0 core1 core2 core3 core4         	  udisabled          clock-controller@13fbf000             mediatek,mt8195-mfgcfg              ûð                «           Ø   n      syscon@14000000           mediatek,mt8195-vppsys0 syscon                                «           
J   p                   Ø         dma-controller@14001000           mediatek,mt8195-mdp3-rdma                                
J   p                  
b              
v   q        å   ,           
ƒ   r   €        ¸            <  þ   p         p         p         p         p              
Š         display@14002000              mediatek,mt8195-mdp3-fg                               
J   p                   ¸             display@14003000              mediatek,mt8195-mdp3-stitch              0                
J   p      0            ¸            display@14004000              mediatek,mt8195-mdp3-hdr                 @                
J   p      @            ¸      "      display@14005000              mediatek,mt8195-mdp3-aal                 P                e      F               
J   p      P            ¸      
        å   ,         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                
J   p      `            
b    %        ¸            display@14007000              mediatek,mt8195-mdp3-tdshp               p                
J   p      p            ¸      #      display@14008000              mediatek,mt8195-mdp3-color               €                e      I               
J   p      €            ¸      $        å   ,         display@14009000              mediatek,mt8195-mdp3-ovl                 �                e      J               
J   p      �            ¸      %        å   ,           
ƒ   r   ‚      display@1400a000              mediatek,mt8195-mdp3-padding                                  
J   p                   ¸              å   ,         display@1400b000              mediatek,mt8195-mdp3-tcc                 °                
J   p      °            ¸            dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot              À                
J   p      À            
b    +        ¸              
ƒ   r   ƒ        å   ,           
Š         mutex@1400f000            mediatek,mt8195-vpp-mutex                ð                e      P               
J   p      ð            ¸              å   ,         smi@14010000              mediatek,mt8195-smi-sub-common                               ¸                          capb smi gals0           
•   s        å   ,           Ø   t      smi@14011000              mediatek,mt8195-smi-sub-common                              ¸                          capb smi gals0           
•   s        å   ,           Ø   ‘      smi@14012000              mediatek,mt8195-smi-common-vpp                                ¸                                capb smi gals0 gals1         å   ,           Ø   s      larb@14013000             mediatek,mt8195-smi-larb                0                
¢           
•   t        ¸                    capb smi         å   ,           Ø   w      iommu@14018000            mediatek,mt8195-iommu-vpp               €              8  
³   u   v   w   x   y   z   {   |   }   ~      €   �   ‚        e      R               ¸              cbclk            ¾           å   ,           Ø   r      clock-controller@14e00000             mediatek,mt8195-wpesys              à                 «           Ø         clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0             à                 «         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1             à0                «         larb@14e04000             mediatek,mt8195-smi-larb                à@                
¢           
•   ƒ        ¸                    capb smi         å   ,           Ø   ˜      larb@14e05000             mediatek,mt8195-smi-larb                àP                
¢           
•   s        ¸                          capb smi gals            å   ,           Ø   y      syscon@14f00000           mediatek,mt8195-vppsys1 syscon              ð                 «           
J   p   	               Ø         mutex@14f01000            mediatek,mt8195-vpp-mutex               ð                e      {               
J   p   	              ¸      '        å   ,         larb@14f02000             mediatek,mt8195-smi-larb                ð                 
¢           
•   ƒ        ¸                          capb smi gals            å   ,           Ø   —      larb@14f03000             mediatek,mt8195-smi-larb                ð0                
¢           
•   t        ¸                          capb smi gals            å   ,           Ø   x      display@14f06000              mediatek,mt8195-mdp3-split              ð`                
J   p   	  `            ¸            +      ,        å   ,         display@14f07000              mediatek,mt8195-mdp3-tcc                ðp                
J   p   	  p            ¸            dma-controller@14f08000           mediatek,mt8195-mdp3-rdma               ð€                
J   p   	  €            
b  „  ¨        ¸              
ƒ   „            å   ,           
Š         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma               ð�                
J   p   	  �            
b  …  ©        ¸      
        
ƒ   „   ¤        å   ,           
Š         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma               ð                 
J   p   	               
b  †  ª        ¸              
ƒ   r   À        å   ,           
Š         display@14f0b000              mediatek,mt8195-mdp3-fg             ð°                
J   p   	  °            ¸      	      display@14f0c000              mediatek,mt8195-mdp3-fg             ðÀ                
J   p   	  À            ¸            display@14f0d000              mediatek,mt8195-mdp3-fg             ðÐ                
J   p   	  Ð            ¸            display@14f0e000              mediatek,mt8195-mdp3-hdr                ðà                
J   p   	  à            ¸            display@14f0f000              mediatek,mt8195-mdp3-hdr                ðð                
J   p   	  ð            ¸            display@14f10000              mediatek,mt8195-mdp3-hdr                ñ                 
J   p   
               ¸             display@14f11000              mediatek,mt8195-mdp3-aal                ñ                e      i               
J   p   
              ¸              å   ,         display@14f12000              mediatek,mt8195-mdp3-aal                ñ                 e      j               
J   p   
               ¸              å   ,         display@14f13000              mediatek,mt8195-mdp3-aal                ñ0                e      k               
J   p   
  0            ¸      !        å   ,         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñ@                
J   p   
  @            
b  �  ¯        ¸            display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñP                
J   p   
  P            
b  ‘  °        ¸      $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñ`                
J   p   
  `            
b  ’  ±        ¸      %      display@14f17000              mediatek,mt8195-mdp3-tdshp              ñp                
J   p   
  p            ¸            display@14f18000              mediatek,mt8195-mdp3-tdshp              ñ€                
J   p   
  €            ¸      (      display@14f19000              mediatek,mt8195-mdp3-tdshp              ñ�                
J   p   
  �            ¸      )      display@14f1a000              mediatek,mt8195-mdp3-merge              ñ                 
J   p   
               ¸              å   ,         display@14f1b000              mediatek,mt8195-mdp3-merge              ñ°                
J   p   
  °            ¸              å   ,         display@14f1c000              mediatek,mt8195-mdp3-color              ñÀ                e      t               
J   p   
  À            ¸              å   ,         display@14f1d000              mediatek,mt8195-mdp3-color              ñÐ                
J   p   
  Ð            e      u               ¸              å   ,         display@14f1e000              mediatek,mt8195-mdp3-color              ñà                e      v               
J   p   
  à            ¸              å   ,         display@14f1f000              mediatek,mt8195-mdp3-ovl                ñð                e      w               
J   p   
  ð            ¸               å   ,           
ƒ   „   ¢      display@14f20000              mediatek,mt8195-mdp3-padding                ò                 
J   p                  ¸              å   ,         display@14f21000              mediatek,mt8195-mdp3-padding                ò                
J   p                 ¸              å   ,         display@14f22000              mediatek,mt8195-mdp3-padding                ò                 
J   p                  ¸              å   ,         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             ò0                
J   p     0            
b  Ÿ  «        ¸              
ƒ   „   £        å   ,           
Š         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             ò@                
J   p     @            
b     ¬        ¸              
ƒ   „   ¦        å   ,           
Š         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             òP                
J   p     P            
b  ¡  ­        ¸              
ƒ   r   Â        å   ,           
Š         clock-controller@15000000             mediatek,mt8195-imgsys                                «           Ø   %      larb@15001000             mediatek,mt8195-smi-larb                                 
¢   	        
•   …        ¸   %       %       %   
        capb smi gals            å   ,           Ø   ™      smi@15002000              mediatek,mt8195-smi-sub-common                                ¸   %      %                 capb smi gals0           
•   s        å   ,           Ø   ˆ      smi@15003000              mediatek,mt8195-smi-sub-common               0                ¸   %       %       %   
        capb smi gals0           
•   ƒ        å   ,           Ø   …      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top                              «           Ø   †      larb@15120000             mediatek,mt8195-smi-larb                                 
¢   
        
•   …        ¸   %      †            capb smi         å   ,           Ø   š      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr                               «         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe             "                 «           Ø   ‡      larb@15230000             mediatek,mt8195-smi-larb                #                 
¢           
•   …        ¸   %      ‡            capb smi         å   ,           Ø   ›      clock-controller@15330000             mediatek,mt8195-ipesys              3                 «           Ø   &      larb@15340000             mediatek,mt8195-smi-larb                4                 
¢           
•   ˆ        ¸   &      &           capb smi         å   ,           Ø   z      clock-controller@16000000             mediatek,mt8195-camsys                                «           Ø   '      larb@16001000             mediatek,mt8195-smi-larb                                 
¢           
•   ‰        ¸   '       '       '           capb smi gals            å   ,           Ø   œ      larb@16002000             mediatek,mt8195-smi-larb                                  
¢           
•   Š        ¸   '      '           capb smi         å   ,           Ø   {      smi@16004000              mediatek,mt8195-smi-sub-common               @                ¸   '       '       '           capb smi gals0           
•   ƒ        å   ,           Ø   ‰      smi@16005000              mediatek,mt8195-smi-sub-common               P                ¸   '      '                 capb smi gals0           
•   s        å   ,           Ø   Š      larb@16012000             mediatek,mt8195-smi-larb                                 
¢           
•   Š        ¸   ‹       ‹            capb smi         å   ,            Ø   |      larb@16013000             mediatek,mt8195-smi-larb                0                
¢           
•   ‰        ¸   Œ       Œ            capb smi         å   ,            Ø   �      larb@16014000             mediatek,mt8195-smi-larb                @                
¢           
•   Š        ¸   �       �            capb smi         å   ,   !        Ø   ‚      larb@16015000             mediatek,mt8195-smi-larb                P                
¢           
•   ‰        ¸   Ž       Ž            capb smi         å   ,   !        Ø   ¢      clock-controller@1604f000             mediatek,mt8195-camsys_rawa             ð                «           Ø   ‹      clock-controller@1606f000             mediatek,mt8195-camsys_yuva             ð                «           Ø   Œ      clock-controller@1608f000             mediatek,mt8195-camsys_rawb             ð                «           Ø   �      clock-controller@160af000             mediatek,mt8195-camsys_yuvb             
ð                «           Ø   Ž      clock-controller@16140000             mediatek,mt8195-camsys_mraw                              «           Ø   �      larb@16141000             mediatek,mt8195-smi-larb                                
¢           
•   ‰        ¸   '       �       '           capb smi gals            å   ,   "        Ø   ¡      larb@16142000             mediatek,mt8195-smi-larb                                 
¢           
•   Š        ¸   �       �            capb smi         å   ,   "        Ø   �      clock-controller@17200000             mediatek,mt8195-ccusys                                «           Ø   �      larb@17201000             mediatek,mt8195-smi-larb                                 
¢           
•   Š        ¸   �       �            capb smi         å   ,           Ø   }      video-codec@18000000              mediatek,mt8195-vcodec-dec          
v   q        
ƒ   „                        +                               @                !                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc                                
ƒ   r  à   r  á         ¸      A                  �        csel vdec lat top            ™      A        ©      �        å   ,         video-codec@10000             mediatek,mtk-vcodec-lat                               e      Ä             0  
ƒ   „      „     „     „     „     „           ¸      A                  �        csel vdec lat top            ™      A        ©      �        å   ,         video-codec@25000             mediatek,mtk-vcodec-core                 P                e      Ã             P  
ƒ   „      „  ¡   „  ¢   „  £   „  ¤   „  ¥   „  ¦   „  §   „  ¨   „  ©         ¸      A                    �        csel vdec lat top            ™      A        ©      �        å   ,            larb@1800d000             mediatek,mt8195-smi-larb                 Ð                
¢           
•   ƒ        ¸                      capb smi         å   ,           Ø          larb@1800e000             mediatek,mt8195-smi-larb                 à                
¢           
•   ‘        ¸                     capb smi         å   ,           Ø   €      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc              ð                «           Ø         larb@1802e000             mediatek,mt8195-smi-larb                à                
¢           
•   ƒ        ¸                        capb smi         å   ,           Ø   Ÿ      clock-controller@1802f000             mediatek,mt8195-vdecsys             ð                «           Ø          larb@1803e000             mediatek,mt8195-smi-larb                à                
¢           
•   ‘        ¸         !            capb smi         å   ,           Ø         clock-controller@1803f000             mediatek,mt8195-vdecsys_core1               ð                «           Ø   !      clock-controller@190f3000             mediatek,mt8195-apusys_pll              0                «         clock-controller@1a000000             mediatek,mt8195-vencsys                               «           Ø   "      larb@1a010000             mediatek,mt8195-smi-larb                                 
¢           
•   ƒ        ¸   "      "           capb smi         å   ,           Ø   ž      video-codec@1a020000              mediatek,mt8195-vcodec-enc                             H  
ƒ   „  `   „  a   „  b   „  c   „  d   „  v   „  w   „  x   „  y        e      U               
v   q        ¸   "         	  cvenc_sel            ™      @        ©      �        å   ,                        +         jpgdec-master             mediatek,mt8195-jpgdec          å   ,         0  
ƒ   „  m   „  n   „  r   „  s   „  t   „  u                     +            !   jpgdec@1a040000           mediatek,mt8195-jpgdec-hw                              0  
ƒ   „  m   „  n   „  r   „  s   „  t   „  u        e      W               ¸   "           cjpgdec          å   ,         jpgdec@1a050000           mediatek,mt8195-jpgdec-hw                              0  
ƒ   „  m   „  n   „  r   „  s   „  t   „  u        e      X               ¸   "           cjpgdec          å   ,         jpgdec@1b040000           mediatek,mt8195-jpgdec-hw                              0  
ƒ   r  �   r  Ž   r  ’   r  “   r  ”   r  •        e      \               ¸   #           cjpgdec          å   ,            clock-controller@1b000000             mediatek,mt8195-vencsys_core1                                 «           Ø   #      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon                                 þ   ’               «           
J   ’                  Ø         jpgenc-master             mediatek,mt8195-jpgenc          å   ,            
ƒ   r  ‡   r  ˆ   r  ‰   r  Œ                     +            !   jpgenc@1a030000           mediatek,mt8195-jpgenc-hw                                 
ƒ   „  g   „  h   „  i   „  l        e      V               ¸   "           cjpgenc          å   ,         jpgenc@1b030000           mediatek,mt8195-jpgenc-hw                                 
ƒ   r  ‡   r  ˆ   r  ‰   r  Œ        e      [               ¸   #           cjpgenc          å   ,            larb@1b010000             mediatek,mt8195-smi-larb                                 
¢           
•   s        ¸   #      #                  capb smi gals            å   ,           Ø   ~      ovl@1c000000              mediatek,mt8195-disp-ovl                                  e      |               å   ,           ¸               
ƒ   „           
J   ’                rdma@1c002000             mediatek,mt8195-disp-rdma                                 e      ~               å   ,           ¸              
ƒ   „            
J   ’                color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color                0                e                     å   ,           ¸              
J   ’     0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr                @                e      €               å   ,           ¸              
J   ’     @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal                P                e      �               å   ,           ¸              
J   ’     P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma                `                e      ‚               å   ,           ¸              
J   ’     `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither              p                e      ƒ               å   ,           ¸      	        
J   ’     p          dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi              €                e      „               å   ,           ¸            *   “        cengine digital hs           j   “        	‡dphy          	  udisabled          dsc@1c009000              mediatek,mt8195-disp-dsc                 �                e      …               å   ,           ¸              
J   ’     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                              e      Ž               å   ,           ¸            +   ”        cengine digital hs           j   ”        	‡dphy          	  udisabled          merge@1c014000            mediatek,mt8195-disp-merge              @                e      �               å   ,           ¸              
J   ’     @          dp-intf@1c015000              mediatek,mt8195-dp-intf             P                e      ‘               ¸      ,                    cpixel engine pll          	  udisabled          mutex@1c016000            mediatek,mt8195-disp-mutex              `                e      ’               å   ,           ¸              
J   ’     `            
b  U      larb@1c018000             mediatek,mt8195-smi-larb                €                
¢            
•   ƒ        ¸      (      (              capb smi gals            å   ,           Ø   •      larb@1c019000             mediatek,mt8195-smi-larb                �                
¢           
•   s        ¸      (                     capb smi gals            å   ,           Ø   u      syscon@1c100000           mediatek,mt8195-vdosys1 syscon                               þ   ’              
J   ’                  «           y           Ø   $      smi@1c01b000              mediatek,mt8195-smi-common-vdo              °                 ¸      %      &      )      $        capb smi gals0 gals1         å   ,           Ø   ƒ      iommu@1c01f000            mediatek,mt8195-iommu-vdo               ð              8  
³   •   –   —   ˜   ™   š   ›   œ   �   ž   Ÿ       ¡   ¢        e      �               ¾           ¸      '        cbclk            å   ,           Ø   „      mutex@1c101000            mediatek,mt8195-disp-mutex                              e      î               å   ,           ¸   $           
J   ’                 
b  À      larb@1c102000             mediatek,mt8195-smi-larb                                 
¢           
•   ƒ        ¸   $       $       $           capb smi gals            å   ,           Ø   –      larb@1c103000             mediatek,mt8195-smi-larb                0                
¢           
•   s        ¸   $      $                  capb smi gals            å   ,           Ø   v      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma               @                e      ï               ¸   $           å   ,           
ƒ   „   @        
J   ’     @            
Š         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma               P                e      ð               ¸   $           å   ,           
ƒ   r   `        
J   ’     P            
Š         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma               `                e      ñ               ¸   $           å   ,           
ƒ   „   A        
J   ’     `            
Š         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma               p                e      ò               ¸   $           å   ,           
ƒ   r   a        
J   ’     p            
Š         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma               €                e      ó               ¸   $           å   ,           
ƒ   „   B        
J   ’     €            
Š         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma               �                e      ô               ¸   $           å   ,           
ƒ   r   b        
J   ’     �            
Š         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma                                e      õ               ¸   $           å   ,           
ƒ   „   C        
J   ’                  
Š         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma               °                e      ö               ¸   $           å   ,           
ƒ   r   c        
J   ’     °            
Š         vpp-merge@1c10c000            mediatek,mt8195-disp-merge              À                e      ÷               ¸   $   	   $           cmerge merge_async           å   ,           
J   ’     À             
Â           $         vpp-merge@1c10d000            mediatek,mt8195-disp-merge              Ð                e      ø               ¸   $   
   $           cmerge merge_async           å   ,           
J   ’     Ð             
Â           $         vpp-merge@1c10e000            mediatek,mt8195-disp-merge              à                e      ù               ¸   $      $           cmerge merge_async           å   ,           
J   ’     à             
Â           $         vpp-merge@1c10f000            mediatek,mt8195-disp-merge              ð                e      ú               ¸   $      $           cmerge merge_async           å   ,           
J   ’     ð             
Â           $         vpp-merge@1c110000            mediatek,mt8195-disp-merge                               e      û               ¸   $      $           cmerge merge_async           å   ,           
J   ’                   
Ö           $         dp-intf@1c113000              mediatek,mt8195-dp-intf             0                e                     å   ,           ¸   $   /   $                 cpixel engine pll          	  udisabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p      @            P            p            �                         °            À              4  †mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  
J   ’     @       ’     P       ’     p       ’     �       ’             ’     °       ’     À          h  ¸   $   %   $       $   #   $   !   $   $   $   "   $   1   $   &   $   '   $   (   $   )   $   *            ƒ  cmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          å   ,           
ƒ   r   d   r   e        e                   (     $   3   $   4   $   5   $   6   $   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx              P        €         B   £        Ndp_calibration_data         å   ,           e      ¤               
í  ¤      	  udisabled          dp-tx@1c600000            mediatek,mt8195-dp-tx               `        €         B   £        Ndp_calibration_data         å   ,           e      Ê               
í  ¤      	  udisabled             thermal-zones      cpu0-thermal            
þ  è           ú        "   ¤      trips      trip-alert          2 L        >  Ð        passive         Ø   ¥      trip-crit           2 †         >  Ð      	  critical             cooling-maps       map0            I   ¥      0  N   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            
þ  è           ú        "   ¤      trips      trip-alert          2 L        >  Ð        passive         Ø   ¦      trip-crit           2 †         >  Ð      	  critical             cooling-maps       map0            I   ¦      0  N   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            
þ  è           ú        "   ¤      trips      trip-alert          2 L        >  Ð        passive         Ø   §      trip-crit           2 †         >  Ð      	  critical             cooling-maps       map0            I   §      0  N   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            
þ  è           ú        "   ¤      trips      trip-alert          2 L        >  Ð        passive         Ø   ¨      trip-crit           2 †         >  Ð      	  critical             cooling-maps       map0            I   ¨      0  N   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            
þ  è           ú        "   ¤       trips      trip-alert          2 L        >  Ð        passive         Ø   ©      trip-crit           2 †         >  Ð      	  critical             cooling-maps       map0            I   ©      0  N   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            
þ  è           ú        "   ¤      trips      trip-alert          2 L        >  Ð        passive         Ø   ª      trip-crit           2 †         >  Ð      	  critical             cooling-maps       map0            I   ª      0  N   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            
þ  è           ú        "   ¤      trips      trip-alert          2 L        >  Ð        passive         Ø   «      trip-crit           2 †         >  Ð      	  critical             cooling-maps       map0            I   «      0  N   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            
þ  è           ú        "   ¤      trips      trip-alert          2 L        >  Ð        passive         Ø   ¬      trip-crit           2 †         >  Ð      	  critical             cooling-maps       map0            I   ¬      0  N   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            
þ  è           ú        "   ­      trips      trip-alert          2 L        >  Ð        passive       trip-crit           2 †         >  Ð      	  critical                vpu1-thermal            
þ  è           ú        "   ­   	   trips      trip-alert          2 L        >  Ð        passive       trip-crit           2 †         >  Ð      	  critical                gpu-thermal         
þ  è           ú        "   ­   
   trips      trip-alert          2 L        >  Ð        passive       trip-crit           2 †         >  Ð      	  critical                gpu1-thermal            
þ  è           ú        "   ­      trips      trip-alert          2 L        >  Ð        passive       trip-crit           2 †         >  Ð      	  critical                vdec-thermal            
þ  è           ú        "   ­      trips      trip-alert          2 L        >  Ð        passive       trip-crit           2 †         >  Ð      	  critical                img-thermal         
þ  è           ú        "   ­      trips      trip-alert          2 L        >  Ð        passive       trip-crit           2 †         >  Ð      	  critical                infra-thermal           
þ  è           ú        "   ­      trips      trip-alert          2 L        >  Ð        passive       trip-crit           2 †         >  Ð      	  critical                cam0-thermal            
þ  è           ú        "   ­      trips      trip-alert          2 L        >  Ð        passive       trip-crit           2 †         >  Ð      	  critical                cam1-thermal            
þ  è           ú        "   ­      trips      trip-alert          2 L        >  Ð        passive       trip-crit           2 †         >  Ð      	  critical                   chosen          ]serial0:921600n8          firmware       optee             linaro,optee-tz         smc          memory@40000000          ûmemory              @                reserved-memory                      +            !   optee@43200000           i            C        À        memory@50000000           shared-dma-pool             P       �           i        Ø   *      memory@53000000           shared-dma-pool             S       @        memory@54600000          i            T`                memory@60000000           shared-dma-pool             `                  i      memory@62000000           shared-dma-pool             b       @           backlight-lcd0            pwm-backlight           p   ®     ¡         u      /            ‚      ÿ        ”  ÿ        «  @      backlight-lcd1            pwm-backlight           p   ¯     ¡         u      .            ‚      ÿ        ”  ÿ        «  @      can-clk           fixed-clock         «            -1-         Ôcan-clk         Ø   7      regulator-0           regulator-fixed         "edp_panel_3v3           1 2Z         I 2Z          Ä        b                  4default         *   °      regulator-1           regulator-fixed         "edp_backlight_12v           1 ·         I ·          Ä        b      `            4default         *   ±      gpio-keys         
    gpio-keys      button-volume-up             o        ×   d        —      j         
  évolume_up           ï   s         regulator-2           regulator-fixed       	  "wifi_3v3            1 2Z         I 2Z         b      ‡             Ä         }         	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 ethernet0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux output-high drive-strength input-enable input-disable bias-disable bias-pull-up drive-strength-microamp bias-pull-down output-low #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents interrupts-extended #io-channel-cells mediatek,mic-type-0 mediatek,mic-type-1 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells memory-region power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-0 pinctrl-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select cs-gpios spi-max-frequency vdd-supply xceiver-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle snps,reset-gpio snps,reset-delays-us mediatek,tx-delay-ps mediatek,mac-wol pinctrl-1 snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup vusb33-supply bus-width cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN3-supply irq-gpios reset-gpios AVDD28-supply mediatek,force-mode operating-points-v2 power-domain-names mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path no-map pwms enable-gpios brightness-levels num-interpolated-steps default-brightness-level enable-active-high debounce-interval label linux,code 